CN110955179A - Dual-channel shared clock trigger delay adjusting device based on PCI bus - Google Patents
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Abstract
本发明公开了一种基于PCI总线的双通道共享时钟触发调延装置，先通过外接的时钟和触发源通过信号输入接口给调延控制模块提供时钟信号和触发信号；同时，控制设备通过PCI总线发送调延参数到调延控制模块，通过调延控制模块的PCI接口输入至参数解析模块，最后根据解析值对时钟信号和触发信号进行延时调整，以此来补偿测量系统自身延时造成的测量不同步问题，从而使测量系统的测量同步精度更高。
The invention discloses a dual-channel shared clock trigger delay adjustment device based on a PCI bus, which firstly provides a clock signal and a trigger signal to a delay adjustment control module through an external clock and a trigger source through a signal input interface; Send the delay adjustment parameters to the delay adjustment control module, input them to the parameter analysis module through the PCI interface of the delay adjustment control module, and finally adjust the delay of the clock signal and trigger signal according to the analysis value to compensate for the delay caused by the measurement system itself. The measurement is not synchronized, so that the measurement synchronization accuracy of the measurement system is higher.
Description
Technical Field
The invention belongs to the technical field of synchronous measurement, and particularly relates to a dual-channel shared clock trigger delay device based on a PCI bus.
Background
Measurement is a means for people to know the unknown world, and measurement data is an information source for people to judge things. In some measurement fields, there is a very high accuracy requirement for consistency of measurement time, i.e. synchronous measurement of multiple or multiple devices is required. The synchronous measurement is beneficial to improving the measurement precision, realizes the multi-directional measurement of the transient signal, and has wide application in the aspects of transient signal monitoring, emission source positioning and the like.
There are many common multi-device synchronous measurement methods, and most of them have a representative measurement method with a master control command, a measurement method with a unified relative time base and a measurement method with a unified absolute time base.
The main control equipment sends commands to all measuring instruments in the measuring process of the main control command measuring method, and all measuring instruments immediately start measuring after receiving the commands. The method has the advantages of simple operation, easy realization, low synchronization precision, and different transmission delays caused by different transmission distances and transmission media between the main control equipment and each measuring instrument.
In the measurement process of the measurement method of the unified relative Time base, the relative Time synchronization among a plurality of instruments is realized by a Network Time Protocol (NTP) or a Precision Time Protocol (PTP), and the unified Time synchronization is set to trigger the measurement. The method has the advantages of complex hardware structure, large software workload and large influence of network conditions on errors.
The measurement process of the measurement method of the unified absolute time base is to realize accurate time service by utilizing a GPS and set the unified time to synchronously trigger measurement. The method generally uses a digital phase-locked loop to realize the clock synchronization with the GPS, and has complex hardware design and difficult realization.
The three multi-equipment synchronous measurement methods can achieve simultaneous triggering of the measurement instruments under the optimal condition. However, there is a delay between triggering and actual acquisition of the instrument, the delay times of different instruments are different, and the error caused by the delay cannot be ignored under the condition of high requirement on synchronization accuracy.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a dual-channel shared clock trigger delay adjusting device based on a PCI bus, which compensates the problem of measurement asynchronism caused by the self delay of a measurement system by delaying a clock signal and a trigger signal, so that the measurement synchronization precision of the measurement system is higher.
In order to achieve the above object, the present invention provides a dual channel shared clock trigger delay apparatus based on PCI bus, comprising:
the PCI bus is used for transmitting the delay parameter of the control equipment to the device and supplying power to each module in the device;
the power module supplies power to the whole device through a PCI bus;
the signal input and output interface is used for inputting and outputting an external clock signal and a trigger signal by the device;
the delay control module is realized by an FPGA (field programmable gate array), and the main functions of the FPGA comprise a parameter analysis module, a frequency multiplication module, a frequency divider, a shunt module, a counter and a register set; the method has the main functions that under the action of an external clock signal and a trigger signal, delay and rough adjustment is carried out on delay parameters;
the accurate delay module comprises four clock delay chips, wherein two of the clock delay chips are used for accurately adjusting the delay of the trigger signal, and the other two clock delay chips are used for accurately adjusting the delay of the clock signal;
the work flow of the double-channel shared clock triggering delay adjusting device is as follows:
an external clock and a trigger source provide a clock signal and a trigger signal for the delay control module through a signal input interface;
meanwhile, the control equipment sends a DELAY parameter to the DELAY control module through a PCI bus, the DELAY parameter is input to the parameter analysis module through a PCI interface of the DELAY control module, and the parameter analysis module analyzes the DELAY parameter into an enable signal EN, a channel 1 clock frequency CH1_ CLK, a channel 2 clock frequency CH2_ CLK, a channel 2 clock DELAY time CLK _ DELAY, a channel 2 trigger DELAY time TRIG _ DELAY and reserved data and respectively stores the data into corresponding registers;
after a new value in the register group is written into a corresponding register every time, reading the value of each register by the FPGA, when the value of an EN register is read to be 0 xfffffffff, multiplying the frequency of the received clock signal by a frequency multiplication module by the FPGA, dividing the frequency of the frequency-multiplied clock signal by a frequency divider according to the values in the registers CH1_ CLK and CH2_ CLK to generate two paths of clock signals, and then performing clock DELAY rough adjustment by using a counter 1 according to the value in the CLK _ DELAY register; meanwhile, the FPGA divides the received trigger signals into two paths through a shunt module, and then the two paths of trigger signals are subjected to DELAY coarse adjustment by using a counter 2 according to the value in a TRIG _ DELAY register; and finally, transmitting the four paths of signals after DELAY coarse adjustment to an accurate DELAY module, wherein two paths of clock signals are respectively input to the two clock DELAY chips, two paths of trigger signals are respectively input to the two trigger DELAY chips, then controlling four groups of DELAY chips by the FPGA according to values in CLK _ DELAY and TRIG _ DELAY registers, carrying out DELAY fine adjustment on the signals input by the four groups of DELAY chips, and finally outputting the signals through a signal output interface.
The invention aims to realize the following steps:
the invention relates to a dual-channel shared clock trigger delay device based on a PCI bus, which is characterized in that a clock signal and a trigger signal are provided for a delay control module through an external clock and a trigger source through a signal input interface; meanwhile, the control equipment sends a delay parameter to the delay control module through a PCI bus, the delay parameter is input to the parameter analysis module through a PCI interface of the delay control module, and finally, the clock signal and the trigger signal are subjected to delay adjustment according to the analysis value so as to compensate the problem of asynchronous measurement caused by the self delay of the measurement system, so that the measurement synchronization precision of the measurement system is higher.
Meanwhile, the two-channel shared clock triggering delay device based on the PCI bus also has the following beneficial effects:
(1) the PCI bus interface is used, so that the advantages of high speed and plug-and-play performance are achieved, and the conflict among the board cards is not worried;
(2) because the delay time from triggering to collecting of the instrument is related to the hardware characteristics of the instrument, the delay is relatively fixed, the invention compensates the asynchronous measurement problem caused by the delay of the measurement system by delaying the input clock and the trigger signal, so that the measurement synchronization precision of the measurement system is higher;
(3) the invention has no requirement on the frequency of the input clock signal, and the frequency of the output clock signal can be set;
(4) the invention has extremely high delay precision which can reach nanosecond level.
Drawings
FIG. 1 is a diagram of an embodiment of a two-channel shared clock triggered delay apparatus according to the present invention;
FIG. 2 is a circuit schematic of a power supply module;
FIG. 3 is a circuit schematic of the precision delay module;
FIG. 4 is a schematic diagram of the internal design of an FPGA chip;
fig. 5 is a schematic diagram of the delay principle.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
Examples
Fig. 1 is an architecture diagram of an embodiment of a dual-channel shared clock triggered delay apparatus based on a PCI bus according to the present invention.
In this embodiment, as shown in fig. 1, the dual-channel shared clock trigger delay apparatus based on the PCI bus of the present invention includes: the system comprises a PCI bus, a power supply module, a signal input interface, a signal output interface and a delay control module, and is mainly used for two close-range systems to be measured;
the PCI bus is used for transmitting the delay parameter of the control equipment to the device and supplying power to each module in the device;
the power module supplies power to the whole device through a PCI bus;
the PCI bus needs to provide 3.3V, 5V, ± 12V power for each module, thus requiring the power modules to provide 3.3V, 2.5V and 1.2V power inputs. Compared with 2.5V and 1.2V power supplies, the two LDO power supply chips LT1963 and LT1764 of Linte company are adopted to generate 2.5V and 1.2V respectively, and the circuit schematic diagram is shown in FIG. 2.
The signal input and output interface is used for inputting and outputting an external clock signal and a trigger signal by the device;
the delay control module is realized by an FPGA (field programmable gate array), and the main functions of the FPGA comprise a parameter analysis module, a frequency multiplication module, a frequency divider, a shunt module, a counter and a register set; the method has the main functions of carrying out delay coarse adjustment on a clock signal and a trigger signal according to a delay parameter;
in this embodiment, the delay control module uses an FPGA as a control core. In this example, an EP3C10F256 chip of Cyclone III series of Altera was selected. The Cyclone III series has the following characteristics: (1) the method has advanced IP core support; (2) the PLL can output 200MHz main frequency; (3) the device has higher performance and lower power consumption; (4) the reliability of the system is greatly improved.
The EP3C10F256 chip has 10320 logic cells, 414kb RAM, 2 PLLs, 10 global clock networks, i.e. at most 182 user I/O. The chip has abundant resources, the dominant frequency is up to more than 200MHz, and the clock delay control and logic design can be completely met.
Theoretically, the FPGA can generate clock signals in the frequency range of 0-100MHz, and the requirements of the embodiment are completely met. The dominant frequency is designed to be 200MHz, namely the precision can reach 5 ns.
The accurate delay module comprises four clock delay chips, wherein two of the clock delay chips are used for accurately adjusting the delay of the trigger signal, and the other two clock delay chips are used for accurately adjusting the delay of the clock signal;
in the embodiment, the precise delay module adopts a group of DS1123L-200 chips of Dallas corporation to realize precise delay. The chip has the following characteristics: (1) 8-bit programmable delay control; (2) having serial and parallel communication interfaces; (3) the time delay in the range of 0-510ns can be realized, and the step is 2 ns.
The work flow of the double-channel shared clock triggering delay adjusting device is as follows:
an external clock and a trigger source provide a clock signal and a trigger signal for the delay control module through a signal input interface;
meanwhile, the control equipment sends a DELAY parameter to the DELAY control module through a PCI bus, the DELAY parameter is input to the parameter analysis module through a PCI interface of the DELAY control module, and the parameter analysis module analyzes the DELAY parameter into an enable signal EN, a channel 1 clock frequency CH1_ CLK, a channel 2 clock frequency CH2_ CLK, a channel 2 clock DELAY time CLK _ DELAY, a channel 2 trigger DELAY time TRIG _ DELAY and reserved data and respectively stores the data into corresponding registers;
after a new value in the register group is written into a corresponding register every time, reading the value of each register by the FPGA, when the value of an EN register is read to be 0 xfffffffff, multiplying the frequency of the received clock signal by a frequency multiplication module by the FPGA, dividing the frequency of the frequency-multiplied clock signal by a frequency divider according to the values in the registers CH1_ CLK and CH2_ CLK to generate two paths of clock signals, and then performing clock DELAY rough adjustment by using a counter 1 according to the value in the CLK _ DELAY register; meanwhile, the FPGA divides the received trigger signals into two paths through a shunt module, and then the two paths of trigger signals are subjected to DELAY coarse adjustment by using a counter 2 according to the value in a TRIG _ DELAY register; and finally, transmitting the four paths of signals after DELAY coarse adjustment to an accurate DELAY module, wherein two paths of clock signals are respectively input to the two clock DELAY chips, two paths of trigger signals are respectively input to the two trigger DELAY chips, then controlling four groups of DELAY chips by the FPGA according to values in CLK _ DELAY and TRIG _ DELAY registers, carrying out DELAY fine adjustment on the signals input by the four groups of DELAY chips, and finally outputting the signals through a signal output interface for a measurement system.
In the invention, two groups of delayed clock signals and trigger signals can be simultaneously output, so that the method can be used for two groups of measuring systems with close distances.
Fig. 3 is a circuit schematic of the precision delay module.
In the embodiment, the FPGA realizes the first-stage coarse delay, and then the DS1123L-200 chip realizes the second-stage precise delay, the chip steps by 2ns at the minimum, the chip is simple to control, and the requirement can be completely met. The 2 clock signals and 2 trigger signals are designed to be 4 signals in total to realize delay control, and the circuit schematic diagram is shown in fig. 3, wherein the two circuits on the left are the circuit schematic diagrams for realizing the clock signal delay control, and the two circuits on the right are the circuit schematic diagrams for realizing the trigger signal delay control.
FIG. 4 is a schematic diagram of the internal design of an FPGA chip.
The FPGA receives and analyzes PCI transmitted data, and the data is divided into six data, namely an enabling signal, the clock frequency of the channel 1, the clock frequency of the channel 2, the clock delay time of the channel 2, the trigger delay time of the channel 2 and reserved data.
An input clock is 10MHz, and a 200MHz main frequency signal is generated by frequency multiplication through a PLL core, so that the internal delay of the FPGA chip is based on the main frequency signal, the period of the main frequency signal is 5ns, and the minimum delay step is 5 ns.
After receiving PCI incoming data, the data is stored in the corresponding six registers.
When the read enable register value is 0xffffffff, the FPGA firstly divides the clock signal according to the values in the CH1_ CLK register and the CH2_ CLK register to generate two paths of clock signals. Since the main frequency is 200MHz, only integer multiple frequency division can be obtained. If a clock output with other frequencies is desired, the code needs to be changed to change the main frequency to other frequencies.
Fig. 5 is a schematic diagram of the delay principle.
In the present embodiment, the counters 1 and 2 in fig. 1 each include A, B two sets of counters; the clock signal before the delay is detected for its edge, and after the edge is detected, a counter is used to count. As shown in fig. 5, the specific process is as follows: and after the rising edge of the clock is detected, changing the counting number of the counter B according to the delay time transmitted by the PCI interface, and after the counting of the counter A is finished, setting the output high. And after the falling edge of the clock is detected, changing the counting number of the counter B according to the delay time transmitted by the PCI interface, and after the counting of the counter A is finished, setting the output to be low. Thus, one cycle of the delay operation is completed.
From the principle of delay, it can be appreciated that the delay time should not exceed the length of one cycle. Since the clock is a periodic signal, a delay of more than one period is not meaningful. And if the delay time is greater than one clock cycle, dividing the delay time by the clock cycle for remainder. For a hardware circuit, the division circuit consumes too many resources, so that it is not suitable to design too many divisions in the hardware circuit. Therefore, the relation between the judgment delay time and the cycle size and the residue taking operation are placed on an upper computer. This saves FPGA resources.
The delay operation of the trigger is realized by detecting the rising edge and the falling edge. However, the default trigger is not a periodic signal but only a pulse signal, so that the relationship between the magnitude and the period of the delay is not determined.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.
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| CN112255533A (en) * | 2020-09-25 | 2021-01-22 | 杭州加速科技有限公司 | Device and method for improving synchronous trigger real-time performance of semiconductor tester |
| CN115129639A (en) * | 2022-06-14 | 2022-09-30 | 沐曦集成电路(南京)有限公司 | AXI bus delay adjusting device |
| CN115129639B (en) * | 2022-06-14 | 2023-10-27 | 沐曦集成电路(南京)有限公司 | Delay adjusting device of AXI bus |
| CN115361344A (en) * | 2022-07-21 | 2022-11-18 | 湖南毂梁微电子有限公司 | Signal tilt compensation device and method |
| CN115361344B (en) * | 2022-07-21 | 2023-05-12 | 湖南毂梁微电子有限公司 | Signal inclination compensation device and method |
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