CN110943126A

CN110943126A - Semiconductor structure and method of making the same

Info

Publication number: CN110943126A
Application number: CN201910900104.0A
Authority: CN
Inventors: 陈京玉; 张玮婷
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-09-21
Filing date: 2019-09-23
Publication date: 2020-03-31
Anticipated expiration: 2039-09-23
Also published as: CN110943126B

Abstract

The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof. The embodiment of the invention discloses a structure and a method for controlling dopant diffusion and activation. In one example, a semiconductor structure is disclosed. The semiconductor structure comprises: a channel layer, a barrier layer, a gate electrode, and a doped layer. The barrier layer is located above the channel layer. A gate electrode is over the barrier layer. The doped layer is formed between the barrier layer and the gate electrode. The doped layer includes an interface layer in contact with the barrier layer and a main layer between the interface layer and the gate electrode. The doping layer includes a dopant, and a doping concentration of the dopant in the interface layer is lower than a doping concentration of the dopant in the main layer.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

Embodiments of the present disclosure relate to a semiconductor structure and a method for fabricating the same, and more particularly, to a semiconductor structure for controlling dopant diffusion and activation and a method for fabricating the same.

Background

The use of High Electron Mobility Transistors (HEMTs) in power applications has become popular due to high current density, high breakdown voltage and low on-resistance. One of the major difficulties in developing high electron mobility transistors, such as normally-off (enhancement mode) high electron mobility transistors with p-type gallium nitride (GaN) gates, is controlling the out-diffusion and activation of magnesium (Mg) or other dopants in the p-type gallium nitride layer.

The key layers of a p-type gallium nitride gate hemt structure include a p-type gallium nitride layer and an aluminum gallium nitride (AlGaN)/gallium nitride heterostructure (heterostructures). The p-type gallium nitride layer below the gate contact region controls the turn-on and turn-off of the high electron mobility transistor. In addition, the aluminum gallium nitride/gallium nitride interface forms a two-dimensional electron gas (2DEG) channel between the source and drain electrodes of the HEMT. In the conventional high electron mobility transistor structure, the dopant in the magnesium-doped p-type gallium nitride layer can easily diffuse out into the aluminum gallium nitride layer and deactivate the dopant. The out-diffusion and non-activation of magnesium in the aluminum gallium nitride layer will form a trapping center in the aluminum gallium nitride layer and reduce the two-dimensional electron gas current. This degrades high electron mobility transistor performance, such as higher on-resistance and/or High Temperature Reverse Bias (HTRB) degradation.

Thus, existing high electron mobility transistor structures are not entirely satisfactory with respect to dopant diffusion and activation.

Disclosure of Invention

An embodiment of the present disclosure provides a semiconductor structure, including: a channel layer, a barrier layer, a gate electrode, and a doped layer. The barrier layer is located above the channel layer. A gate electrode is over the barrier layer. The doped layer is formed between the barrier layer and the gate electrode. The doped layer includes an interface layer in contact with the barrier layer and a main layer between the interface layer and the gate electrode. The doping layer includes a dopant, and a doping concentration of the dopant in the interface layer is lower than a doping concentration of the dopant in the main layer.

The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, which includes: forming a channel layer; forming a barrier layer over the channel layer; growing a doped layer above the barrier layer, and doping a dopant into the doped layer, wherein the doped layer comprises an interface layer in contact with the barrier layer and a main layer on the interface layer, and the flow rate of the dopant is controlled during doping so that the doping concentration of the dopant in the interface layer is lower than the doping concentration of the dopant in the main layer; and forming a gate electrode over the doped layer.

The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, which includes: forming a channel layer; forming a barrier layer over the channel layer; growing a doped layer over the barrier layer, doping a dopant into the doped layer, wherein the doped layer comprises an interface layer in contact with the barrier layer and a main layer on the interface layer, and controlling a temperature of the dopant during doping such that the temperature of the dopant in the main layer is higher than the temperature of the dopant in the interface layer; and forming a gate electrode over the doped layer.

Drawings

The concepts of the disclosed embodiments can be better understood from the following detailed description when considered in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, the various components in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced for clarity of illustration. Like reference numerals are used to denote like features throughout the specification and drawings.

Figure 1 illustrates a cross-sectional view of an exemplary semiconductor structure with controlled dopant diffusion and activation, according to some embodiments of the present disclosure.

Fig. 2 illustrates a method of doping dopants in an exemplary semiconductor structure, according to some embodiments of the present disclosure.

Fig. 3 illustrates an exemplary doping flux profile controlled during doping according to some embodiments of the present disclosure.

Fig. 4 illustrates dopant diffusion behavior for different doping methods according to some embodiments of the present disclosure.

Figure 5 illustrates a flow diagram of an exemplary method for fabricating a semiconductor structure with controlled dopant diffusion and activation, according to some embodiments of the present disclosure.

Figure 6 illustrates a flow diagram of another exemplary method for fabricating a semiconductor structure with controlled dopant diffusion and activation, according to some embodiments of the present disclosure.

Description of reference numerals:

100 semiconductor structure

110. 210 channel layer

112. 212 two-dimensional electron gas

120. 220 barrier layer

125 consumption layer

130. 230 doped layer (p-type gallium nitride layer)

132. 232 dopant

142 source electrode

144 gate electrode

146 drain electrode

232-1 bottom dopant (dopant)

232-2 intermediate dopants (dopants)

232-3 Top dopant (dopant)

301. 302 magnesium doping profile

303 function of constant

320. 420 AlGaN layer

330. 430 p-type gallium nitride layer

330-1 interfacial layer

330-2 Main layer

410 undoped gallium nitride layer

421. 422 aluminum concentration distribution

431. 432 magnesium concentration profile

441. 442 magnesium out diffusion depth

500. 600 method

502. 504, 506, 508, 510, 602, 604, 606, 608, 610 operations

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of embodiments of the disclosure. Specific examples of components and arrangements are described below to simplify the description of the embodiments of the present disclosure. Of course, these specific examples are merely exemplary and are not intended to limit the disclosed embodiments. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the same reference signs and/or labels may be reused in different examples of the following disclosure. These iterations are for simplicity and clarity and are not intended to specify a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms may be used herein. Such as "under," "below," "lower," "above," "upper," and the like, to facilitate describing the relationship of one element or component to another element(s) or component as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in different orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Unless expressly stated otherwise, terms such as "attached," "secured," "connected," and "interconnected" refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

One of the major difficulties in developing high electron mobility transistors, such as normally-off (enhancement mode) high electron mobility transistors with p-type gallium nitride gates, is controlling the out-diffusion and activation of magnesium or other dopants in the p-type gallium nitride layer. The key layers of the p-type gallium nitride gate HEMT structure include a p-type gallium nitride layer and an aluminum gallium nitride/gallium nitride heterostructure. To avoid out-diffusion of the dopant magnesium in the magnesium-doped p-type gallium nitride layer to the aluminum gallium nitride layer, the present disclosure provides various embodiments of structures and methods for controlling dopant out-diffusion and activation. The present disclosure is applicable to any semiconductor structure having potential dopant out-diffusion issues. The dopant magnesium may be substituted for any p-type dopant, such as carbon (C), iron (Fe), zinc (Zn), etc., without affecting the technical effect of the disclosed structures and methods.

In some embodiments, the p-type gallium nitride gate transistor has a structure for controlling out-diffusion and activation of dopants in the p-type gallium nitride layer. For example, a transistor has a gallium nitride channel layer, an aluminum gallium nitride barrier layer over the gallium nitride channel layer, and a doped p-type gallium nitride layer under a gate contact region and over the aluminum gallium nitride barrier layer. The p-type gallium nitride layer may consume a two-dimensional electron gas (2DEG) channel formed in the channel layer, and a more efficient p-type dopant, such as magnesium, may improve the consumption capability of the p-type gallium nitride layer. Out-diffusion of magnesium occurs during the deposition of the p-type gallium nitride layer. To reduce or avoid magnesium out-diffusion into the aluminum gallium nitride barrier layer, the p-type gallium nitride layer is divided into two sublayers, namely a main layer and an interfacial layer. The interfacial layer is in contact with the aluminum gallium nitride barrier layer, and the main layer is on the interfacial layer and under the gate. The Mg doping concentration in the interfacial layer is lower than that in the main layer to reduce or prevent Mg from out-diffusing into the AlGaN barrier layer.

In one example, the doping concentration of magnesium in the interface layer is lowest at the surface of the barrier layer and gradually increases as magnesium moves away from the surface of the barrier layer. The magnesium doping concentration in the interfacial layer may follow a gradual profile with the lowest concentration at the surface of the barrier layer and the highest concentration at the surface of the main layer.

The doping concentration of magnesium can be controlled by controlling the flow rate of magnesium during doping. For example, in a Metal Organic Chemical Vapor Deposition (MOCVD) system, the disclosed method includes controlling the flow of bis (cyclopentadienyl) magnesium (Cp 2Mg) to follow a parabolic function at the AlGaN/p-type GaN interface to reduce or eliminate magnesium outdiffusion. The parabolic function would cause the initial magnesium flux to be low to inhibit magnesium out-diffusion and maintain a high flux of magnesium in the p-type gallium nitride host layer to maintain the p-type gallium nitride gate function, such as depleting the two-dimensional electron gas region, turning off the device at 0 volts, etc. Reducing the magnesium out-diffusion by controlling the doping flow profile (profile) eliminates trap centers in the gan barrier layer and avoids degradation of the hemt performance, such as higher on-resistance, higher sheet resistance (sheet resistance) or High Temperature Reverse Bias (HTRB) degradation in the hemt device.

In addition, the mg doping concentration in the main layer may be the same throughout the main layer and above a predetermined threshold (i.e., maintained at a high concentration level) to maintain sufficient mg activation to aid the p-gan function of the gate. In one embodiment, the magnesium doping concentration in the entire p-type gallium nitride layer may gradually increase from the top surface of the aluminum gallium nitride barrier layer to the bottom surface of the gate, such as a bis (cyclopentadienyl) magnesium flux that follows a parabolic function. In this way, out-diffusion of dopants can be addressed without changing the total doping amount of the dopants. In another embodiment, the temperature of the magnesium is controlled during doping such that the growth temperature of the magnesium in the host layer is higher than the growth temperature of the magnesium in the interfacial layer. Since high temperatures increase magnesium outdiffusion and activation, lower temperatures in the interfacial layer help reduce magnesium outdiffusion, while higher temperatures in the host layer help magnesium activation.

Fig. 1 illustrates a cross-sectional view of an exemplary semiconductor structure 100 with controlled dopant diffusion and activation, according to some embodiments of the present disclosure. According to an embodiment, the semiconductor structure 100 may be a portion of a transistor, such as a group III-V high electron mobility transistor. The iii-v high electron mobility transistors on the silicon substrate may be used as power switching transistors for voltage converter applications. Due to the property of having a wide energy gap, the iii-v high electron mobility transistor has low on-resistance and low switching loss compared to a silicon power transistor. In the present disclosure, "iii-v group semiconductor" refers to a compound semiconductor including at least one iii-group element and at least one v-group element, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), aluminum indium gallium nitride (InAlGaN), indium gallium nitride (InGaN), and the like, but is not limited thereto. Similarly, the "group iii nitride semiconductor" refers to a compound semiconductor containing nitrogen and at least one group iii element, such as gallium nitride, aluminum gallium nitride (aigan), indium nitride (InN), aluminum nitride (AlN), indium gallium nitride (InGaN), aluminum indium gallium nitride (InAlGaN), and the like, but is not limited thereto.

As shown in fig. 1, the semiconductor structure 100 includes a channel layer 110, a barrier layer 120, a doped layer 130, a source electrode 142, a gate electrode 144, and a drain electrode 146. The channel layer 110 has a channel potential for accommodating the two-dimensional electron gas 112 to improve the current performance of the semiconductor structure 100. In some embodiments, the channel layer 110 includes one or more iii-v compound layers. For example, the channel layer 110 includes gallium nitride. In at least one embodiment, one or more of the iii-v compound layers are doped. In at least one embodiment, one or more of the iii-v compound layers are undoped. In this example, the top of the channel layer 110 is in contact with the barrier layer 120 and comprises undoped gallium nitride. In one embodiment, the channel layer 110 is formed on a semiconductor substrate. In another embodiment, there may be other layers between the channel layer 110 and the substrate, such as buffer layers, transition layers, and/or intermediate layers.

The barrier layer 120 in this example is formed over the channel layer 110. The barrier layer has a barrier potential for confining the two-dimensional electron gas 112 in the channel layer 110. In some embodiments, the barrier layer 120 includes one or more group iii-v compounds. For example, the barrier layer 120 includes aluminum gallium nitride (AlGaN) or Al_xGa_1-xN (wherein 0)<x<1). The composition of the aluminum and the thickness of the barrier layer 120 are varied to control the threshold voltage of the transistor over a wide range. In one or more embodiments, the barrier layer 120 comprises undoped aluminum gallium nitride.

The source electrode 142 in this example is formed over the barrier layer 120 and is configured to supply an input current to the two-dimensional electron gas 112. The drain electrode 146 in this example is formed over the barrier layer 120 and is configured to supply an output current. An input current flows from the source electrode 142 through the two-dimensional electron gas 112 to the drain electrode 146 to generate an output current of the transistor. The gate electrode 144 in this example is formed over the barrier layer 120 and is configured to control the flow of an input current through the two-dimensional electron gas 112.

The doped layer 130 in this example is formed between the barrier layer 120 and the gate electrode 144. The doped layer 130 is configured to consume the two-dimensional electron gas 112 under the gate electrode 144 at zero bias. In some embodiments, doped layer 130 includes one or more iii-v compounds. For example, doped layer 130 comprises p-type gallium nitride. In addition, the doped layer 130 is doped with a dopant 132 to improve the consumption capability of the doped layer 130. By forming the depletion layer 125, the high barrier of the p-type gallium nitride layer 130 may completely deplete the two-dimensional electron gas 112 from the portion below the gate electrode 144, in one embodiment, the dopant 132 is a p-type dopant that includes at least one of carbon (C), iron (Fe), magnesium (Mg), and zinc (Zn).

As shown in fig. 1, the doping concentration of the dopant 132 in the p-type gallium nitride layer 130 gradually increases from the top surface of the aluminum gallium nitride barrier layer 120 to the bottom surface of the gate electrode 144. For example, the doping concentration may follow a parabolic function. In one example, doped layer 130 includes an interface layer (not shown) in contact with barrier layer 120 and a main layer (not shown) located between the interface layer and gate electrode 144. The doped layer 130 includes a dopant 132 having a lower doping concentration in the interfacial layer than in the main layer. For example, the doping concentration of the dopant 132 in the interfacial layer is lowest at the surface of the barrier layer 120 and gradually increases as the dopant 132 is farther away from the aforementioned surface of the barrier layer 120. The doping concentration of dopant 132 in the interfacial layer may follow a parabolic function with the lowest concentration at the top surface of barrier layer 120 and the highest concentration at the bottom surface of the primary layer. In addition, the doping concentration of the dopant 132 in the main layer may be the same throughout the main layer and above a predetermined threshold (i.e., maintained at a high concentration level) to maintain the activation of the dopant 132 to aid the gallium nitride function of the gate electrode 144.

Fig. 2 illustrates a method of doping dopants 232 in an exemplary semiconductor structure, according to some embodiments of the present disclosure. Fig. 2 shows a portion of a semiconductor structure including a channel layer 210, a barrier layer 220, and a doped layer 230. The channel layer 210 has a channel potential for accommodating a two-dimensional electron gas 212 for improving the current performance of the semiconductor structure. In this example, the channel layer 210 comprises undoped gallium nitride. In one embodiment, the channel layer 210 is formed on a semiconductor substrate. In another embodiment, there may be other layers between the channel layer 210 and the substrate, such as buffer layers, transition layers, and/or intermediate layers. In this example, the thickness of the channel layer 210 is about 0.5 microns.

The barrier layer 220 in this example is formed on the channel layer 210. The barrier layer 220 has a barrier potential for confining the two-dimensional electron gas 212 in the channel layer 210. In this example, the barrier layer 220 comprises aluminum gallium nitride and has a thickness of about 18 nanometers.

The doped layer 230 in this example is formed over the barrier layer 220 and is configured to consume the two-dimensional electron gas 212 at zero bias. In this example, doped layer 230 comprises p-type gallium nitride and has a thickness of about 70 nanometers. In addition, the doped layer 230 is doped with a dopant 232 to improve the consumption capability of the doped layer 230. The high barrier of the p-type gallium nitride layer 230 may completely consume the two-dimensional electron gas 212. In one embodiment, the dopant 232 is a p-type dopant including at least one of carbon, iron, magnesium, and zinc.

Dopant 232 may be placed into doped layer 230 as doped layer 230 is grown. That is, the doping layer 230 and the dopant 232 may be formed simultaneously. The "doping" described in the present disclosure may refer to a process of putting a dopant into a layer after the layer is formed or while the layer is grown.

As shown in fig. 2, during the doping of the dopant 232, the doping concentration of the dopant 232 in the p-type gallium nitride layer 230 gradually increases from the top surface of the barrier layer 220 to the top surface of the doped layer 230. For example, the bottom dopant 232-1 has the lowest doping concentration, the top dopant 232-3 has the highest doping concentration, and the middle dopant 232-2 has a doping concentration between the two doping concentrations. Therefore, the distribution of the doping concentration along the longitudinal axis will follow a parabolic function. In one example, the doped layer 230 includes an interface layer (not shown) in contact with the barrier layer 220 and a main layer (not shown) located above the interface layer. The dopant concentration of the dopant 232 in the interfacial layer is lower than the dopant concentration of the dopant 232 in the main layer. For example, the doping concentration of dopant 232 in the interfacial layer is lowest at the top surface of barrier layer 220 and gradually increases as dopant 232 moves away from the top surface of barrier layer 220. The doping concentration of dopant 232 in the interfacial layer may follow a parabolic function with the lowest concentration at the top surface of barrier layer 220 and the highest concentration at the bottom surface of the primary layer. In addition, the doping concentration of the dopant 232 in the main layer may be the same throughout the main layer and above a predetermined threshold (i.e., maintained at a high concentration level) to keep the dopant 232 activated to aid the p-type gallium nitride function, such as consuming the two-dimensional electron gas 212.

By controlling the doping flow of the dopant 232, different doping concentrations of the dopant 232 in the doped layer 230 can be achieved during doping. For example, the doping flux of the dopant 232-1 at the bottom of the doped layer 230 may be controlled to be the lowest, the doping flux of the dopant 232-3 at the top of the doped layer 230 may be controlled to be the highest, and the doping flux of the dopant 232-2 at the middle portion of the doped layer 230 may be controlled to be between the two fluxes. Thus, the distribution of doping flux along the longitudinal axis may follow a parabolic function. As such, out-diffusion of the dopants 232 into the barrier layer 220 is minimized or avoided.

In addition, in order to ensure the activation of the dopant 232, the temperature of the dopant 232 is controlled during doping such that the temperature of the dopant 232 in the main layer is higher than the temperature of the dopant 232 in the interface layer. For example, the temperature of the dopant 232-1 at the bottom of the doped layer 230 may be controlled to be the lowest, the temperature of the dopant 232-3 at the top of the doped layer 230 to be the highest, and the temperature of the dopant 232-2 at the middle portion of the doped layer 230 to be between the two temperatures during doping. Thus, the temperature profile along the longitudinal axis during doping may also follow a parabolic function. As such, out-diffusion of dopants 232 into barrier layer 220 is minimized without compromising activation of dopants 232 in doped layer 230.

Fig. 3 illustrates an exemplary doping flux profile controlled during doping according to some embodiments of the present disclosure. Fig. 3 shows a portion of an epitaxial recipe (recipe) for a transistor (p-type gallium nitride gate hemt, including an aluminum gallium nitride layer 320 and a magnesium-doped p-type gallium nitride layer 330). The AlGaN layer 320 serves as a barrier layer, and the p-type GaN layer 330 serves as a consumption control layer. The p-type gallium nitride layer 330 includes two sublayers: an interface layer 330-1 and a main layer 330-2. According to the growth sequence, during the fabrication of the transistor, the AlGaN layer 320 is formed first, then the interfacial layer 330-1 is formed, and finally the main layer 330-2 is formed.

In this example, although the gallium growth levels of the two sublayers of the p-type gallium nitride layer 330 are the same and follow a constant function 303, the magnesium doping levels in the two sublayers are different. In the interfacial layer 330-1, the magnesium doping profile follows a parabolic function such that the initial magnesium flux at the surface of the aluminum gallium nitride layer 320 is low to inhibit magnesium out-diffusion and gradually increase the magnesium flux as the magnesium moves away from the aluminum gallium nitride layer 320. In the p-type gallium nitride main layer 330-2, the magnesium doping profile is kept high to maintain the p-type gallium nitride function, e.g., consuming a two-dimensional electron gas region, turning off the device at 0 volts, etc. Different magnesium doping profiles 301, 302 may be implemented according to different embodiments and different customer requirements. In an embodiment, the magnesium doping profile may follow a function other than a parabolic function, as long as the magnesium concentration is lower at the surface of the aluminum gallium nitride layer 320 in the interface layer 330-1 and is increased in the p-type gallium nitride main layer 330-2.

In this example, the gallium in the device is in the form of trimethyl gallium (TMGa), the aluminum in the aluminum gallium nitride layer 320 is in the form of trimethyl aluminum (TMAl), and the magnesium in the p-type gallium nitride layer 330 is in the form of bis (cyclopentadienyl) magnesium. As shown in fig. 3, the source valve of trimethyl gallium is turned on during the formation of the aluminum gallium nitride layer 320 and the p-type gallium nitride layer 330, and the source valve of trimethyl aluminum is turned on during the formation of the aluminum gallium nitride layer 320, but is turned off during the formation of the p-type gallium nitride layer 330. The source valve of bis (cyclopentadienyl) magnesium is closed during the formation of aluminum gallium nitride layer 320, but is open during the formation of p-type gallium nitride layer 330. Thus, there is no magnesium in the aluminum gallium nitride layer 320. The magnesium concentration in the interface layer 330-1 is lower than the magnesium concentration in the main layer 330-2.

In one embodiment, when forming the p-type gallium nitride layer 330, gallium and magnesium are grown/doped together, but with different growth/doping fluxes. When the gallium growth flux reaches the desired level from the beginning of growth, the magnesium doping flux starts at a low level and increases to the desired level as the p-type gallium nitride layer 330 grows (i.e., as the magnesium doping moves away from the aluminum gallium nitride layer 320).

Fig. 4 is a portion of a Secondary Ion Mass Spectrometry (SIMS) -based display transistor, such as a p-type gallium nitride gate high electron mobility transistor, including an undoped gallium nitride layer 410, an aluminum gallium nitride layer 420, and a p-type gallium nitride layer 430 doped with magnesium. The undoped gallium nitride layer 410 serves as a channel layer, the aluminum gallium nitride layer 420 serves as a barrier layer, and the p-type gallium nitride layer 430 serves as a consumption control layer. Depending on the depth information, the undoped gallium nitride layer 410 is deepest among the three layers shown in fig. 4. An aluminum gallium nitride layer 420 is formed over the undoped gallium nitride layer 410, and a p-type gallium nitride layer 430 is formed over the aluminum gallium nitride layer 420.

Because all three layers in fig. 4 include gallium nitride, the boundaries of the different layers are identified by the aluminum concentration in different regions or at different depths of the three layers. As shown in fig. 4, the boundary of the aluminum gallium nitride layer 420 may be identified at a depth where the aluminum concentration drops below a certain threshold. FIG. 4 compares the performance of the disclosed method and the baseline method according to one embodiment. The reference method does not control the flow rate of magnesium during doping so that the doping flow rate of magnesium is the same from the beginning to the end of magnesium doping. As shown in fig. 4, the aluminum concentration profile 422 based on the disclosed method and the aluminum concentration profile 421 based on the reference method show the same identification of the boundaries of the three layers. However, the magnesium concentration profile 432 based on the disclosed method and the magnesium concentration profile 431 based on the baseline method show different out-diffusion of magnesium to a depth in the aluminum gallium nitride layer 420. As shown in fig. 4, the magnesium concentration profile 432 based on the disclosed method has a magnesium out-diffusion depth 442 that is less than the magnesium out-diffusion depth 441 of the magnesium concentration profile 431 based on the baseline method. In addition, the magnesium concentration profile 432 based on the disclosed method has a lower magnesium concentration at the bottom of the p-type gallium nitride layer 430 (i.e., near the interface of the p-type gallium nitride layer 430 and the interlayer 420 of aluminum gallium nitride) and maintains a high magnesium concentration at the top of the p-type gallium nitride layer 430, as compared to the magnesium concentration profile 431 based on the baseline method. In this way, out-diffusion of magnesium into the AlGaN layer 420 is reduced while the activation of magnesium in the p-type GaN layer 430 is maintained at a high level.

Figure 5 illustrates a flow diagram of an exemplary method 500 for fabricating a semiconductor structure with controlled dopant diffusion and activation, according to some embodiments of the present disclosure. In operation 502, a channel layer is formed over a substrate. At operation 504, a barrier layer is formed over the channel layer. In operation 506, a doped layer is grown over the barrier layer. The doped layer includes: an interfacial layer in contact with the barrier layer, and a main layer located on the interfacial layer. In operation 508, dopants are doped into the doped layer by controlling the flow of the dopants such that the doping concentration of the dopants in the interfacial layer is lower than the dopant concentration of the dopants in the main layer. In an embodiment,

operations

506 and 508 may be performed in conjunction and together. That is, dopants are doped into the doped layer while the doped layer is grown over the barrier layer. In operation 510, a gate electrode is formed over the doped layer. In one embodiment, the order of operations shown in FIG. 5 may be altered according to different embodiments of the present disclosure.

Figure 6 illustrates a flow diagram of another exemplary method 600 for fabricating a semiconductor structure with controlled dopant diffusion and activation, according to some embodiments of the present disclosure. In operation 602, a channel layer is formed over a substrate. At operation 604, a barrier layer is formed over the channel layer. In operation 606, a doped layer is grown over the barrier layer. The doped layer includes: an interfacial layer in contact with the barrier layer, and a main layer located on the interfacial layer. In operation 608, dopants are doped into the doped layer by controlling the temperature of the dopants during doping such that the temperature of the dopants is higher in the main layer and lower in the interface layer. In an embodiment,

operations

606 and 608 may be performed in conjunction and together. That is, dopants are doped into the doped layer while the doped layer is grown over the barrier layer. In operation 610, a gate electrode is formed over the doped layer. In one embodiment, the order of operations shown in FIG. 6 may be changed according to different embodiments of the present disclosure.

In some embodiments, a semiconductor structure is disclosed. The semiconductor structure comprises: a channel layer, a barrier layer, a gate electrode, and a doped layer. The barrier layer is located above the channel layer. A gate electrode is over the barrier layer. The doped layer is formed between the barrier layer and the gate electrode. The doped layer includes an interface layer in contact with the barrier layer and a main layer between the interface layer and the gate electrode. The doping layer includes a dopant, and a doping concentration of the dopant in the interface layer is lower than a doping concentration of the dopant in the main layer.

In some embodiments, the channel layer has a channel potential to contain a two-dimensional electron gas, and the barrier layer has a barrier potential to confine the two-dimensional electron gas in the channel layer.

In some embodiments, the semiconductor structure further comprises a source electrode and a drain electrode. The source electrode is configured to supply an input current to the two-dimensional electron gas. The drain electrode is configured to supply an output current, wherein the input current flows from the source electrode to the drain electrode via the two-dimensional electron gas to generate the output current, and the gate electrode is configured to control the input current flowing through the two-dimensional electron gas.

In some embodiments, the doped layer is configured to consume the two-dimensional electron gas under the gate electrode at zero bias, and the dopant in the doped layer is configured to improve the consumption capability of the doped layer.

In some embodiments, the aforementioned dopant is a p-type dopant comprising at least one of carbon, iron, magnesium, and zinc.

In some embodiments, the doping concentration of the dopant in the interfacial layer is lowest at the surface of the barrier layer and gradually increases as the dopant is farther away from the surface of the barrier layer.

In some embodiments, the dopant concentration of the dopant in the interfacial layer follows a parabolic function with the lowest concentration at the surface of the barrier layer and the highest concentration at the surface of the main layer.

In some embodiments, the dopant concentration of the dopant in the main layer is the same throughout the main layer and is above a predetermined threshold.

In some embodiments, the channel layer comprises a first group III-V compound, the barrier layer comprises a second group III-V compound, and the doped layer comprises a third group III-V compound and the dopant.

In some embodiments, the channel layer comprises undoped gallium nitride, the barrier layer comprises aluminum gallium nitride, and the doped layer comprises p-type gallium nitride and the dopant.

In other embodiments, a method of fabricating a semiconductor structure is disclosed. The manufacturing method of the semiconductor structure comprises the following steps: forming a channel layer; forming a barrier layer over the channel layer; growing a doped layer above the barrier layer, and doping a dopant into the doped layer, wherein the doped layer comprises an interface layer in contact with the barrier layer and a main layer on the interface layer, and the flow rate of the dopant is controlled during doping so that the doping concentration of the dopant in the interface layer is lower than the doping concentration of the dopant in the main layer; and forming a gate electrode over the doped layer.

In some embodiments, the flow rate of the dopant is controlled during doping such that the dopant concentration of the dopant in the interfacial layer is lowest at the surface of the barrier layer and gradually increases as the dopant is further away from the surface of the barrier layer.

In some embodiments, the flow rate of the dopant is controlled during doping such that the dopant concentration of the dopant in the interfacial layer follows a parabolic function with the lowest concentration at the surface of the barrier layer and the highest concentration at the surface of the main layer.

In some embodiments, the flow of the dopant is controlled during doping such that the dopant concentration of the dopant in the main layer is the same throughout the main layer and is above a predetermined threshold.

In some embodiments, the method further comprises controlling a temperature of the dopant during doping such that the temperature of the dopant in the main layer is higher than the temperature of the dopant in the interfacial layer.

In yet other embodiments, a method of fabricating a semiconductor structure is disclosed. The manufacturing method of the semiconductor structure comprises the following steps: forming a channel layer; forming a barrier layer over the channel layer; growing a doped layer over the barrier layer, doping a dopant into the doped layer, wherein the doped layer comprises an interface layer in contact with the barrier layer and a main layer on the interface layer, and controlling a temperature of the dopant during doping such that the temperature of the dopant in the main layer is higher than the temperature of the dopant in the interface layer; and forming a gate electrode over the doped layer.

In some embodiments, the method further includes controlling a flow rate of the dopant during the doping such that a doping concentration of the dopant in the interfacial layer is lowest at the surface of the barrier layer and gradually increases as the dopant is farther away from the surface of the barrier layer.

In some embodiments, the method further comprises controlling the flow of the dopant during doping such that the dopant concentration of the dopant in the main layer is the same throughout the main layer and is above a predetermined threshold.

The foregoing outlines features of many embodiments so that those skilled in the art may better understand the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the disclosed embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure. Various changes, substitutions, and alterations can be made to the embodiments of the disclosure without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor structure comprising:

a channel layer;

a barrier layer located above the channel layer;

a gate electrode over the barrier layer; and

a doped layer formed between the barrier layer and the gate electrode, wherein the doped layer includes an interface layer in contact with the barrier layer and a main layer between the interface layer and the gate electrode, The doping layer further includes a dopant, and the doping concentration of the dopant in the interface layer is lower than the doping concentration of the dopant in the main layer.

2. The semiconductor structure of claim 1, wherein:

The channel layer has a channel potential to accommodate a two-dimensional electron gas; and

The barrier layer has a barrier potential to confine the two-dimensional electron gas in the channel layer.

3. The semiconductor structure of claim 2, further comprising:

a source electrode configured to supply an input current to the two-dimensional electron gas; and

a drain electrode configured to supply an output current, wherein the input current flows from the source electrode through the two-dimensional electron gas to the drain electrode to generate the output current, and the gate electrode is configured to control the flow through the input current of the two-dimensional electron gas.

4. The semiconductor structure of claim 2, wherein:

The doped layer is configured to deplete the two-dimensional electron gas under the gate electrode at zero bias; and

The dopant in the doped layer is configured to improve the dissipation capability of the doped layer.

5. The semiconductor structure of claim 1, wherein the dopant is a p-type dopant comprising at least one of carbon, iron, magnesium, and zinc.

6. The semiconductor structure of claim 1, wherein the dopant concentration of the dopant in the interface layer is lowest at a surface of the barrier layer, and as the dopant moves away from the dopant of the barrier layer surface and gradually increase.

7. The semiconductor structure of claim 1, wherein the doping concentration of the dopant in the main layer is the same throughout the main layer and is higher than a predetermined threshold.

8. The semiconductor structure of claim 1, wherein:

The channel layer includes a Group 135 compound;

The barrier layer includes a Group 235 compound; and

The doped layer includes a Group 335 compound and the dopant.

9. A method of manufacturing a semiconductor structure, comprising:

forming a channel layer;

forming a barrier layer over the channel layer;

A doped layer is grown above the barrier layer, and a dopant is doped into the doped layer, wherein the doped layer includes an interface layer in contact with the barrier layer and a main layer on the interface layer , controlling a flow rate of the dopant during the doping period so that the doping concentration of the dopant in the interface layer is lower than the doping concentration of the dopant in the main layer; and

A gate electrode is formed over the doped layer.

10. A method of manufacturing a semiconductor structure, comprising:

forming a channel layer;

forming a barrier layer over the channel layer;

A doped layer is grown above the barrier layer, and a dopant is doped into the doped layer, wherein the doped layer includes an interface layer in contact with the barrier layer and a main layer on the interface layer , controlling a temperature of the dopant during the doping so that the temperature of the dopant in the main layer is higher than the temperature of the dopant in the interface layer; and

A gate electrode is formed over the doped layer.