CN110912529B - Monolithic filter ladder network and method of manufacturing the same - Google Patents
Monolithic filter ladder network and method of manufacturing the same Download PDFInfo
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- CN110912529B CN110912529B CN201911148479.2A CN201911148479A CN110912529B CN 110912529 B CN110912529 B CN 110912529B CN 201911148479 A CN201911148479 A CN 201911148479A CN 110912529 B CN110912529 B CN 110912529B
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- H—ELECTRICITY
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- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
- H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
- H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
- H03H9/172—Means for mounting on a substrate, i.e. means constituting the material interface confining the waves to a volume
- H03H9/174—Membranes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/0023—Balance-unbalance or balance-balance networks
- H03H9/0095—Balance-unbalance or balance-balance networks using bulk acoustic wave devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/02007—Details of bulk acoustic wave devices
- H03H9/02015—Characteristics of piezoelectric layers, e.g. cutting angles
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/02535—Details of surface acoustic wave devices
- H03H9/02543—Characteristics of substrate, e.g. cutting angles
- H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
- H03H9/0542—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a lateral arrangement
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
- H03H9/56—Monolithic crystal filters
- H03H9/566—Electric coupling means therefor
- H03H9/568—Electric coupling means therefor consisting of a ladder configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
- H03H9/58—Multiple crystal filters
- H03H9/60—Electric coupling means therefor
- H03H9/605—Electric coupling means therefor consisting of a ladder configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
- H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
- H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
- H03H9/172—Means for mounting on a substrate, i.e. means constituting the material interface confining the waves to a volume
- H03H9/175—Acoustic mirrors
Landscapes
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Abstract
The invention relates to a monolithic filter ladder network and a method of manufacturing the same. The monolithic filter ladder network includes a plurality of SCAR devices labeled R1 through RN disposed on a common substrate member, where N is an integer greater than 1. Each SCAR device includes a bulk substrate structure having a surface region and a thickness of material, and a thickness of single crystal piezoelectric material formed to cover the surface region, the single crystal piezoelectric material characterized by a thickness of less than 10 12 Defect/cm 2 Dislocation density of (c) is provided. Each SCAR device further comprises: a first electrode member, a second electrode member, a first electrode structure, a second electrode structure, a dielectric material, and an acoustic reflector structure.
Description
The present application is a divisional application of chinese patent application having application date 2015, 6 and 5, application number 201580042442.5, and the name of "integrated circuit provided with crystal acoustic resonator device".
Cross Reference to Related Applications
The present application claims priority from U.S. application Ser. No.14/298,057 submitted at 6.6.2014 and U.S. application Ser. No.14/298,100 submitted at 6.6.2014.
Technical Field
The present invention relates generally to electronic devices. More particularly, the present invention provides techniques related to mono-crystal acoustic resonators. By way of example only, the invention has been applied to resonator devices, in particular for communication devices, mobile devices, computing devices.
Background
Mobile telecommunications devices have been successfully deployed worldwide. Over one billion mobile devices (including cellular handsets and smartphones) have been manufactured in one year, and the unit volume continues to grow year by year. Due to the steep mass production of 4G/LTE in about 2012, and the proliferation of mobile data traffic, the data-rich content drives the growth of the smart phone field-hopefully 2B per year in the next few years. Coexistence of new standards and legacy standards, as well as the desire for higher data rate requirements, drives RF complexity in smartphones. Unfortunately, there are limitations in conventional RF technology, which are problematic and may cause defects in the future.
From the foregoing, techniques for improving electronic devices are highly desirable.
Disclosure of Invention
In accordance with the present invention, techniques are provided that generally relate to electronic devices. More particularly, the present invention provides techniques related to mono-crystal acoustic resonators. By way of example only, the invention has been applied to resonator devices, in particular for communication devices, mobile devices, computing devices.
In an example, the present invention provides single crystal capacitor dielectric material disposed on a substrate through limited area epitaxy. The material is coupled between a pair of electrodes, which in the example are configured from the upper side and the backside of the substrate member. In an example, single crystal capacitor dielectric materials are provided using metal organic chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, pulsed laser deposition, chemical vapor deposition, or wafer bonding processes. In an example, a limited area epitaxy is stripped (lifted-off) of the substrate and transferred to another substrate. In an example, the material is characterized by a defect density of less than 1E+11 defects per square centimeter. In an example, the single crystal capacitor material is selected from at least one of AlN, alGaN, inN, BN or other group iii nitride. In an example, the single crystal capacitor material is selected from at least one of single crystal oxide ZnO or MgO including a high K dielectric.
In an example, a mono-crystalline acoustic electronic device is provided. The device has a substrate having a surface area. The device has a first electrode material coupled to a portion of a substrate and a single crystal capacitor dielectric material having a thickness greater than 0.4 microns and covering a storm of the surface area The exposed portion is coupled to the first electrode material. In an example, the single crystal capacitor dielectric material is characterized by less than 10 12 Defect/cm 2 Dislocation density of (c) is provided. The second electrode material overlies the single crystal capacitor dielectric material.
In an example, the present invention provides a configurable Single Crystal Acoustic Resonator (SCAR) device integrated circuit. The circuit includes a plurality of SCAR devices numbered 1 through N, where N is 2 and an integer greater than 2. Each SCAR device has a thickness of single crystal piezoelectric material formed to cover a surface area of the substrate member. The single crystal piezoelectric material is characterized by being less than 10 12 Defect/cm 2 Dislocation density of (c) is provided.
One or more benefits over the prior art are realized using the present invention. In particular, the invention enables a cost-effective resonator device for communication applications. In particular embodiments, the present device may be manufactured in a relatively simple and cost effective manner. According to embodiments, the present devices and methods may be manufactured according to one of ordinary skill in the art using conventional materials and/or methods. The present apparatus uses a material comprising gallium and nitrogen, which is monocrystalline. Depending on the implementation, one or more of these benefits may be realized. Of course, other variations, modifications, and alternatives are possible.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the attached drawings.
Drawings
For a more complete understanding of the present invention, reference is made to the accompanying drawings. It is to be understood that these drawings are not to be considered limiting of the scope of the invention, and that the presently described embodiments and the presently understood best mode of the invention are described in more detail by using the drawings in which:
fig. 1 is a simplified diagram illustrating an example surface mono-crystal acoustic resonator according to the present invention.
Fig. 2 is a simplified diagram illustrating an example bulk mono-crystal acoustic resonator according to the present invention.
Fig. 3 is a simplified diagram illustrating features of a bulk mono-crystalline acoustic resonator according to an example of the invention.
Fig. 4 is a simplified diagram illustrating a piezoelectric structure according to an example of the present invention.
Fig. 5 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention.
Fig. 6 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention.
Fig. 7 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention.
Fig. 8 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention.
Fig. 9 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention.
Fig. 10 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention.
Fig. 11 is a simplified diagram of a substrate member according to an example of the invention.
Fig. 12 is a simplified diagram of a substrate member according to an example of the invention.
Fig. 13 is a simplified table showing the characteristics of the present example compared to a conventional filter according to an example of the present invention.
Fig. 14 to 22 show a method of manufacturing a single crystal acoustic resonator device used in an example of the present invention.
Fig. 23 shows a circuit diagram of a mono-crystal acoustic resonator device in an example of the invention.
Fig. 24 to 32 show a method of manufacturing a single crystal acoustic resonator device used in an example of the present invention.
Fig. 33 shows a circuit diagram of a mono-crystal acoustic resonator device in an example of the invention.
Fig. 34 and 35 show reflector structures configured on a single crystal acoustic resonator device in an example of the present invention.
Fig. 36 shows a circuit diagram of a reflector structure integrated with the mono-crystal acoustic resonator device of the above-described fig.
Fig. 37 and 38 show reflector structures configured on a single crystal acoustic resonator device in an example of the present invention.
Fig. 39 shows a circuit diagram of a reflector structure integrated with the mono-crystal acoustic resonator device of the above-described fig.
Fig. 40 shows a simplified diagram of the bottom and top surface regions of a mono-crystalline acoustic resonator device in an example of the invention.
Fig. 41 to 44 show simplified examples of a single crystal acoustic resonator device configured in a filter ladder network in an example of the present invention.
Fig. 45 to 52 show simplified examples of a two-element mono-crystal acoustic resonator device and a three-element mono-crystal acoustic resonator device according to examples of the present invention.
Detailed Description
In accordance with the present invention, techniques are provided that generally relate to electronic devices. More particularly, the present invention provides techniques related to mono-crystal acoustic resonators. By way of example only, the invention has been applied to resonator devices, in particular for communication devices, mobile devices, computing devices.
As an additional background, the number of frequency bands supported by a smart phone is estimated to increase by 7 times compared to the conventional art. Thus, more frequency bands means that highly selective filtering performance is increasingly becoming a differentiator in the RF front end of smartphones. Unfortunately, conventional techniques have severe limitations.
That is, conventional filter technology is based on amorphous materials, which have poor electromechanical coupling efficiency (only 7.5% for lead-free materials), which results in nearly half of the transmit power being dissipated in the highly selective filter. In addition, single crystal acoustic wave devices are expected to realize improvements in adjacent channel suppression. Since there are twenty (20) or more filters in current smartphones and these filters are interposed between the power amplifier and the antenna scheme, there is then an opportunity to improve the RF front-end and maximize spectral efficiency within the system by reducing heat dissipation, the size of the power amplifier, and at the same time increasing the signal quality of the smartphone receiver.
With single crystal acoustic wave devices (hereinafter "SAW" devices) and filter schemes, one or more of the following benefits may be realized: (1) large diameter silicon wafers (up to 200 mm) are expected to achieve cost-effective high performance solutions, (2) with newly designed strained piezoelectric materials, electromechanical coupling efficiency is expected to be over three times, (3) filter insertion loss is expected to be reduced by 1dB, enabling extended battery life, improved thermal management with smaller RF packaging, and improved signal quality and user experience. These benefits and other benefits may be realized by the apparatus and methods of the present invention as further provided throughout this specification and more particularly below.
Fig. 1 is a simplified diagram illustrating an example surface mono-crystal acoustic resonator according to the present invention. The diagram is merely an example, which should not unduly limit the scope of the claims. There is shown a surface mono-crystal acoustic resonator device 100 having a crystalline piezoelectric material 120 of the present invention overlying a substrate 110. As shown, the acoustic wave propagates from the first spatial region to the second spatial region along a lateral direction substantially parallel to the pair of electrical ports 140, which forms an interdigital transducer configuration 130, the interdigital transducer configuration 130 having a plurality of metal wires 131 spatially arranged between the pair of electrical ports 140. In an example, the left side electrical port may be designated for signal input and the right side electrical port designated for signal output. In an example, a pair of electrode regions are configured and routed to a vicinity of a plane parallel to a contact region coupled to the second electrode material.
In SAW device examples, the surface acoustic wave produces resonant behavior over a narrow band near the 880MHz to 915MHz band, which is a specified passband for LTE-enabled mobile smartphones for europe, middle east and africa (EMEA). Variations may exist depending on the region of operation of the communication device. For example, in the transmit band of north america, the resonator may be designed such that the resonant behavior is in the frequency passband approaching 777MHz to 787 MHz. Other transmit bands found in other regions may be higher in frequency, such as asian transmit bands in the 2570MHz to 2620MHz passband. In addition, examples provided herein are for multiple transmit bands. In a similar way, the passband at the receiver side of the radio front-end also requires a similar implementation of the resonator filter. Of course, variations, modifications, and alternatives are possible.
Other features of surface acoustic wave devices include the fundamental frequency of the SAW device, which is determined by the surface propagation velocity (determined by the crystal mass of the piezoelectric material selected for the resonator) divided by the wavelength (determined by the fingers in the interdigital arrangement in fig. 1). Measured propagation speeds (also known as SAW speeds) in GaN of approximately 5800m/s have been recorded, with similar values being expected for AlN. Thus, the higher SAW speeds of such group III nitrides enable the resonator to handle higher frequency signals for a given device geometry.
Resonators made of group III nitrides are desirable because such materials operate at high power (with their high critical electric fields), high temperature (low intrinsic carrier concentration from their large band gap), and high frequency (high saturated electron velocity). Such high power devices (greater than 10 watts) are utilized in wireless infrastructure as well as commercial and military radar systems, to name a few. In addition, the stability, survivability, and reliability of such devices are critical to field deployment.
Further details of the individual elements provided in the present device may be found throughout the present specification and more particularly below.
Fig. 2 is a simplified diagram illustrating an example bulk mono-crystal acoustic resonator according to the present invention. The diagram is merely an example, which should not unduly limit the scope of the claims. A bulk mono-crystalline acoustic resonator device 200 of the present invention having a crystalline piezoelectric material is shown. As shown, the acoustic wave propagates in a vertical direction between the upper electrode material 231 and the substrate member 210 from the first spatial region to the second spatial region. As shown, the crystalline piezoelectric material 220 is disposed between the upper electrode material 231 and the lower electrode material 232. The upper electrode material 231 is disposed beneath a plurality of optional reflective layers formed to cover the upper electrode 231 to form the acoustic reflector region 240.
In a bulk acoustic wave (hereinafter "BAW") device example, the acoustic wave produces resonant behavior over a narrow frequency band that approximates the 3600MHz to 3800MHz frequency band, which is a designated passband for a mobile smartphone with LTE functionality. Variations may exist depending on the region of operation of the communication device. For example, in the transmit band of north america, the resonator may be designed such that the resonance behavior is in the frequency passband approaching 2000MHz to 2020 MHz. Other transmit bands are found in other regions, such as the transmit band of asia in the 2500MHz to 2570MHz passband. In addition, examples provided herein are for multiple transmit bands. In a similar way, the passband at the receiver side of the radio front-end also requires a similar implementation of the resonator filter. Of course, variations, modifications, and alternatives are possible.
Other features of single crystal BAW devices include electromechanical acoustic coupling in the device, which is proportional to the piezoelectric constant (affected by the design and strain of the single crystal piezoelectric layer) divided by the acoustic wave velocity (affected by scattering and reflection in the piezoelectric material). Sonic speeds in GaN in excess of 5300m/s have been observed. Thus, the high acoustic velocity of such group III nitrides enables the resonator to handle higher frequency signals for a given device geometry.
Similar to SAW devices, resonators made of group III nitrides are desirable because these materials operate at high power (with their high critical electric fields), high temperature (low intrinsic carrier concentrations from their large band gaps), and high frequency (high saturated electron velocities). Such high power devices (greater than 10 watts) are utilized in wireless infrastructure as well as commercial and military radar systems, to name a few. In addition, the stability, survivability, and reliability of such devices are critical to field deployment.
Further details of the individual materials provided in the present apparatus may be found throughout the present specification and more particularly below.
In an example, the device has a substrate having a surface area. In an example, the substrate may be a thickness of material, composite, or other structure. In an example, the substrate may be selected from a dielectric material, a conductive material, a semiconductor material, or any combination of these materials. In an example, the substrate may also be a polymer member or the like. In a preferred example, the substrate is selected from materials provided from silicon, gallium arsenide, aluminum oxide, and the like, and combinations thereof.
In an example, the substrate is silicon. The substrate has a surface area, which may be in an offset configuration or a cut-out configuration. In an example, the surface area ranges from 0.5 degrees An offset angle to 1.0 degrees. In an example, the substrate has<111>Oriented and has a high resistivity (greater than 10 3 ohm-cm). Of course, other variations, modifications, and alternatives are possible.
In an example, an apparatus has a first electrode material coupled to a portion of a substrate and a single crystal capacitor dielectric material having a thickness greater than 0.4 microns. In an example, the single crystal capacitor dielectric material has a suitable dislocation density. The dislocation density is less than 10 12 Defect/cm 2 And is greater than 10 4 Defect/cm 2 And variations thereof. The device has a second electrode material overlying the single crystal capacitor dielectric material. Further details of each of these materials may be found throughout the present specification and more particularly below.
In an example, the single crystal capacitor material is a suitable single crystal material having desired electrical properties. In an example, the single crystal capacitor material is typically a gallium and nitrogen containing material such as AlN, alGaN or GaN, including InN, inGaN, BN or other group III nitride. In an example, the single crystal capacitor material is selected from at least one single crystal oxide of single crystal oxides (ZnO, mgO, or an alloy of MgZnGaInO) comprising a high K dielectric. In an example, the high K is characterized by less than 10 12 Defect/cm 2 And is greater than 10 4 Defect/cm 2 Is a defect density of the (c). Of course, other variations, modifications, and alternatives are possible.
In an example, the single crystal capacitor dielectric material is characterized by a surface area of at least 50 microns by 50 microns, as well as variations. In examples, the surface area may be 200 micrometers by 200 micrometers or up to 1000 micrometers by 1000 micrometers. Of course, variations, modifications, and alternatives are possible.
In an example, the single crystal capacitor dielectric material is configured in a first strained state to compensate for the substrate. That is, the single crystal material is in a compressive or tensile strain state relative to the overlying substrate material. In an example, the strain state of GaN when deposited on silicon is tensile strain, while the AlN layer is compressive strain relative to the silicon substrate.
In a preferred example, single crystal capacitor dielectric material is deposited to cover the exposed portions of the substrate. In an example, the single crystal capacitor dielectric is a lattice that does not match the crystal structure of the substrate and may be strain compensated using a compressively strained piezoelectric nucleation layer (such as AlN or SiN).
In an example, the device has a first electrode material configured via a backside of the substrate. In an example, the first electrode material is configured by means of a back side of the substrate. The arrangement includes a via structure arranged within a thickness of the substrate.
In an example, the electrode material may be made of a suitable material or materials. In an example, each of the first electrode material and the second electrode material is selected from refractory metals or other noble metals. In an example, each of the first electrode material and the second electrode material is selected from one of tantalum, molybdenum, platinum, titanium, gold, aluminum, tungsten, or platinum, combinations thereof, and the like.
In an example, the first electrode material and the single crystal capacitor dielectric material include a first interface region substantially free of oxide-containing material. In an example, the first electrode material and the single crystal capacitor dielectric material include a second interface region substantially free of oxide-containing material. In an example, the device may include a first contact coupled to the first electrode material and a second contact coupled to the second electrode material such that each of the first contact and the second contact are configured in a coplanar arrangement.
In an example, the device has a reflector region disposed at the first electrode material. In an example, the device further has a reflector region disposed on the second electrode material. The reflector region is made of alternating low impedance reflector layers (e.g., dielectric) and high impedance reflector layers (e.g., metal), where the thickness of each layer targets a quarter wavelength, but variations are possible.
In an example, the device has a nucleation material disposed between the single crystal capacitor dielectric material and the first electrode material. The nucleation material is typically AlN or SiN.
In an example, the apparatus has a capping material disposed between the single crystal capacitor dielectric material and the second electrode material. In an example, the capping material is GaN.
In an example, the single crystal capacitor dielectric material preferably has other properties. That is, single crystal capacitor dielectric materials are characterized by a FWHM of less than 1 degree.
In an example, the single crystal capacitor dielectric is configured to propagate the longitudinal signal at a speed of sound of 5000 meters/second and greater. In other embodiments designed with strain, the signal may be higher than 6000m/s and lower than 12000m/s. Of course, variations, modifications, and alternatives are possible.
The device also has a desired resonant behavior when tested using a two port network analyzer. The resonance behaviour is characterized by two resonance frequencies (so-called serial and parallel) such that one exhibits an infinite electrical impedance and the other exhibits an impedance of zero. Between such frequencies, the device operates inductively. In an example, the device has an s-parameter derived from a two-port analysis, which can be converted to an impedance. From the s11 parameters, the real and imaginary impedance of the device can be extracted. From the s21 parameter, the transmission gain of the resonator can be calculated. Using parallel resonant frequencies along the known piezoelectric layer thickness, the speed of sound for the device can be calculated.
Fig. 3 is a simplified diagram illustrating features of a bulk mono-crystalline acoustic resonator according to an example of the invention. The diagram is merely an example, which should not unduly limit the scope of the claims. As shown, the graph 300 illustrates the present invention applied as a bandpass filter for RF signals. A specific frequency range is allowed to pass through the filter, as indicated by the black box rising from the RF spectrum below the wavelength plot. This box matches the signal allowed to pass through the filter in the above figures. Monocrystalline devices can provide better sound quality relative to BAW devices and alleviate the specification requirements for power amplifiers due to lower filter loss. These may result in benefits such as extended battery, efficient spectrum use, uninterrupted caller experience, etc. for devices utilizing the present invention.
Fig. 4 is a simplified diagram illustrating a piezoelectric structure according to an example of the present invention. The diagram is merely an example, which should not unduly limit the scope of the claims. In an example, structure 400 is configured on a bulk substrate member 410 that includes a surface area. In an example, single crystal piezoelectric material epitaxy 420 is formed using a growth process. The growth process may include chemical vapor deposition, molecular beam epitaxial growth, or other techniques to cover the surface of the substrate. In an example, the single crystal piezoelectric material may include a single crystal gallium nitride (GaN) material, a single crystal Al (x) Ga (1-x) N (where 0< x <1.0 (x= "Al mole fraction")) material, a single crystal aluminum nitride (AlN) material, or any combination of the above mentioned substances with each other. Of course, modifications, alternatives, and variations are also possible. Further details of the substrate may be found throughout the present specification and more particularly below.
Fig. 5 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention. The diagram is merely an example, which should not unduly limit the scope of the claims. In an example, the structure 500 is configured to cover a nucleation region 530, the nucleation region 530 covering a surface of the substrate 510. In an example, the nucleation region 530 is one layer or may be multiple layers. The nucleation region is made of a piezoelectric material so as to enable acoustic coupling in the resonator circuit. In an example, the nucleation region is a thin piezoelectric nucleation layer, which may range in thickness from about 0nm to 100nm, which may be used to initiate growth of the single crystal piezoelectric material 520 covering the surface of the substrate. In an example, the nucleation region may be made using a thin SiN or AlN material, but variations can be included. In an example, the thickness of the single crystal piezoelectric material may range from 0.2 μm to 20 μm, but variations are possible. In an example, piezoelectric materials having a thickness of about 2 μm are commonly used in 2GHz acoustic resonator devices. Further details of the substrate may be found throughout the present specification and more particularly below.
Fig. 6 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention. The diagram is merely an example, which should not unduly limit the scope of the claims. In an example, structure 600 is configured using GaN piezoelectric material 620. In an example, each region is monocrystalline or substantially monocrystalline. In an example, the structure is provided using a thin AlN or SiN piezoelectric nucleation region 630, which nucleation region 630 may be To be one or more layers. In an example, the region is unintentionally doped (UID) and is configured to strain GaN on a surface region of the compensation substrate 610. In an example, the nucleation region has a covered GaN single crystal piezoelectric region (with Nd-Na: at 10 14 /cm 3 And 10 (V) 18 /cm 3 Between) and a thickness in the range between 1.0 μm and 10 μm, but variations are possible. Further details of the substrate may be found throughout the present specification and more particularly below.
Fig. 7 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention. The diagram is merely an example, which should not unduly limit the scope of the claims. As shown, structure 700 is configured using AlN piezoelectric material 720. Each region is monocrystalline or substantially monocrystalline. In an example, the structure is provided using a thin AlN or SiN piezoelectric nucleation region 730, which nucleation region 730 may be one or more layers. In an example, the region is unintentionally doped (UID) and is configured to strain AlN on a surface area of the compensation substrate 710. In an example, the nucleation region has a covered AlN single crystal piezoelectric region (with Nd-Na: at 10 14 /cm 3 And 10 (V) 18 /cm 3 Between) and a thickness in the range between 1.0 μm and 10 μm, but variations are possible. Further details of the substrate may be found throughout the present specification and more particularly below.
Fig. 8 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention. The diagram is merely an example, which should not unduly limit the scope of the claims. As shown, structure 800 is configured using AlGaN piezoelectric material 820. Each region is monocrystalline or substantially monocrystalline. In an example, the structure is provided using a thin AlN or SiN piezoelectric nucleation region 830, which nucleation region 830 may be one or more layers. In an example, the region is unintentionally doped (UID) and is configured to strain AlN on a surface area of the compensation substrate 810. In an example, in other features, the AlGaN single crystal piezoelectric layer, wherein Al (x) Ga (1-x) N has an Al molar composition of 0<x<1.0 (Nd-Na: at 10) 14 /cm 3 And 10 (V) 18 /cm 3 Between) a thickness in the range between 1 μm and 10 μm. May be throughout the present specification and more particularly belowFurther details of the substrate were found.
Fig. 9 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention. The diagram is merely an example, which should not unduly limit the scope of the claims. The structure 900 is configured using an AlN/AlGaN piezoelectric material 920. Each region is monocrystalline or substantially monocrystalline. In an example, the structure is provided using a thin AlN or SiN piezoelectric nucleation region 930, which nucleation region 930 may be one or more layers. In an example, the region is unintentionally doped (UID) and is configured to strain AlN on a surface area of the compensation substrate 910. In an example, one or more alternating stacks are formed to cover the nucleation region. In an example, the laminate includes an AlGaN/AlN single crystal piezoelectric layer in which Al (x) Ga (1-x) N has an Al molar composition of 0 <x<1.0; (Nd-Na: at 10) 14 /cm 3 And 10 (V) 18 /cm 3 Between) a thickness in the range between 1.0 μm and 10 μm; alN (1 nm)<Thickness of (L)<30 nm) is used for strain compensating the lattice and allows for thicker AlGaN piezoelectric layers. In an example, the last single crystal piezoelectric layer is AlGaN. In an example, the total stack thickness of the structure is at least 1 μm and less than 10 μm, among others. Further details of the substrate may be found throughout the present specification and more particularly below.
Fig. 10 is a simplified diagram showing a piezoelectric structure according to an alternative example of the present invention. The diagram is merely an example, which should not unduly limit the scope of the claims. As shown, structure 1000 has optional one or more GaN piezoelectric cap layers 1040. In an example, among other things, the cap layer 1040 or region can be configured on any of the foregoing examples. In an example, the cover region may include at least one or more benefits. Such benefits include, inter alia, improved electroacoustic coupling from the upper side metal (electrode 1) into the piezoelectric material, reduced surface oxidation, improved manufacturing, etc. In an example, the GaN cap region has a thickness ranging between 1nm to 10nm, and has Nd-Na: at 10 14 /cm 3 And 10 18 /cm 3 Although variations may exist. Further details of the substrate may be found throughout the present specification and more particularly below.
Fig. 11 is a simplified diagram of a substrate member according to an example of the invention. The diagram is merely an example, which should not unduly limit the scope of the claims. In an example, the single crystal acoustic resonator material 1120 can be a single crystal piezoelectric material epitaxy grown (using CVD or MBE techniques) on the substrate 1110. The substrate 1110 may be a bulk substrate, a composite, or other component. The bulk substrate 1110 is preferably gallium nitride (GaN), silicon carbide (SiC), silicon (Si), sapphire (Al 2O 3), aluminum nitride (AlN), combinations thereof, or the like.
Fig. 12 is a simplified diagram of a substrate member according to an example of the invention. The diagram is merely an example, which should not unduly limit the scope of the claims. In an example, the single crystal acoustic resonator material 1220 can be a single crystal piezoelectric material epitaxy grown (using CVD or MBE techniques) on the substrate 1210. Substrate 1210 may be a bulk substrate, a composite, or other component. The bulk substrate 1210 is preferably gallium nitride (GaN), silicon carbide (SiC), silicon (Si), sapphire (Al 2O 3), aluminum nitride (AlN), combinations thereof, or the like. In an example, the surface area of the substrate is bare and exposed crystalline material.
Fig. 13 is a simplified table showing the characteristics of the present example compared to a conventional filter according to an example of the present invention. As shown, the specifications of the "present example" and "conventional" implementations are shown relative to the standard under "filter scheme".
In an example, gaN, siC, and Al 2 O 3 Oriented c-axis in order to improve or even maximize the polarization field in the piezoelectric material. In an example, the silicon substrate is for the same or similar reasons<111>The orientation, in examples, the substrate may be cut or offset. Although the c-axis or<111>For nominal orientation, but a cut angle between +/-1.5 degrees may be selected for one or more of the following reasons: (1) controllability of the process; (2) maximization of K2 of acoustic resonator, among other reasons. In an example, the substrate is grown on one face (such as a growth face). Ga-faces are the preferred growth surface (due to the more mature process). In an example, the substrate has a substrate resistivity greater than 104ohm-cm, although variations may exist. In an example, the substrate thickness ranges from 100 μm to 1mm as the single crystal piezodeposited material grows.Of course, other variations, modifications, and alternatives are possible.
As used herein, the terms "first," "second," "third," and "nth" are to be understood in a generic sense. Such terms (alone or together) do not necessarily imply order unless understood by one of ordinary skill in the art to be so. In addition, the terms "top" and "bottom" may not have the meaning of referring to the direction of gravity, but should be understood in the ordinary sense. These terms should not unduly limit the scope of the claims.
As used herein, the term substrate is associated with a group III nitride based material including GaN, inGaN, alGaN, or other group III containing alloys or compositions used as raw materials, or AlN or the like. Such starting materials include polar GaN substrates (i.e., substrates having a maximum area nominally in the (hk l) plane, where h=k=0 and l is non-zero), nonpolar GaN substrates (i.e., substrate materials having a maximum area oriented at an angle ranging from about 80 degrees to 100 degrees from the polar orientation described above toward the (hk l) plane, where l=0 and at least one of h and k is non-zero), or semipolar GaN substrates (i.e., substrate materials having a maximum area oriented at an angle ranging from about +0.1 degrees to 80 degrees or 110 degrees to 179.9 degrees from the polar orientation described above toward the (hk l) plane, where l=0 and at least one of h and k is non-zero).
As shown, the present device may be enclosed in a suitable package. As an example, a packaged device may include any combination of the elements described above as well as elements other than the present specification. As used herein, the term "substrate" may refer to a bulk substrate or may include overlying growth structures such as epitaxial or functional regions containing gallium and nitrogen, combinations, and the like.
In an example, the present disclosure provides for the stepwise fabrication of a Single Crystal Acoustic Resonator (SCAR) device. In addition, the present disclosure provides, among other devices, a manufacturing process for manufacturing two or more resonators together to provide a SCAR filter. In an example, the process may be implemented using conventional high volume wafer fabrication facilities for efficient operation and competitive costs. Of course, other variations, modifications, and alternatives are possible.
Fig. 14 to 22 show a method of manufacturing a single crystal acoustic resonator device used in an example of the present invention. These illustrations are merely examples and should not unduly limit the scope of the claims.
An example of a manufacturing process may be briefly described as follows, with reference to the accompanying drawings:
1. starting;
2. providing a substrate member having a surface area, such as a material having a diameter of 150mm or 200 mm;
3. treating the surface area;
4. forming an epitaxial material comprising a single crystal piezoelectric material covering the surface region to a desired thickness;
5. patterning the epitaxial material using a mask and etching process to form a trench region by causing formation of an exposed portion of the surface region by means of a pattern provided in the epitaxial material;
6. Forming an upper side bond pad metal, which may include a laminate having a metal layer that slowly reacts with an etchant in a backside substrate etching process, as defined below;
7. forming an upper electrode member including a first electrode member covering a portion of the epitaxial material and a second electrode member covering the upper side bonding pad metal;
8. masking a portion of the substrate and removing (by etching) the portion of the substrate from the backside to form a first trench region exposing the backside of the epitaxial material overlying the first electrode member and a second trench region exposing the backside of the bond pad metal;
9. forming a backside resonator metal material for covering the exposed portion of the epitaxial material (or piezoelectric film) to form a connection from the epitaxial material to a backside of a bond pad metal coupled to a second electrode member covering the upper side bond pad metal;
10. forming a resonator active region using a mask and etch process while electrically and spatially isolating the first electrode member from the upper second electrode member while also trimming the resonant capacitor;
11. forming a protective dielectric material (e.g. SiO) covering the upper surface area on the upper side surface 2 SiN); and
12. other steps are performed as needed.
The above mentioned steps are provided for forming a resonator device using a single crystal capacitor dielectric. As shown, a pair of electrode members are configured to provide contacts from one side of the device. One of the electrode members uses a backside contact coupled to the metal stack layer to configure the pair of electrodes. Of course, depending on the embodiment, one or more steps may be added, removed, combined, rearranged, or replaced, or have other variations, alternatives, and modifications. Further details of the present manufacturing method may be found throughout the present specification and more particularly below.
As shown in fig. 14, the method begins by providing a substrate member 1410. The substrate member has a surface area, in the example the substrate member thickness (t) is 400 μm, which may have a diameter of 150mm or 200mm diameter material, but variations from 50mm to 300mm may exist.
In an example, a surface area of a substrate member is processed. The treatment typically includes cleaning and/or conditioning. In an example, the treatment occurs in a MOCVD or LPCVD reactor having ammonia gas flowing at a high temperature (e.g., in the range from 940 ℃ to 1100 ℃) and at a pressure ranging from one tenth of atmospheric pressure to one atmosphere. Other processes may also be used, depending on the implementation.
In an example, the method includes forming an epitaxial material, as shown, including a single crystal piezoelectric material 1420 covering a surface region to a desired thickness. Using Trimethylgallium (TMG), trimethylaluminum (TMA), ammonia (NH) 3 ) And hydrogen (H) 2 ) Is prepared by using MOCVD or LPCVD growth apparatus, and exposing to high temperature in the range of 940 to 1100 deg.C in an atmosphere controlled environmentThe extension material grows to a thickness in the range of 0.4 μm to 7.0 μm depending on the target resonant frequency of the capacitor device. The material also had a weight of 10 per square centimeter 4 To 10 12 Although variations may exist.
In an example, epitaxial material 1521 is patterned (fig. 15). Patterning involves masking and etching processes. The mask is typically a photoresist of 1 μm to 3 μm. Chlorine-based chemistry (the gas may include BCl) is used in RIE or ICP etching tools under controlled temperature and pressure conditions 3 、Cl 2 And/or argon) to adjust the etch rate and sidewall profile. Patterning forms trench regions (or via structures) by causing formation of exposed portions of the surface regions by means of a pattern provided in the epitaxial material.
In an example, the method forms an upper side bond pad metal 1630 (fig. 16), which may include a laminate with a metal layer that slowly reacts with the etchant during the backside substrate etching process, as defined below. In examples, the metal is a refractory metal (such as tantalum, molybdenum, tungsten) or other metal (such as gold, aluminum, titanium, or platinum). As can be noted, this metal is then used as a termination region for the backside etch process.
In an example, the method forms an upper side metal structure (fig. 17). As shown, the structure has an upper electrode member comprising a first electrode member 1741 covering a portion of the epitaxial material and a second electrode member 1742 covering the upper bond pad metal. The metal structure is made using refractory metals (such as tantalum, molybdenum, tungsten) and has a thickness of 300nm, selected to define the resonant frequency of the capacitor device.
In an example, the method performs backside processing by flipping the substrate upside down (fig. 18). In an example, the method includes a patterning process of a backside of the substrate. The process uses a masking and removal process by etching a portion of the substrate 1811 from the backside to form a first trench region exposing the backside of the epitaxial material covering the first electrode member and a second trench region exposing the backside of the bond pad metal. In an example, chlorine-based gases are used in a RIE or ICP reactor and etching is performed at a temperature and pressure defined to control etch rate, selectivity, and sidewall slope.
Next, the method includes forming a backside resonator metal material 1943 (fig. 19) for covering the exposed portion of the epitaxial material (or piezoelectric film) to form a connection from the epitaxial material to a backside of the bond pad metal that is coupled to the second electrode member covering the upper side bond pad metal.
As shown, the piezoelectric film 1921 is sandwiched between the pair of electrodes disposed from the upper side and the back side of the substrate member 1911. The component is a <111> oriented silicon substrate having a resistivity greater than 10 ohm-cm.
In an example, the method forms or patterns the resonator active region 2022 using a masking and etching process (fig. 20). The final objective is to electrically and spatially isolate the first electrode member from the upper second electrode member while also trimming the resonant capacitor. In an example, the resonator active area is 200 μm by 200 μm. Patterning uses chlorine-based RIE or ICP etching techniques.
The method forms a thickness of protective material 2150 (fig. 21). In an example, the method forms a combination of silicon dioxide (which forms a compliant structure) and a capping silicon nitride cap material. Silicon dioxide and silicon nitride materials are formed using a combination of silane, nitrogen, and an oxygen source, and deposited using a PECVD chamber.
The method forms first and second electrodes 2261, 2262 (fig. 22) electrically coupled to first and second upper electrodes 2241, 2242, respectively. The intrinsic device is labeled 2201. As desired, in examples, the method may also include other steps or other materials.
In an example, the method may further include one or more of these processes for forming the upper electrode structure, passivation material, and backside processing. In an example, a substrate including a cover structure can include a surface cleaner that uses HCl: h 2 O (1:1) for a predetermined amount of time, followed by rinsing and placing into a sputtering tool.
In use forIn a sputtering tool for forming electrode metallization, the method includes molybdenum (Mo) metal on an exposed upper side of a single crystal piezoelectric material using sputtering techniquesAnd (5) depositing a covering layer. In an example, if desired, a thin titanium bond metal may be deposited before the Mo metal is formed>Among other features, such titanium metal is used as an adhesion layer. In an example, the method performs a masking and patterning process to etch away Mo in the field region (leaving Mo in the probe pad, coplanar waveguide (CPW) interconnect, top plate/first electrode, via bond pad/second electrode, and alignment mask regions). In the example, titanium-aluminum (+)>4 μm) is deposited on the Mo metal in the probe disc and CPW area. In an example, ti/Al is formed on the bond pads for subsequent deposition of copper-tin metal pillars-CuSn pillars and die dicing for wafer level flip chip packaging are deposited. In an example, the method forms a dielectric passivation of the upper surface (25 μm spin polymer photo-dielectric (ELECTRA WLP SH-1-1)), or alternatively, a combination of SiN or SiO2 is formed to cover the upper surface.
In an example, the method includes patterning to open the pads and probe the pads by exposing the photo-dielectric and developing away the dielectric material on the pads. The patterning process completes an upper region of the substrate structure before backside processing is performed. Further details of the present method may be found throughout the present specification and more particularly below.
In an example, a substrate is disposed on a flip-chip wafer and mounted (using photoresist) onto a carrier wafer to begin a backside process. In an example, the backside processing uses a multi-step (e.g., two-step) process. In an example, the wafer is thinned to from about 500 μm to about 300 μm and less using a back side grinding process, which may further include polishing and cleaning. In an example, the backside is coated with a masking material (such as photoresist) and patterned to open the trench regions and bond pad regions for the piezoelectric material. In an example, the method includes a shallow etch process that etches into a substrate (which may be silicon, for example). In an example, the method coats the backside with photoresist to open and expose a backside region of the piezoelectric material, which exposes an entire film region, including the enclosed piezoelectric material and bond pad region. In an example, the method further performs etching until the piezoelectric material and the bond pads are exposed. In an example, as described further below, a "flange" support is a feature derived from a two-step process, although variations are possible.
In an example, the backside is patterned with photoresist to align the backside pad metal (electrode # 2), interconnects, and bond pads. In an example, HCl: H with dilution is used 2 O (1:1) cleaning process or other suitable process. In an example, if the backside of the wafer is patterned with metal in a selectable manner rather than large area layered deposition, the method further includes depositing Mo metal of about 3000A in selected regions. In an example, the metal is formed to reduce parasitic capacitance and enable back-side routing for circuit implementation, which is beneficial for different circuit node interconnections. In an example, if desired, a thin titanium bond metal may be deposited as a bond material prior to Mo
In an example, the method further includes forming a dielectric passivation of the backside surface (25 μm spin polymer photo-dielectric (e.g., ELECTRA WLP SH 32-1-1)) for mechanical stability. In an example, in an alternative example, the method includes depositing SiN and/or SiO 2 To fill the backside trench regions to provide suitable protection, isolation, and to provide other features, if desired.
In an example, the method then separates and/or unloads the completed substrate for transfer into a wafer carrier. The finished substrate has a plurality of devices and a covering of protective material. In an example, the substrate is now ready for sawing and dicing and other back-end processes, such as wafer level packaging, or other techniques. Of course, other variations, modifications, and alternatives are possible.
Fig. 23 shows a circuit diagram of a mono-crystal acoustic resonator device in an example of the invention. The diagram is merely an example, and should not unduly limit the scope of the claims herein. The circuit 2301 shows a block diagram with a piezoelectric film 2322, the piezoelectric film 2322 being sandwiched between a first upper electrode 2361 and a second upper electrode 2362. The connection region 2303 of the block diagram 2301 is shown in a circuit diagram 2302, which circuit diagram 2302 shows an equivalent circuit configuration.
Fig. 24 to 32 show a manufacturing method for a mono-crystal acoustic resonator device in an example of the invention. The diagram is merely an example, and should not unduly limit the scope of the claims herein.
An example of an alternative manufacturing process may be briefly described as follows:
1. starting;
2. providing a substrate member having a surface area, such as a material having a diameter of 150mm or 200 mm;
3. treating the surface region to prepare for epitaxial growth;
4. forming an epitaxial material comprising a single crystal piezoelectric material covering the surface region to a desired thickness;
5. patterning the epitaxial material using a mask and etching process to form a trench region by causing formation of an exposed portion of the surface region by means of a pattern provided in the epitaxial material; alternatively, patterning of the epitaxial material may also occur using laser drilling techniques;
6. Forming an upper side bond pad metal, which may include a laminate having a metal layer that slowly reacts with an etchant during a backside substrate etching process, as defined below;
7. forming an upper electrode member including a first electrode member covering a portion of the epitaxial material and a second electrode member covering the upper side bonding pad metal;
8. masking a portion of the substrate and removing (by etching) the portion of the substrate from the backside to form a single trench region exposing the backside of the epitaxial material overlying the first electrode member and exposing the backside of the bond pad metal; a two-step mask and etch process may be used to form shallow "bank" structures with the goal of providing mechanical support for the epitaxial material;
9. forming a backside resonator metal material for covering the exposed portion of the epitaxial material (or piezoelectric film) to form a connection from the epitaxial material to a backside of a bond pad metal coupled to a second electrode member covering the upper side bond pad metal;
10. forming a resonator active region having low surface leakage current using a passivation process that electrically and spatially isolates the first electrode member from the upper second electrode member while also trimming the resonant capacitor; deposition of dielectric passivation layers (such as SiN or SiO) using PECVD techniques in a controlled temperature and pressure environment using silane gas 2 ) To control the refractive dielectric index;
11. forming a protective dielectric material covering the upper surface area on the upper side surface (options include SiO 2 SiN or spin polymer coating); and
12. other steps are performed as needed.
The above mentioned steps are provided for forming a resonator device using a single crystal capacitor dielectric. As shown, a pair of electrode members are configured to provide contacts from one side of the device. One of the electrode members uses a backside contact coupled to the metal stack layer to configure the pair of electrodes. Of course, depending on the embodiment, one or more steps may be added, removed, combined, rearranged, or replaced, or have other variations, alternatives, and modifications. Further details of the present manufacturing method may be found throughout the present specification and more particularly below.
As shown in fig. 24, the method begins by providing a substrate member 2410. The substrate member has a surface area, in the example the substrate member thickness is 400 μm, which may have a diameter of 150mm or 200mm diameter material, although variations from 50mm to 300mm are possible.
In an example, a surface area of a substrate member is processed. The treatment typically includes cleaning and/or conditioning. In an example, the treatment occurs in a MOCVD or LPCVD reactor having ammonia gas flowing at a high temperature (e.g., in the range from 940 ℃ to 1100 ℃) and at a pressure ranging from one tenth of atmospheric pressure to one atmosphere.
In an example, the method includes forming an epitaxial material, as shown, that includes a single crystal piezoelectric material 2420 that covers a surface region to a desired thickness (t). Using Trimethylgallium (TMG), trimethylaluminum (TMA), ammonia (NH) 3 ) And hydrogen (H) 2 ) Using an MOCVD or LPCVD growth apparatus, and growing the epitaxial material at a high temperature in the range of 940 ℃ to 1100 ℃ to a thickness in the range of 0.4 μm to 7.0 μm in an atmosphere controlled environment, depending on the target resonant frequency of the capacitor device. The material also had a weight of 10 per square centimeter 4 To 10 12 Is a defect density of the (c).
In an example, the epitaxial material 2521 is patterned (fig. 25). Patterning involves masking and etching processes. The mask is typically a photoresist of 1 μm to 3 μm. Chlorine-based chemistry (the gas may include BCl) is used in RIE or ICP etching tools under controlled temperature and pressure conditions 3 、Cl 2 And/or argon) to adjust the etch rate and sidewall profile. Patterning forms trench regions (or via structures) by causing formation of exposed portions of the surface regions by means of a pattern provided in the epitaxial material.
In an example, the method forms an upper side bond pad metal 2630 (fig. 26), which may include a laminate with a metal layer that slowly reacts with an etchant during a backside substrate etching process, as defined below. In examples, the metal is a refractory metal (such as tantalum, molybdenum, tungsten) or other metal (such as gold, aluminum, titanium, or platinum). As noted, this metal is then used as a termination region for the backside etch process.
In an example, the method forms an upper side metal structure (fig. 27). As shown, the structure has an upper electrode member including a first electrode member 2741 covering a portion of the epitaxial material and a second electrode member 2742 covering the upper bond pad metal. The metal structure is made using refractory metals (such as tantalum, molybdenum, tungsten) and has a thickness of 300nm, selected to define the resonant frequency of the capacitor device.
In an example, the method performs backside processing by flipping the substrate upside down (fig. 28). In an example, the method includes a patterning process of a backside of the substrate 2811. The process uses a masking and removal process by etching a portion of the substrate from the backside to form a first trench region exposing the backside of the epitaxial material overlying the first electrode member and a second trench region exposing the backside of the bond pad metal. The support member 2821 may be disposed between two channel regions. In an example, the support member may be recessed from the bottom side surface area, although variations are possible. In an example, a chlorine-based gas is used in a RIE or ICP reactor and etching is performed at a temperature and pressure defined to control etch rate, selectivity, and sidewall slope.
Next, the method includes forming a backside resonator metal material 2943 (fig. 29) for covering the exposed portion of the epitaxial material (or piezoelectric film) to form a connection from the epitaxial material to a backside of the bond pad metal that is coupled to the second electrode member covering the upper side bond pad metal.
As shown, the piezoelectric film 2921 is sandwiched between the pair of electrodes arranged from the upper side and the back side of the substrate member. The component is a <111> oriented silicon substrate having a resistivity greater than 10 ohm-cm.
In an example, the method forms or patterns the resonator active area using a mask and etch process. The final objective is to electrically and spatially isolate the first electrode member from the upper second electrode member while also trimming the resonant capacitor. In an example, the resonator active area is 200 μm by 200 μm. Patterning uses chlorine-based RIE or ICP etching techniques.
The method forms a passivation layer 3050 (fig. 30) and a thickness of protective material 3170 (fig. 31). In an example, the method forms a combination of silicon dioxide (which forms a compliant structure) and a capping silicon nitride cap material. Silicon dioxide and silicon nitride materials are formed using a combination of silane, nitrogen, and an oxygen source, and deposited using a PECVD chamber.
The method forms first and second electrodes 3261, 3262 (fig. 32) electrically coupled to first and second upper electrodes 3241, 3242, respectively. The intrinsic device is labeled 3201. In examples, the method may also include other steps or other materials, as desired.
In an example, the method may further include one or more of these processes for forming the upper electrode structure, passivation material, and backside processing. In an example, the present substrate including the cover structure may include a surface cleaner that uses HCl: h 2 O (1:1) for a predetermined amount of time, followed by rinsing and placing into a sputtering tool.
In a sputtering tool for forming electrode metallization, the method includes molybdenum (Mo) metal on an exposed upper side of a single crystal piezoelectric material using sputtering techniquesAnd (5) depositing a covering layer. In an example, if desired, a thin titanium bond metal may be deposited before the Mo metal is formed>Among other features, such titanium metal is used as an adhesion layer. In an example, the method performs a masking and patterning process to etch away Mo in the field region (leaving Mo in the probe pad, coplanar waveguide (CPW) interconnect, top plate/first electrode, via bond pad/second electrode, and alignment mask regions). In the example, titanium-aluminum (+) >4 μm) is deposited on the Mo metal in the probe disc and CPW area. In an example, ti/Al is formed on the bond pad for subsequent deposition of copper for wafer level flip chip packagingTin metal pillars-CuSn pillars and grain dicing are deposited. In an example, the method forms a dielectric passivation of the upper surface (25 μm spin-on polymer photo-dielectric (ELECTRA WLP SH-1-1)), or alternatively SiN or SiO 2 Is formed to cover the upper surface.
In an example, the method includes patterning to open the pads and probe the pads by exposing the photo-dielectric and developing away the dielectric material on the pads. The patterning process completes an upper region of the substrate structure before backside processing is performed. Further details of the present method may be found throughout the present specification and more particularly below.
In an example, a substrate is disposed on a flip-chip wafer and mounted (using photoresist) onto a carrier wafer to begin a backside process. In an example, the backside processing uses a multi-step (e.g., two-step) process. In an example, the wafer is thinned to from about 500 μm to about 300 μm and less using a backside grinding process, which may further include polishing and cleaning. In an example, the backside is coated with a masking material (such as photoresist) and patterned to open the trench regions and bond pad regions for the piezoelectric material. In an example, the method includes a shallow etch process that etches into a substrate (which may be silicon, for example). In an example, the method coats the backside with photoresist to open and expose a backside region of the piezoelectric material, which exposes an entire film region, including the enclosed piezoelectric material and bond pad region. In an example, the method further performs etching until the piezoelectric material and the bond pads are exposed. In the examples, the "flange" support is a feature derived from a two-step process, although variations are possible.
In an example, the backside is patterned with photoresist to align the backside disk metal (electrode # 2), interconnects, and bond pads. In an example, HCl: H with dilution is used 2 O (1:1) cleaning process or other suitable process. In an example, if the backside of the wafer is patterned with metal in a selectable manner rather than large area layered deposition, the method further includes depositing Mo metal of about 3000A in selected regions. In an example, gold is formedTo reduce parasitic capacitance and to enable back-side wiring for circuit implementation, which is beneficial for different circuit node interconnections. In an example, if desired, a thin titanium bond metal may be deposited as a bond material prior to Mo
In an example, the method further includes forming a dielectric passivation of the backside surface (25 μm spin polymer photo-dielectric (e.g., ELECTRA WLP SH 32-1-1)) for mechanical stability. In an example, in an alternative example, the method includes depositing SiN and/or SiO 2 To fill the backside trench regions to provide suitable protection, isolation, and to provide other features, if desired.
In an example, the method then separates and/or unloads the completed substrate for transfer into a wafer carrier. The finished substrate has a plurality of devices and a covering of protective material. In an example, the substrate is now ready for sawing and dicing and other back-end processes, such as wafer level packaging, or other techniques. Of course, other variations, modifications, and alternatives are possible.
Fig. 33 shows a circuit diagram of a mono-crystal acoustic resonator device in an example of the invention. The diagram is merely an example, and should not unduly limit the scope of the claims herein. The circuit 3301 shows a block diagram with a piezoelectric film 3322, the piezoelectric film 3322 sandwiched between a first upper electrode 3361 and a second upper electrode 3362. The connection area 3303 of the block diagram 3301 is shown in a circuit diagram 3302, which circuit diagram 3302 shows an equivalent circuit configuration.
In an example, the present disclosure shows an acoustic reflector structure that can be added only if needed or desired. In an example, an acoustic reflector on a Single Crystal Acoustic Resonator (SCAR) device may provide improved acoustic coupling, so-called K 2 . In conventional BAW devices, acoustic resonators are inserted into the substrate/carrier material, which, although used, can be cumbersome and ineffective. In an example, because a portion of the substrate is removed from the backside of the single crystal piezoelectric material of the device, at the acoustic resonatorAn acoustic reflector may not be needed or desired on either side. However, in contrast to conventional bulk acoustic wave devices in which the reflector is integrated in the substrate, the acoustic reflector is integrated on the upper side of the device, which can serve, among other functions, two functions: (i) Reducing the humidity sensitivity to the SCAR device, and (ii) providing acoustic isolation from the filter device and the surrounding environment (similar to a faraday cage). These features and further features can be found throughout the present specification and more particularly below.
Fig. 34 and 35 show reflector structures 3400, 3500 configured on a single crystal acoustic resonator device in an example of the invention. As shown, the device has similar features to the devices of the previous examples (fig. 14-22). In addition, the device is configured with a reflector structure comprising alternating quarter wave layers of high acoustic impedance material 3452, 3552 (e.g., metal such as Mo, W, cu, ta) and low impedance material 3451, 3551 (e.g., dielectric such as to form an acoustic reflector over the acoustic resonator device). Fig. 35 also shows a first electrode 3561 horizontally coupled to the first upper electrode 3541 and a second electrode 3562 vertically coupled to the second upper electrode 3542. The intrinsic device is labeled 3501. Of course, other variations, modifications, and alternatives are possible.
Fig. 36 shows a circuit diagram of a reflector structure integrated with the mono-crystal acoustic resonator device of the above-described fig. The diagram is merely an example, and should not unduly limit the scope of the claims herein. As shown, the circuit 3601 is a block diagram having a piezoelectric film 3622, the piezoelectric film 3622 being sandwiched between a first upper electrode 3661 and a second upper electrode 3662. The connection area 3603 of the block diagram 3601 is shown in a circuit diagram 3602, the circuit diagram 3602 showing an equivalent circuit configuration.
In an example, the invention may provide an acoustic resonator device comprising a bulk substrate member and having a surface area and a thickness of material. In an example, a bulk substrate has a first recessed region and a second recessed region, and a support member disposed between the first recessed region and the second recessed region.
In an example, the device has a thickness of single crystal piezoelectric material formed to cover a surface area. In an example, the thickness of single crystal piezoelectric material has an exposed backside region configured with a first recessed region and a contact region configured with a second recessed region. The apparatus has a first electrode member formed to cover an upper portion of the thickness of the single crystal piezoelectric material, and a second electrode member formed to cover a lower portion of the thickness of the single crystal piezoelectric material so as to sandwich the thickness of the single crystal piezoelectric material with the first electrode member and the second electrode member. In an example, the second electrode member extends from a lower portion including the exposed backside region to the contact region. In an example, the device has a second electrode structure configured with a contact area and a first electrode structure configured with a first electrode member.
As shown, the apparatus also has a dielectric material covering an upper surface area of the forming structure that covers the bulk substrate member. The apparatus has an acoustic reflector structure configured to cover the first electrode member, the upper portion, the lower portion, and the second electrode member. As shown, the acoustic reflector structure has a plurality of quarter wave layers spatially disposed within a dielectric material.
Fig. 37 and 38 show reflector structures 3700, 3800 configured on a mono-crystal acoustic resonator device in an example of the invention. The diagram is merely an example, and should not unduly limit the scope of the claims herein. As shown, the device has similar features to the devices of the previous examples (fig. 24 to 32). In addition, the device is configured with a reflector structure comprising alternating quarter wave layers of high acoustic impedance material 3752, 3852 (e.g., metal such as Mo, W, cu, ta) and low impedance material 3751, 3752 (e.g., dielectric such as to form an acoustic reflector over the acoustic resonator device). Fig. 38 also shows a first electrode 3861 horizontally coupled to the first upper electrode 3841 and a second electrode 3862 vertically coupled to the second upper electrode 3842. The intrinsic device is labeled 3801. Of course, other variations, modifications, and alternatives are possible.
Fig. 39 shows a circuit diagram of a reflector structure integrated with the mono-crystal acoustic resonator device of the above-described figures. The diagram is merely an example, and should not unduly limit the scope of the claims herein. As shown, the circuit 3901 is a block diagram having a piezoelectric film 3922, which piezoelectric film 3922 is sandwiched between a first upper electrode 3961 and a second upper electrode 3962. The connection region 3903 of the block diagram 3901 is shown in a circuit diagram 3902, which circuit diagram 3902 shows an equivalent circuit configuration.
In an example, the present invention may provide an acoustic resonator device comprising a bulk substrate member and having a surface area and a thickness of material. In an example, a bulk substrate has a first recessed region and a second recessed region, and a support member disposed between the first recessed region and the second recessed region.
In an example, the device has a thickness of single crystal piezoelectric material formed to cover a surface area. In an example, the thickness of single crystal piezoelectric material has an exposed backside region configured with a first recessed region and a contact region configured with a second recessed region. The apparatus has a first electrode member formed to cover an upper portion of the thickness of the single crystal piezoelectric material and a second electrode member formed to cover a lower portion of the thickness of the single crystal piezoelectric material so as to sandwich the thickness of the single crystal piezoelectric material with the first electrode member and the second electrode member. In an example, the second electrode member extends from a lower portion including the exposed backside region to the contact region. In an example, the device has a second electrode structure configured with a contact area and a first electrode structure configured with a first electrode member.
As shown, the apparatus also has a dielectric material covering an upper surface area of the forming structure that covers the bulk substrate member. The apparatus has an acoustic reflector structure configured to cover the first electrode member, the upper portion, the lower portion, and the second electrode member. As shown, the acoustic reflector structure has a plurality of quarter wave layers spatially disposed within a dielectric material.
Fig. 40 shows a simplified diagram of the bottom and top surface regions of a mono-crystalline acoustic resonator device in an example of the invention. As shown, fig. 40 includes a top view 4001 and a bottom view 4003, each view having a corresponding cross-sectional view 4002 and 4004, respectively. These views show a resonator device similar to the one described above. The piezoelectric film 4020 is arranged to cover the substrate 4010. The upper side of the device comprises a first upper electrode 4041 and a second lower electrode 4042. The etched underside of the substrate includes a lower electrode 4043. Of course, variations, modifications, and alternatives are possible.
Fig. 41 to 44 show simplified examples of a single crystal acoustic resonator device configured in a filter ladder network in an example of the present invention. The diagram is merely an example, and should not unduly limit the scope of the claims herein. In an example, the following description provides illustrations and manufacturing processes for manufacturing together, among other elements, two or more resonators to produce a SCAR filter.
Referring to fig. 41, as shown, the method begins by taking a physical implementation for a SCAR device 4100 (details found in fig. 22) and converting to circuit elements 4102. The circuit element includes a first electrode 4161, a second electrode 4162, and a resonant circuit device 4101 between the two electrodes. In an example, each acoustic resonator device includes a bulk substrate structure having a surface area, and a thickness of material. In an example, a bulk substrate structure has a first recessed region and a second recessed region and a support member disposed between the first recessed region and the second recessed region. Of course, variations may exist.
In an example, the device has a thickness of single crystal piezoelectric material formed to cover a surface area. In an example, the thickness of single crystal piezoelectric material has an exposed backside region configured with a first recessed region and a contact region configured with a second recessed region. In an example, the single crystal piezoelectric material has a thickness greater than 0.4 microns, although variations are possible. In an example, the single crystal piezoelectric material is characterized by less than 10 12 Defect/cm 2 Although variations may exist.
In an example, the apparatus has a first electrode member formed to cover an upper portion of the thickness of single crystal piezoelectric material, and a second electrode member formed to cover a lower portion of the thickness of single crystal piezoelectric material to sandwich the thickness of single crystal piezoelectric material with the first electrode member and the second electrode member extending from the lower portion including the exposed backside region to the contact region. In an example, the second electrode structure is configured with a contact area and the first electrode structure is configured with a first electrode member. In an example, the apparatus also has a dielectric material covering an upper surface area of the forming structure that covers the bulk substrate member and an acoustic reflector structure configured to cover the first electrode member, the upper portion, the lower portion, and the second electrode member.
Alternatively, the device may include any of the other aforementioned features and other items. Of course, other variations, modifications, and alternatives are possible. Further details of the present example may be found throughout the present specification and more particularly below.
Referring to fig. 42, a series shunt configuration 4200 of circuit elements R1, R2, R3, R4, R5, R6, and R7 is shown, although variations and modifications are possible. That is, the configuration may include a greater number of resonators or fewer resonators, depending on the example. As shown, a filter ladder network is illustrated configured for use in an acoustic filter consisting of a series shunt configuration SCARs.
Referring now to fig. 43, a monolithic filter ladder network has a plurality of single crystal acoustic resonator devices designated R1, R2, R3, R4, R5, R6 and R7 disposed on a common substrate member. The circuit diagram 4300 corresponds to the device configuration 4301. Of course, there may be a greater or lesser number of devices already configured together.
In an example, each acoustic resonator device includes a bulk substrate structure having a surface area, and a thickness of material. In an example, a bulk substrate structure has a first recessed region and a second recessed region, and a support member disposed between the first recessed region and the second recessed region. Of course, variations may exist.
In an example, the device has a thickness of single crystal piezoelectric material formed to coverSurface area. In an example, the thickness of single crystal piezoelectric material has an exposed backside region configured with a first recessed region and a contact region configured with a second recessed region. In an example, the single crystal piezoelectric material has a thickness greater than 0.4 microns, although variations are possible. In an example, the single crystal piezoelectric material is characterized by less than 10 12 Defect/cm 2 Although variations may exist.
In an example, the apparatus has a first electrode member formed to cover an upper portion of the thickness of single crystal piezoelectric material, and a second electrode member formed to cover a lower portion of the thickness of single crystal piezoelectric material to sandwich the thickness of single crystal piezoelectric material with the first electrode member and the second electrode member extending from the lower portion including the exposed backside region to the contact region. In an example, the second electrode structure is configured with a contact area and the first electrode structure is configured with a first electrode member. In an example, the apparatus also has a dielectric material covering an upper surface area of the forming structure that covers the bulk substrate member and an acoustic reflector structure configured to cover the first electrode member, the upper portion, the lower portion, and the second electrode member. Alternatively, the device may include any of the other aforementioned features or other items.
As shown, R1, R3, R5, and R7 are configured in a series fashion such that the second electrode structure of R1 is coupled to the first electrode structure of R3, the second electrode structure of R3 is coupled to the first electrode structure of R5, and the second electrode structure of R5 is coupled to the first electrode structure of R7. The circuit further includes a first node disposed between the second electrode structure of R2 and the first electrode structure of R3, a second node disposed between the second electrode structure of R3 and the first electrode structure of R5, and a third node disposed between the second electrode structure of R5 and the first electrode structure of R7.
In an example, R2 is configured between the first node and the lower common electrode such that the first electrode structure of R2 is connected to the first node and the second electrode structure of R2 is connected to the lower common electrode. In an example, R4 is configured between the second node and the lower common electrode such that the first electrode structure is connected to the second node and the second electrode structure is connected to the lower common electrode. In an example, R6 is configured between the third node and the lower common electrode such that the first electrode structure of R6 is connected to the third node and the second electrode structure of R6 is connected to the lower common electrode.
In the example, assuming that a single device has two electrodes on the upper surface (or common side) due to the use of backside vias (from backside electrode 2 to upper side electrode 2), the present circuit is routed accordingly to each SCAR device having backside vias, as shown in the upper right. In an example, 7 backside vias are included, which may consume a larger portion of the substrate structure. Further examples of the present circuit arrangement may be found throughout the present specification and more particularly below.
Referring to fig. 44, the following illustration is a filter configuration with reduced or even minimal use of vias to save substrate area. The circuit diagram 4400 corresponds to the device configuration 4401. In an example, the range of values for the filter configuration drops from 7 to 1, or a single via (shown on the right). In an example, the present illustration uses the following boundary conditions: (1) The input of R1 and the output of R7 are arranged such that they are both upper node 1; (2) Maximizing the number of internal nodes that use common nodes; and (3) common nodes (bottom of R2, R4, R6) are combined on the upper surface of the substrate. As shown, only a single via is included, which results in cost, process and substrate area savings. Of course, there are multiple examples that may range from a single via to 7 vias or more.
In an example, the second electrode is shared on a common internal node using backside connection and metallization. In an example, the first electrodes are shared using an upper side connection that couples the respective first electrodes together. In an example, only R4 has a via structure coupled to the lower common electrode member. Of course, variations, modifications, and alternatives are possible. In an example, fewer vias results in less parasitic capacitance or other loading, and reduces processing, as well as improving substrate usage, which is beneficial for manufacturing highly integrated devices.
Fig. 45 to 52 show simplified examples of a two-element mono-crystal acoustic resonator device and a three-element mono-crystal acoustic resonator device according to examples of the present invention. The diagram is merely an example, and should not unduly limit the scope of the claims herein. In an example, the following description provides illustrations for two-element or three-element SCARs devices that are used at the circuit level to implement filters. In examples, some devices do not include via structures, which is beneficial and more efficient.
Referring to fig. 45, a diagram shows the previously discussed filter ladder 4500, in an example, the filter ladder 4500 can be configured by two-element devices, R1, R2, R3, R4, R5, R6, and R7. As shown, in an example, R1 and R2 may be configured as a two-element device 4501 that forms a series split. As shown, in an example, R6 and R7 may be configured as a two-element device 4502 that forms a series split. Of course, other variations are possible.
Referring to fig. 46, the illustration shows the same filter ladder 4600 previously discussed, in an example, the filter ladder 4600 may be configured as a three-element "Y" device and a "Pi" device. In an example, R1, R2, and R3 may be configured to make up a series-shunt-series "Y" element SCAR device 4601. In an example, R4, R5, and R6 may be configured to make up a split-series-split three-element "Pi" SCAR device 4602. In an example, other three-element "Y" and "Pi" SCAR devices may be constructed from the network, e.g., R5-R6-R7 constitute "Y" devices, and R2-R3-R4 constitute "Pi" devices. Of course, other alternatives, modifications, and variations are possible. In the example referring to fig. 47, the illustration may provide the lowest count of vias in the SCAR filter or any desired count, depending on the implementation. Fig. 47 may show a configuration (4700/4701) similar to the configuration (4400/4401) shown in fig. 44. Further details of the present example may be found throughout the present specification and more particularly below.
In an example, this description shows a series-shunt two-element three-terminal SCAR device through fig. 48. In an example, R1 and R2, as noted, may be configured from two simple SCAR structures, among other combinations. In an example, such a two-element device 4801 has no through-holes, but two terminals (including T1, T2) on the upper side of the substrate member, and a third terminal (T3) on the back side of the substrate. In an example, the description shows a shunt-series two-element three-terminal SCAR device 4800. In an example, referring to R1 to R2 from left to right, a series-shunt device is shown. From right to left, a split-series device is shown and has the same physical structure as the device described above. Of course, other variations, modifications, and alternatives are possible.
Referring now to fig. 49, the description shows a "Y" three terminal SCAR device without a via structure, which reduces the size of the device. As shown and described, in an example, R1, R2, and R3 form a three-element three-terminal "Y" configured SCAR device 4900, among other combinations. Such examples have remarkable features such as a no-via structure, T1, T2, T3 being connections for bonding wires arranged on the upper side of the substrate member. In an example, the device also has a node two (2), which is common to R1, R2 and R3, and is configured "internally" and connected on the back side of the substrate member. In an example, the device is in a serial split serial configuration and has three separate SCARs regions corresponding to the three devices that make up the "Y" configuration device.
Referring now to fig. 50, the description shows a "Y" three terminal SCAR device with a single via structure, which reduces the size of the device. As shown and described, in an example, R3, R4, and R5 form a three-element three-terminal "Y" configured SCAR device 5000, among other combinations. Such examples have significant features such as a single through hole on the backside that is connected to the front or upper side of the substrate member. In an example, the device also has T1 and T2 contacts configured to and accessible to the back side of the substrate. T3 is configured to and accessible to the front side of the substrate. Node one (1) common to R3, R4 and R5 is configured "internally" and connected on the front side of the substrate member. In an example, the device is in a serial split serial configuration and has three separate SCARs regions corresponding to the three devices that make up the "Y" configuration device.
Referring to fig. 51, in an example, the description shows a "Pi" three-terminal SCAR device having a single via structure. As shown, R2, R3, and R4 form, among other combinations, a SCAR device 5100 in a three-element three-terminal "Pi" configuration. Such devices have significant features such as a single backside via structure for routing backside connections to the front side of the substrate. In an example, node two (2) for each of device R2 and device R3 are connected to each other on the back side and form terminal 1 (T1). In the example, terminal 3 (which is T3) is a contact accessible to the front side of the substrate. In an example, node one (1) for each of the devices R3 and R4 is configured to the front side and connected on the front side and forms terminal 2 (T2). In an example, the apparatus is a split series split configuration. In an example, the device includes three separate SCARs regions corresponding to three devices forming three (3) elements that form and make up a "Pi" configuration. Shown is a simplified illustration of a shunt series shunt tri (3) element three-terminal "Pi" SCAR device having a single via structure on the R4 shunt leg or member. Of course, variations, alternatives, and modifications are possible.
Referring to fig. 52, in an example, the description shows a "Pi" three-terminal SCAR device with two (2) backside via structures. As shown, the device has been described in the previous example, however, in this example, the present device has an additional through hole on the terminal 1 (T1), which terminal 1 is configured to the contact area from the back side to the front side. In an example, the device has significant features such as two (2) backside via structures for routing backside contact regions to connect to the front side of the substrate. In the example, the device has a node two (2) for the respective device elements R2 and R3, which node two (2) are connected to each other on the back side and then routed to the front side of the substrate using a via structure to form the terminal 1 (T1). In the example, the terminal 3 (T3) is configured to a contact accessible to the front side of the base substrate. In the example, the node 1 (1) for the respective device elements R3 and R4 is arranged to the front side and connected on the front side and forms the terminal 2 (T2). In an example, the apparatus provides a split series split configuration. In addition, the device includes the use of three separate SCAR regions associated with the device that form and constitute the "Pi" configuration. In the example, shown is a shunt series shunt three element three terminal "Pi" SCAR device 5200, the SCAR device 5200 having a single via on the R4 shunt branch and a single via structure 1, the single via structure 1 connecting internal node two (2) for configuration R2 and R3 and having T1 connected to the front side of the substrate.
While the above is a complete description of the specific embodiments, various modifications, alternative constructions, and equivalents may be used. Accordingly, the foregoing description and drawings should not be deemed to limit the scope of the invention as defined by the appended claims.
Claims (61)
1. A monolithic filter ladder network comprising:
a plurality of mono-crystal acoustic resonator devices numbered R1 through RN disposed on a common substrate member, wherein N is an integer greater than 1, each of the mono-crystal acoustic resonator devices comprising:
a bulk substrate structure of material having a surface region and a thickness, the bulk substrate structure having first and second recessed regions and a support member disposed between the first and second recessed regions, the bulk substrate structure being formed of gallium nitride (GaN), silicon carbide (SiC), silicon (Si), sapphire (Al 2 O 3 ) And aluminum nitride (AlN) or a combination thereof;
a thickness of single crystal piezoelectric material formed to cover the surface region, the thickness of single crystal piezoelectric material having an exposed backside region configured with the first recessed region and a contact region configured with the second recessed region, the single crystal piezoelectric material having a thickness greater than 0.4 microns, the single crystal piezoelectric material characterized by less than 10 12 Defect/cm 2 Dislocation density of (a);
a first electrode member formed to cover an upper portion of the thickness of single crystal piezoelectric material;
a second electrode member formed to cover a lower portion of the thickness of single crystal piezoelectric material to sandwich the thickness of single crystal piezoelectric material with the first electrode member and the second electrode member, the second electrode member extending from the lower portion including the exposed backside region to the contact region;
a second electrode structure electrically coupled to the second electrode member at the contact region;
a first electrode structure electrically coupled to the first electrode member;
a dielectric material covering an upper surface area of a forming structure, the forming structure covering the bulk substrate structure; and
an acoustic reflector structure configured to cover the first electrode member, the upper portion, the lower portion, and the second electrode member.
2. The monolithic filter ladder network of claim 1, wherein the support member is configured in a plane coincident with a bottom surface region of the bulk substrate structure.
3. The monolithic filter ladder network of claim 1, wherein the support member is configured in a plane offset and recessed relative to a bottom surface region of the bulk substrate structure but protruding relative to the first recessed region and the second recessed region.
4. The monolithic filter ladder network of claim 1, wherein the single crystal piezoelectric material is characterized by X-ray diffraction having a sharp peak at a detector angle (2Θ) associated with a single crystal film, and a full width at half maximum (FWHM) of the single crystal piezoelectric material is measured to be less than 1.0 °.
5. The monolithic filter ladder network of claim 1, wherein N equals at least 7, R1, R3, R5, and R7 are configured in series such that the second electrode structure of R1 is coupled to the first electrode structure of R3, the second electrode structure of R3 is coupled to the first electrode structure of R5, and the second electrode structure of R5 is coupled to the first electrode structure of R7; and
the monolithic filter ladder network further comprises: a first node disposed between the second electrode structure of R1 and the first electrode structure of R3; a second node disposed between the second electrode structure of R3 and the first electrode structure of R5; and a third node disposed between the second electrode structure of R5 and the first electrode structure of R7.
6. The monolithic filter ladder network of claim 1, wherein N equals at least 7, R1, R3, R5, and R7 are configured in series such that the second electrode structure of R1 is coupled to the first electrode structure of R3, the second electrode structure of R3 is coupled to the first electrode structure of R5, and the second electrode structure of R5 is coupled to the first electrode structure of R7; and
the monolithic filter ladder network further comprises: a first node disposed between the second electrode structure of R1 and the first electrode structure of R3; a second node disposed between the second electrode structure of R3 and the first electrode structure of R5; and a third node disposed between the second electrode structure of R5 and the first electrode structure of R7; and
wherein R2 is arranged between the first node and a lower common electrode, R4 is arranged between the second node and the lower common electrode, and R6 is arranged between the third node and the lower common electrode.
7. The monolithic filter ladder network of claim 1, wherein N equals at least 7, R1, R3, R5, and R7 are configured in series such that the second electrode structure of R1 is coupled to the first electrode structure of R3, the second electrode structure of R3 is coupled to the first electrode structure of R5, and the second electrode structure of R5 is coupled to the first electrode structure of R7; and
The monolithic filter ladder network further comprises: a first node disposed between the second electrode structure of R1 and the first electrode structure of R3; a second node disposed between the second electrode structure of R3 and the first electrode structure of R5; and a third node disposed between the second electrode structure of R5 and the first electrode structure of R7; and
wherein R2 is configured between the first node and a lower common electrode such that the first electrode structure of R2 is connected to the first node and the second electrode structure of R2 is connected to the lower common electrode; r4 is configured between the second node and the lower common electrode such that the first electrode structure of R4 is connected to the second node and the second electrode structure of R4 is connected to the lower common electrode; and R6 is configured between the third node and the lower common electrode such that the first electrode structure of R6 is connected to the third node and the second electrode structure of R6 is connected to the lower common electrode.
8. The monolithic filter ladder network of claim 1 wherein N is equal to at least 7, R1, R2, and R3 are configured to share a first common node; wherein R3, R4, and R5 are configured to share a second common node; wherein R5, R6, and R7 are configured to share a third common node; and wherein R2, R4, and R6 are configured to share a fourth common node.
9. The monolithic filter ladder network of claim 1, wherein at least one of the plurality of single crystal acoustic resonator devices comprising R1, R2, R3, R4, R5, R6, and R7 comprises a via structure electrically coupled to the contact region.
10. The monolithic filter ladder network of claim 1 wherein N is equal to at least 7, R1, R2, and R3 are configured to share a first common node; wherein R3, R4, and R5 are configured to share a second common node; wherein R5, R6, and R7 are configured to share a third common node; and wherein R2, R4, and R6 are configured to share a fourth common node; and R4 is configured with a via structure coupled to the fourth common node.
11. The monolithic filter ladder network of claim 1, wherein the thickness of single crystal piezoelectric material is selected from at least one of AlN, alGaN, inN, BN and other group iii nitrides.
12. The monolithic filter ladder network of claim 1, wherein the thickness of single crystal piezoelectric material is selected from at least one of single crystal oxide ZnO and MgO comprising a high K dielectric.
13. The monolithic filter ladder network of claim 1, wherein each of the first electrode structure and the second electrode structure is selected from one of tantalum and molybdenum.
14. A configurable monolithic filter ladder network comprising:
a plurality of Single Crystal Acoustic Resonator (SCAR) devices, numbered R1 through RN, disposed on a common substrate member, wherein N is an integer greater than 1, each of said single crystal acoustic resonator devices comprising:
a bulk substrate structure of material having a surface region and a thickness, the bulk substrate structure having first and second recessed regions and a support member disposed between the first and second recessed regions, the bulk substrate structure being formed of gallium nitride (GaN), silicon carbide (SiC), silicon (Si), sapphire (Al 2 O 3 ) And aluminum nitride (AlN) or a combination thereof;
a thickness of single crystal piezoelectric material formed to cover the surface region, the thickness of single crystal piezoelectric material having an exposed backside region configured with the first recessed region and a contact region configured with the second recessed region, the single crystal piezoelectric material having a thickness of greater than 0.4 micronsThickness of the single crystal piezoelectric material is characterized by less than 10 12 Defect/cm 2 Dislocation density of (a);
a first electrode member formed to cover an upper portion of the thickness of single crystal piezoelectric material;
A second electrode member formed to cover a lower portion of the thickness of single crystal piezoelectric material to sandwich the thickness of single crystal piezoelectric material with the first electrode member and the second electrode member, the second electrode member extending from the lower portion including the exposed backside region to the contact region; and
a second electrode structure electrically coupled to the second electrode member at the contact region;
a first electrode structure electrically coupled to the first electrode member;
a dielectric material covering an upper surface area of a forming structure that covers the bulk substrate structure.
15. The configurable monolithic filter ladder network of claim 14, wherein N is equal to at least 7; wherein R1 and R2 are configured to form a series split first two-element device; and R6 and R7 are configured to form a series split second two-element device.
16. The configurable monolithic filter ladder network of claim 14, wherein N is equal to at least 7; and wherein R1, R2, and R3 are configured to form a first series-shunt-series Y-element SCAR device; and R4, R5, and R6 are configured to make up a split-series-split three-element Pi-type SCAR device.
17. The configurable monolithic filter ladder network of claim 14, wherein the thickness of single crystal piezoelectric material is selected from at least one of AlN, alGaN, inN, BN and other group iii nitrides.
18. The configurable monolithic filter ladder network of claim 14, wherein the thickness of single crystal piezoelectric material is selected from at least one of single crystal oxide ZnO and MgO comprising a high K dielectric.
19. The configurable monolithic filter ladder network of claim 14, wherein each of the first electrode structure and the second electrode structure is selected from one of tantalum and molybdenum.
20. A method of manufacturing a monolithic filter ladder network comprising a plurality of mono-crystal acoustic resonator devices numbered R1 through RN disposed on a common substrate member, wherein N is an integer greater than 1, the method comprising:
providing a bulk substrate structure of a material having a surface region and a thickness, the bulk substrate structure having a first recessed region and a second recessed region, and a support member disposed between the first recessed region and the second recessed region, the bulk substrate structure being formed of gallium nitride (GaN), silicon carbide (SiC), silicon (Si), sapphire (Al 2 O 3 ) And aluminum nitride (AlN);
forming a thickness of single crystal piezoelectric material overlying the surface region, the thickness of single crystal piezoelectric material having an exposed backside region provided with the first recessed region and a contact region provided with the second recessed region, the single crystal piezoelectric material having a thickness greater than 0.4 microns, the single crystal piezoelectric material characterized by a thickness of less than 10 12 Defect/cm 2 Dislocation density of (a);
forming a first electrode member covering an upper portion of the thickness of single crystal piezoelectric material;
forming a second electrode member covering a lower portion of the thickness of single crystal piezoelectric material to sandwich the thickness of single crystal piezoelectric material with the first electrode member and the second electrode member, the second electrode member extending from the lower portion including the exposed backside region to the contact region;
forming a first electrode terminal electrically coupled to the first electrode member;
forming a second electrode terminal electrically coupled to the second electrode member at the contact region;
forming a dielectric material covering at least the first and second electrode members and the surface area of the bulk substrate structure; and
An acoustic reflector structure is formed, the acoustic reflector structure being configured to cover the first electrode member, the upper portion, the lower portion, and the second electrode member.
21. The method of claim 20, wherein the support member is configured in a plane coincident with a bottom surface region of the bulk substrate structure.
22. The method of claim 20, wherein the support member is configured in a plane offset and recessed relative to a bottom surface region of the bulk substrate structure, but protruding relative to the first recessed region and the second recessed region.
23. The method of claim 20, wherein the single crystal piezoelectric material is characterized by X-ray diffraction having a sharp peak at a detector angle (2Θ) associated with the single crystal film, and a full width at half maximum (FWHM) of the single crystal piezoelectric material is measured to be less than 1.0 °.
24. The method of claim 20, wherein N is equal to at least 7, R1, R3, R5, and R7 are configured in series such that the second electrode terminal of R1 is coupled to the first electrode terminal of R3, the second electrode terminal of R3 is coupled to the first electrode terminal of R5, and the second electrode terminal of R5 is coupled to the first electrode terminal of R7; and
Wherein the monolithic filter ladder network further comprises: a first node disposed between the second electrode terminal of R1 and the first electrode terminal of R3; a second node disposed between the second electrode terminal of R3 and the first electrode terminal of R5; and a third node disposed between the second electrode terminal of R5 and the first electrode terminal of R7.
25. The method of claim 20, wherein N is equal to at least 7, R1, R3, R5, and R7 are configured in series such that the second electrode terminal of R1 is coupled to the first electrode terminal of R3, the second electrode terminal of R3 is coupled to the first electrode terminal of R5, and the second electrode terminal of R5 is coupled to the first electrode terminal of R7; and
wherein the monolithic filter ladder network further comprises: a first node disposed between the second electrode terminal of R1 and the first electrode terminal of R3; a second node disposed between the second electrode terminal of R3 and the first electrode terminal of R5; and a third node disposed between the second electrode terminal of R5 and the first electrode terminal of R7; and
Wherein R2 is arranged between the first node and a lower common electrode, R4 is arranged between the second node and the lower common electrode, and R6 is arranged between the third node and the lower common electrode.
26. The method of claim 20, wherein N is equal to at least 7, R1, R3, R5, and R7 are configured in series such that the second electrode terminal of R1 is coupled to the first electrode terminal of R3, the second electrode terminal of R3 is coupled to the first electrode terminal of R5, and the second electrode terminal of R5 is coupled to the first electrode terminal of R7; and
wherein the monolithic filter ladder network further comprises: a first node disposed between the second electrode terminal of R1 and the first electrode terminal of R3; a second node disposed between the second electrode terminal of R3 and the first electrode terminal of R5; and a third node disposed between the second electrode terminal of R5 and the first electrode terminal of R7; and
wherein R2 is configured between the first node and a lower common electrode such that the first electrode terminal of R2 is connected to the first node and the second electrode terminal of R2 is connected to the lower common electrode; r4 is configured between the second node and the lower common electrode such that the first electrode terminal of R4 is connected to the second node and the second electrode terminal of R4 is connected to the lower common electrode; and R6 is configured between the third node and the lower common electrode such that the first electrode terminal of R6 is connected to the third node and the second electrode terminal of R6 is connected to the lower common electrode.
27. The method of claim 20, wherein N is equal to at least 7, R1, R2, and R3 are configured to share a first common node; wherein R3, R4, and R5 are configured to share a second common node; wherein R5, R6, and R7 are configured to share a third common node; and wherein R2, R4, and R6 are configured to share a fourth common node.
28. The method of claim 20, wherein at least one of the plurality of mono-crystalline acoustic resonator devices comprising R1, R2, R3, R4, R5, R6, and R7 comprises a via structure electrically coupled to the contact region.
29. The method of claim 20, wherein N is equal to at least 7, R1, R2, and R3 are configured to share a first common node; wherein R3, R4, and R5 are configured to share a second common node; wherein R5, R6, and R7 are configured to share a third common node; and wherein R2, R4, and R6 are configured to share a fourth common node; and R4 is configured with a via structure coupled to the fourth common node.
30. The method of claim 20, wherein the thickness of single crystal piezoelectric material is selected from at least one of AlN, alGaN, inN, BN and other group iii nitrides.
31. The method of claim 20, wherein the thickness of single crystal piezoelectric material is a single crystal oxide of at least one selected from ZnO and MgO of a high K dielectric;
Wherein the high K is characterized by less than 10 12 Defect/cm 2 And is greater than 10 4 Defect/cm 2 Dislocation density of (c) is provided.
32. The method of claim 20, wherein each of the first electrode terminal and the second electrode terminal is selected from one of tantalum and molybdenum.
33. A method of manufacturing a configurable monolithic filter ladder network comprising a plurality of Single Crystal Acoustic Resonator (SCAR) devices numbered R1 through RN configured on a common substrate member, wherein N is an integer greater than 1, the method comprising:
forming a bulk substrate structure of a material having a surface region and a thickness, the bulk substrate structure having a first recessed region and a second recessed region, and a support member disposed between the first recessed region and the second recessed region, the bulk substrate structure being formed of gallium nitride (GaN), silicon carbide (SiC), silicon (Si), sapphire (Al 2 O 3 ) And aluminum nitride (AlN);
forming a thickness of single crystal piezoelectric material overlying the surface region, the thickness of single crystal piezoelectric material having an exposed backside region provided with the first recessed region and a contact region provided with the second recessed region, the single crystal piezoelectric material having a thickness greater than 0.4 microns, the single crystal piezoelectric material characterized by a thickness of less than 10 12 Defect/cm 2 Dislocation density of (a);
forming a first electrode member covering an upper portion of the thickness of single crystal piezoelectric material;
forming a second electrode member covering a lower portion of the thickness of single crystal piezoelectric material to sandwich the thickness of single crystal piezoelectric material with the first electrode member and the second electrode member, the second electrode member extending from the lower portion including the exposed backside region to the contact region; and
forming a first electrode terminal electrically coupled to the first electrode member;
forming a second electrode terminal electrically coupled to the second electrode member at the contact region;
a dielectric material is formed covering at least the first and second electrode members and the surface area of the bulk substrate structure.
34. The method of claim 33, wherein N is equal to at least 7; wherein R1 and R2 are configured to form a series split first two-element device; and R6 and R7 are configured to form a series split second two-element device.
35. The method of claim 33, wherein N is equal to at least 7; and wherein R1, R2, and R3 are configured to form a first series-shunt-series Y-element SCAR device; and R4, R5, and R6 are configured to make up a split-series-split three-element Pi-type SCAR device.
36. The method of claim 33, wherein the thickness of single crystal piezoelectric material is selected from at least one of AlN, alGaN, inN, BN and other group iii nitrides.
37. The method of claim 33, wherein the thickness of single crystal piezoelectric material is a single crystal oxide of at least one selected from ZnO and MgO of a high K dielectric;
wherein the high K is characterized by less than 10 12 Defect/cm 2 And is greater than 10 4 Defect/cm 2 Dislocation density of (c) is provided.
38. The method of claim 33, wherein each of the first electrode terminal and the second electrode terminal is selected from one of tantalum and molybdenum.
39. A method for manufacturing a monolithic filter ladder network comprising a plurality of crystal acoustic resonator devices numbered R1 through RN disposed on a common substrate member, wherein N is an integer greater than 1, the method comprising:
providing a bulk substrate structure of material having a surface region and a thickness, the bulk substrate structure having a first recessed region and a second recessed region, and a support member disposed between the first recessed region and the second recessed region;
forming a thickness of crystalline piezoelectric material overlying the surface region, the thickness of crystalline piezoelectric material having an exposed backside region configured with the first recessed region and a contact region configured with the second recessed region;
Forming a first electrode member covering an upper portion of the thickness of the crystalline piezoelectric material;
forming a second electrode member covering a lower portion of the thickness of the crystalline piezoelectric material to sandwich the thickness of the crystalline piezoelectric material with the first electrode member and the second electrode member, the second electrode member extending from the lower portion including the exposed backside region to the contact region;
forming a first electrode terminal electrically coupled to the first electrode member;
forming a second electrode terminal electrically coupled to the second electrode member at the contact region;
forming a dielectric material covering at least the first and second electrode members and the surface area of the bulk substrate structure; and
an acoustic reflector structure is formed, the acoustic reflector structure being configured to cover the first electrode member, the upper portion, the lower portion, and the second electrode member.
40. The method of claim 39, wherein,the bulk substrate structure is composed of gallium nitride (GaN), silicon carbide (SiC), silicon (Si), sapphire (Al) 2 O 3 ) And aluminum nitride (AlN).
41. The method of claim 39, wherein the crystalline piezoelectric material comprises a single crystal piezoelectric material; wherein the crystalline piezoelectric material has a thickness greater than 0.4 microns, the crystalline piezoelectric material being characterized by a thickness of less than 10 12 Defect/cm 2 Dislocation density of (c) is provided.
42. The method of claim 39, wherein the support member is disposed in a plane coincident with a bottom surface region of the bulk substrate structure.
43. The method of claim 39, wherein the support member is configured in a plane that is offset and recessed relative to a bottom surface region of the bulk substrate structure, but protruding relative to the first recessed region and the second recessed region.
44. The method of claim 39, wherein the crystalline piezoelectric material is characterized by X-ray diffraction having a sharp peak at a detector angle (2Θ) associated with a single crystal film, and a full width at half maximum (FWHM) of the crystalline piezoelectric material is measured to be less than 1.0 °.
45. The method of claim 39, wherein N is equal to at least 7, R1, R3, R5, and R7 are configured in series such that the second electrode terminal of R1 is coupled to the first electrode terminal of R3, the second electrode terminal of R3 is coupled to the first electrode terminal of R5, and the second electrode terminal of R5 is coupled to the first electrode terminal of R7; and
Wherein the monolithic filter ladder network further comprises: a first node disposed between the second electrode terminal of R1 and the first electrode terminal of R3; a second node disposed between the second electrode terminal of R3 and the first electrode terminal of R5; and a third node disposed between the second electrode terminal of R5 and the first electrode terminal of R7.
46. The method of claim 39, wherein N is equal to at least 7, R1, R3, R5, and R7 are configured in series such that the second electrode terminal of R1 is coupled to the first electrode terminal of R3, the second electrode terminal of R3 is coupled to the first electrode terminal of R5, and the second electrode terminal of R5 is coupled to the first electrode terminal of R7; and
wherein the monolithic filter ladder network further comprises: a first node disposed between the second electrode terminal of R1 and the first electrode terminal of R3; a second node disposed between the second electrode terminal of R3 and the first electrode terminal of R5; and a third node disposed between the second electrode terminal of R5 and the first electrode terminal of R7; and
wherein R2 is arranged between the first node and a lower common electrode, R4 is arranged between the second node and the lower common electrode, and R6 is arranged between the third node and the lower common electrode.
47. The method of claim 39, wherein N is equal to at least 7, R1, R3, R5, and R7 are configured in series such that the second electrode terminal of R1 is coupled to the first electrode terminal of R3, the second electrode terminal of R3 is coupled to the first electrode terminal of R5, and the second electrode terminal of R5 is coupled to the first electrode terminal of R7; and
wherein the monolithic filter ladder network further comprises: a first node disposed between the second electrode terminal of R1 and the first electrode terminal of R3; a second node disposed between the second electrode terminal of R3 and the first electrode terminal of R5; and a third node disposed between the second electrode terminal of R5 and the first electrode terminal of R7; and
wherein R2 is configured between the first node and a lower common electrode such that the first electrode terminal of R2 is connected to the first node and the second electrode terminal of R2 is connected to the lower common electrode; r4 is configured between the second node and the lower common electrode such that the first electrode terminal of R4 is connected to the second node and the second electrode terminal of R4 is connected to the lower common electrode; and R6 is configured between the third node and the lower common electrode such that the first electrode terminal of R6 is connected to the third node and the second electrode terminal of R6 is connected to the lower common electrode.
48. The method of claim 39, wherein N is equal to at least 7, R1, R2, and R3 are configured to share a first common node; wherein R3, R4, and R5 are configured to share a second common node; wherein R5, R6, and R7 are configured to share a third common node; and wherein R2, R4, and R6 are configured to share a fourth common node.
49. The method of claim 39, wherein at least one of the plurality of crystal acoustic resonator devices comprising R1, R2, R3, R4, R5, R6, and R7 comprises a via structure electrically coupled to the contact region.
50. The method of claim 39, wherein N is equal to at least 7, R1, R2, and R3 are configured to share a first common node; wherein R3, R4, and R5 are configured to share a second common node; wherein R5, R6, and R7 are configured to share a third common node; and wherein R2, R4, and R6 are configured to share a fourth common node; and R4 is configured with a via structure coupled to the fourth common node.
51. The method of claim 39, wherein the thickness of crystalline piezoelectric material is selected from at least one of AlN, alGaN, inN, BN and other group III nitrides.
52. The method of claim 39, wherein the thickness of crystalline piezoelectric material is a crystalline oxide of at least one selected from the group consisting of ZnO and MgO of a high-K dielectric;
Wherein the high K is characterized by less than 10 12 Defect/cm 2 And is greater than 10 4 Defect/cm 2 Dislocation density of (c) is provided.
53. The method of claim 39, wherein each of the first electrode terminal and the second electrode terminal is selected from one of tantalum and molybdenum.
54. A method of manufacturing a configurable monolithic filter ladder network comprising a plurality of crystal acoustic resonator devices numbered R1 through RN configured on a common substrate member, wherein N is an integer greater than 1, the method comprising:
forming a bulk substrate structure of material having a surface region and a thickness, the bulk substrate structure having a first recessed region and a second recessed region, and a support member disposed between the first recessed region and the second recessed region;
forming a thickness of crystalline piezoelectric material overlying the surface region, the thickness of crystalline piezoelectric material having an exposed backside region configured with the first recessed region and a contact region configured with the second recessed region;
forming a first electrode member covering an upper portion of the thickness of the crystalline piezoelectric material;
forming a second electrode member covering a lower portion of the thickness of the crystalline piezoelectric material to sandwich the thickness of the crystalline piezoelectric material with the first electrode member and the second electrode member, the second electrode member extending from the lower portion including the exposed backside region to the contact region; and
Forming a first electrode terminal electrically coupled to the first electrode member;
forming a second electrode terminal electrically coupled to the second electrode member at the contact region;
a dielectric material is formed covering at least the first and second electrode members and the surface area of the bulk substrate structure.
55. The method of claim 54, wherein the bulk substrate structure is composed of gallium nitride (GaN), silicon carbide (SiC), silicon (Si), sapphire (Al) 2 O 3 ) And aluminum nitride (AlN).
56. The method of claim 54, wherein the crystalline piezoelectric material comprises a single crystal piezoelectric material; wherein the crystalline piezoelectric material has a thickness greater than 0.4 microns, the crystalline piezoelectric material being characterized by a thickness of less than 10 12 Defect/cm 2 Dislocation density of (c) is provided.
57. The method of claim 54, wherein N is equal to at least 7; wherein R1 and R2 are configured to form a series split first two-element device; and R6 and R7 are configured to form a series split second two-element device.
58. The method of claim 54, wherein N is equal to at least 7; and wherein R1, R2, and R3 are configured to form a first series-shunt-series Y-element SCAR device; and R4, R5, and R6 are configured to make up a split-series-split three-element Pi-type SCAR device.
59. The method of claim 54, wherein the thickness of crystalline piezoelectric material is selected from at least one of AlN, alGaN, inN, BN and other group III nitrides.
60. The method of claim 54, wherein the thickness of crystalline piezoelectric material is a crystalline oxide of at least one selected from the group consisting of ZnO and MgO of a high-K dielectric;
wherein the high K is characterized by less than 10 12 Defect/cm 2 And is greater than 10 4 Defect/cm 2 Dislocation density of (c) is provided.
61. The method of claim 54, wherein each of the first electrode terminal and the second electrode terminal is selected from one of tantalum and molybdenum.
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| US14/298,100 | 2014-06-06 | ||
| US14/298,057 US9673384B2 (en) | 2014-06-06 | 2014-06-06 | Resonance circuit with a single crystal capacitor dielectric material |
| CN201911148479.2A CN110912529B (en) | 2014-06-06 | 2015-06-05 | Monolithic filter ladder network and method of manufacturing the same |
| PCT/US2015/034560 WO2015188147A1 (en) | 2014-06-06 | 2015-06-05 | Integrated circuit configured with a crystal acoustic resonator device |
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| CN109150135B (en) * | 2018-11-13 | 2024-05-31 | 杭州左蓝微电子技术有限公司 | Film bulk acoustic resonator based on bonding and processing method thereof |
| CN113411064A (en) * | 2020-03-17 | 2021-09-17 | 济南晶正电子科技有限公司 | Film bulk acoustic wave device and preparation method thereof |
| WO2022087445A1 (en) * | 2020-10-23 | 2022-04-28 | Murata Manufacturing Co., Ltd. | Acoustic wave device |
| CN116803001A (en) * | 2021-01-29 | 2023-09-22 | 株式会社村田制作所 | Acoustic wave device |
| KR20230146636A (en) * | 2021-02-20 | 2023-10-19 | 스펙트론 (선전) 테크놀로지스 씨오., 엘티디 | Resonator devices and acoustic filters |
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| CN110912529A (en) | 2020-03-24 |
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