CN110909514B - Simulation debugging method and simulation debugging platform of matching network - Google Patents
Simulation debugging method and simulation debugging platform of matching network Download PDFInfo
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- CN110909514B CN110909514B CN201911198425.7A CN201911198425A CN110909514B CN 110909514 B CN110909514 B CN 110909514B CN 201911198425 A CN201911198425 A CN 201911198425A CN 110909514 B CN110909514 B CN 110909514B
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- 238000004088 simulation Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000005070 sampling Methods 0.000 claims abstract description 18
- 239000003990 capacitor Substances 0.000 claims description 20
- 230000005669 field effect Effects 0.000 claims description 17
- 229910044991 metal oxide Inorganic materials 0.000 claims description 17
- 150000004706 metal oxides Chemical class 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000004891 communication Methods 0.000 claims description 6
- 238000007493 shaping process Methods 0.000 claims description 3
- 238000011161 development Methods 0.000 abstract description 3
- 238000012827 research and development Methods 0.000 abstract 1
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Abstract
The invention discloses a simulation debugging method and a debugging platform of a matching network, comprising the following steps: outputting a signal source by using a signal generator, and controlling the frequency, the phase and the amplitude of the signal source by an upper computer; the lower computer is used for controlling the direct current power supply to supply power for the power device simulation network, and the power device simulation network converts the direct current power supply into an output signal of the simulated power device under the driving of the signal generator and outputs the output signal; the debugging object is a matching network to be debugged, and the matching network to be debugged matches signals output by the power device simulation network and then transmits the signals to the load; collecting voltage and current of an output end of a matching network to be debugged by using a sampling circuit, and feeding back the voltage and current to a lower computer; the lower computer records the sampling data of the voltage and the current and feeds the sampling data back to the upper computer. The invention uses the analog network to replace the true machine for debugging, can effectively reduce the time for debugging the matching network, greatly reduce the development period, reduce the research and development cost, and has the advantages of convenient control, high response speed and the like.
Description
Technical Field
The invention relates to the technical field of circuit debugging, in particular to a matching network debugging simulation method and a simulation debugging platform.
Background
Matching networks are one of the most important concepts in radio frequency circuits and are important factors that must be considered in circuit design. The matching network enables the power device and the load to be subjected to conjugate matching, and important parameters such as the output efficiency, the power capacity and the working stability of the radio frequency power supply are related.
In the debugging process, the matching network may be affected by factors such as installation position, installation size, space size and medium, and the debugging process is complicated. The object of matching network debugging is usually the physical signals of voltage, current phase, amplitude, frequency, etc. in the working process, and these signals can be completed under small signals.
The characteristic parameters of the radio frequency power supply after the power device is packaged are generally stable, and can be described by a nonlinear equation. Therefore, the output of the power device in the system can be simulated and calculated by utilizing a digital technology, the high-power output of the power device is converted into a simulated low-power output signal, and then the simulated low-power output signal is connected into the matching network, so that the matching network to be debugged is debugged under the environment meeting the overall performance index. The difficulty is that the high power device output is converted to an analog low power output signal.
Disclosure of Invention
The invention aims to provide a matching network debugging simulation method and a matching network debugging platform.
In order to achieve the above purpose, the technical scheme of the invention is as follows: a simulation debugging method of a matching network comprises the following steps:
step 2, controlling a direct current power supply by using a lower computer, providing a power supply for a power device simulation network, and converting the direct current power supply into an output signal of a simulated power device by the power device simulation network under the drive of a signal generator and outputting the output signal;
step 3, the debugging object is a matching network to be debugged, and the matching network to be debugged matches signals output by the power device simulation network and then transmits the signals to the load;
and step 5, the lower computer records the sampling data of the voltage and the current and feeds the sampling data back to the upper computer.
Further, the power device simulation network comprises a first resistor, a second resistor and a first capacitor which are connected in parallel, wherein the first resistor is connected in series with a first switch, the second resistor is connected in series with a second capacitor, the first capacitor is connected in series with a second switch, the second resistor is connected in parallel with a third switch, and the second capacitor is connected in parallel with a fourth switch; the output end of the first resistor is connected with the input end of the MOSFET, the first output end of the MOSFET is connected with the input end of the matching network to be debugged, the second output end of the MOSFET is connected to the output end of the direct current power supply through an inductor, and the third output end of the MOSFET is grounded.
Further, the MOSFET is a low-voltage low-power MOSFET, and the model of the MOSFET is determined by the simulated power device.
A matching network simulation debugging platform comprises
A signal generator for outputting a signal source;
the upper computer is connected with the signal generator and used for setting output parameters of the signal generator, carrying out data communication with the lower computer and storing data of the lower computer;
the power device simulation network converts a direct-current power supply into an output signal of a simulated power device under the driving of the signal generator;
the lower computer is respectively connected with the upper computer and the direct current power supply, is responsible for carrying out data communication with the upper computer, controls the direct current power supply and records sampling data of voltage and current;
the matching network to be debugged is connected with the output end of the power device simulation network and is used for shaping the simulation signal output by the power device simulation network into a sine power signal to be output, so that the power device and the load are subjected to conjugate matching, and the output efficiency is maximized;
the sampling circuit is used for collecting the voltage and the current of the output end of the matching network to be debugged and feeding the voltage and the current back to the lower computer;
and a load for consuming the output power.
Further, the power device simulation network comprises a first resistor, a second resistor and a first capacitor which are connected in parallel, wherein the first resistor is connected in series with a first switch, the second resistor is connected in series with a second capacitor, the first capacitor is connected in series with a second switch, the second resistor is connected in parallel with a third switch, and the second capacitor is connected in parallel with a fourth switch; the output end of the first resistor is connected with the input end of the MOSFET, the first output end of the MOSFET is connected with the input end of the matching network to be debugged, the second output end of the MOSFET is connected to the output end of the direct current power supply through an inductor, and the third output end of the MOSFET is grounded.
Further, the MOSFET is a low-voltage low-power MOSFET, and the model of the MOSFET is determined by the simulated power device.
Further, the parameters are frequency, phase and amplitude of the signal source.
The beneficial effects of the invention are as follows: according to the invention, the simulation network is used for debugging instead of a true machine, so that the time for debugging the matching network can be effectively reduced, and meanwhile, the whole debugging process is realized under low pressure, so that the debugging safety is improved, and the risk is reduced. The invention can greatly reduce the development period, reduce the development cost, and has the advantages of convenient control, high response speed and the like.
Drawings
FIG. 1 is a schematic diagram of the structural principle of a matching network simulation debugging platform of the present invention;
fig. 2 is a schematic circuit diagram of a power device simulation network according to the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.
A simulation debugging method of a matching network comprises the following steps:
the method comprises the following steps:
step 2, controlling a direct current power supply by using a lower computer, providing a power supply for a power device simulation network, and converting the direct current power supply into an output signal of a simulated power device by the power device simulation network under the drive of a signal generator and outputting the output signal;
step 3, the debugging object is a matching network to be debugged, and the matching network to be debugged matches signals output by the power device simulation network and then transmits the signals to the load;
and step 5, the lower computer records the sampling data of the voltage and the current and feeds the sampling data back to the upper computer.
1-2, a matching network simulation debugging platform comprises
A signal generator for outputting a signal source;
the upper computer is connected with the signal generator and used for setting output parameters of the signal generator, carrying out data communication with the lower computer and storing data of the lower computer;
the power device simulation network converts a direct-current power supply into an output signal of a simulated power device under the driving of the signal generator;
the lower computer is respectively connected with the upper computer and the direct current power supply, is responsible for carrying out data communication with the upper computer, controls the direct current power supply and records sampling data of voltage and current;
the matching network to be debugged is connected with the output end of the power device simulation network and is used for shaping the simulation signal output by the power device simulation network into a sine power signal to be output, so that the power device and the load are subjected to conjugate matching, and the output efficiency is maximized;
the sampling circuit is used for collecting the voltage and the current of the output end of the matching network to be debugged and feeding the voltage and the current back to the lower computer;
and a load for consuming the output power.
As shown in fig. 2, the power device simulation network includes a first resistor R1, a second resistor R2, and a first capacitor C1 connected in parallel, where the first resistor R1 is connected in series with a first switch S1, the second resistor R2 is connected in series with a second capacitor C2, the first capacitor is connected in series with a second switch S2, the second resistor R2 is connected in parallel with a third switch S3, and the second capacitor is connected in parallel with a fourth switch S4; the output end of the first resistor R1 is connected with the input end of the metal oxide semiconductor field effect transistor U1, the first output end of the metal oxide semiconductor field effect transistor U1 is connected with the input end of the matching network to be debugged, the second output end is connected to the output end of the direct current power supply through an inductor, and the third output end is grounded.
The metal oxide semiconductor field effect transistor adopts a low-voltage small-power MOSFET, and the specific type and model are determined according to the simulated power device.
Depending on the type of power device, the impedance between the signal source and the input of the low power MOSFET U1 is set to Rp, where Rp is determined by the involved devices during the actual debugging process, as in fig. 2, if S1-S3 are turned on and S4 are turned off, the impedance is described as: rp=r2.
U1 also needs to be selected according to the debugged power device, and for different U1, the output is different under the same lower computer control and signal source, and the ideal low-power MOSFET is taken as an example for analysis, after the noise is subjected to Fourier transform, the output signal after U1 is described as:
in the method, in the process of the invention,
vector voltage for output power, +.>
For the vector current of the output power, an and Bn are the amplitudes of the different harmonics, n is the harmonic order, ω is the frequency of the voltage and current signal, t is the time,/v,>
is the phase of the voltage signal->
I is the phase of the current signal and i is the magnitude of the highest harmonicIs small. />
The above formula is the output signal of the power analog device, the parameters in the formula are set by the upper computer, the lower computer and the signal generator, and the influence of noise is not considered, and in the actual process, the output of the MOSFET has noise.
The described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
Claims (5)
1. The simulation debugging method of the matching network is characterized by comprising the following steps of:
step 1, outputting a signal source by using a signal generator, and controlling the frequency, the phase and the amplitude of the signal source by an upper computer;
step 2, controlling a direct current power supply by using a lower computer, providing a power supply for a power device simulation network, and converting the direct current power supply into an output signal of a simulated power device by the power device simulation network under the drive of a signal generator and outputting the output signal;
step 3, the debugging object is a matching network to be debugged, and the matching network to be debugged matches signals output by the power device simulation network and then transmits the signals to the load;
step 4, collecting voltage and current of the output end of the matching network to be debugged by utilizing a sampling circuit, and feeding back the voltage and current to a lower computer;
step 5, the lower computer records sampling data of voltage and current and feeds the sampling data back to the upper computer;
the power device simulation network comprises a first resistor, a second resistor and a first capacitor which are connected in parallel, wherein the first resistor is connected in series with a first switch, the second resistor is connected in series with a second capacitor, the first capacitor is connected in series with a second switch, the second resistor is connected in parallel with a third switch, and the second capacitor is connected in parallel with a fourth switch; the output end of the first resistor is connected with the input end of the metal oxide semiconductor field effect transistor, the first output end of the metal oxide semiconductor field effect transistor is connected with the input end of the matching network to be debugged, the second output end of the metal oxide semiconductor field effect transistor is connected to the output end of the direct current power supply through an inductor, and the third output end of the metal oxide semiconductor field effect transistor is grounded.
2. The method for debugging the matching network according to claim 1, wherein the metal oxide semiconductor field effect transistor is a low-voltage low-power metal oxide semiconductor field effect transistor, and the model of the metal oxide semiconductor field effect transistor is determined by the power device to be simulated.
3. A matching network simulation debugging platform is characterized by comprising
A signal generator for outputting a signal source;
the upper computer is connected with the signal generator and used for setting output parameters of the signal generator, carrying out data communication with the lower computer and storing data of the lower computer;
the power device simulation network converts a direct-current power supply into an output signal of a simulated power device under the driving of the signal generator;
the lower computer is respectively connected with the upper computer and the direct current power supply, is responsible for carrying out data communication with the upper computer, controls the direct current power supply and records sampling data of voltage and current;
the matching network to be debugged is connected with the output end of the power device simulation network and is used for shaping the simulation signal output by the power device simulation network into a sine power signal to be output, so that the power device and the load are subjected to conjugate matching, and the output efficiency is maximized;
the sampling circuit is used for collecting the voltage and the current of the output end of the matching network to be debugged and feeding the voltage and the current back to the lower computer;
a load for consuming the output power;
the power device simulation network comprises a first resistor, a second resistor and a first capacitor which are connected in parallel, wherein the first resistor is connected in series with a first switch, the second resistor is connected in series with a second capacitor, the first capacitor is connected in series with a second switch, the second resistor is connected in parallel with a third switch, and the second capacitor is connected in parallel with a fourth switch; the output end of the first resistor is connected with the input end of the metal oxide semiconductor field effect transistor, the first output end of the metal oxide semiconductor field effect transistor is connected with the input end of the matching network to be debugged, the second output end of the metal oxide semiconductor field effect transistor is connected to the output end of the direct current power supply through an inductor, and the third output end of the metal oxide semiconductor field effect transistor is grounded.
4. A matching network simulation debugging platform as claimed in claim 3, wherein the metal oxide semiconductor field effect transistor is a low voltage low power metal oxide semiconductor field effect transistor, and the model of the metal oxide semiconductor field effect transistor is determined by the power device to be simulated.
5. A matching network simulation debugging platform as claimed in claim 3, wherein the parameters are frequency, phase and amplitude of the signal source.
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