CN110867452B

CN110867452B - Circuit structure

Info

Publication number: CN110867452B
Application number: CN201810985899.5A
Authority: CN
Inventors: 洪裕杰; 林冠峄; 卢俊宇; 叶佳俊
Original assignee: E Ink Holdings Inc
Current assignee: E Ink Holdings Inc
Priority date: 2018-08-28
Filing date: 2018-08-28
Publication date: 2022-02-01
Anticipated expiration: 2038-08-28
Also published as: CN110867452A

Abstract

The invention discloses a circuit structure, comprising a flexible substrate, an inorganic barrier layer, a first wire, a second wire, a third wire, a fourth wire, an organic dielectric layer, a first conductive through hole, and a second conductive wire through hole. The inorganic barrier layer is disposed on the flexible substrate. The first wire and the second wire are arranged on the inorganic barrier layer and contact the inorganic barrier layer. The first wire and the second wire are separated from each other. The organic dielectric layer is disposed on the first wire and the second wire. The third wire is disposed in the organic dielectric layer. The fourth wire is disposed on the organic dielectric layer. The first conductive via is disposed in the organic dielectric layer and contacts the first wire and the third wire. The second conductive via is disposed in the organic dielectric layer and contacts the second wire and the fourth wire. The wires in the circuit structure disclosed herein do not have the problem of being easily broken.

Description

Circuit structure

Technical Field

The invention relates to a circuit structure.

Background

Generally, an Organic thin film transistor Array (Organic TFT Array) display device has an Organic buffer layer, an Organic gate isolation layer, and an Organic passivation layer sequentially stacked on an edge of a flexible substrate. A data line is disposed between the organic buffer layer and the organic gate isolation layer, and a gate line is disposed between the organic gate isolation layer and the organic protective layer. The data lines and the gate lines are connected to an Integrated Circuit (IC) chip and a flexible Circuit board, respectively.

However, the data lines and the gate lines are generally made of metal materials, and the organic buffer layer, the organic gate isolation layer, and the organic protection layer are generally made of organic materials. When a metal wiring is formed on an organic material, there is a problem of poor adhesion. Therefore, when the display device is bent due to stress, the metal circuit with poor adhesion is easily displaced and broken.

Disclosure of Invention

The invention aims to provide a circuit structure, wherein a lead in the circuit structure does not have the problem of easy breakage.

One aspect of the present invention provides a circuit structure including a flexible substrate, an inorganic barrier layer, a first conductive line, a second conductive line, a third conductive line, a fourth conductive line, an organic dielectric layer, a first conductive via, and a second conductive via. The inorganic barrier layer is disposed on the flexible substrate. The first conductive line and the second conductive line are disposed on the inorganic barrier layer and contact the inorganic barrier layer. The first conductive line and the second conductive line are separated from each other. The organic dielectric layer is disposed on the first conductive line and the second conductive line. The third conductive line is disposed in the organic dielectric layer. The fourth conductive line is disposed on the organic dielectric layer. The first conductive via is disposed in the organic dielectric layer and contacts the first conductive line and the third conductive line. The second conductive via is disposed in the organic dielectric layer and contacts the second conductive line and the fourth conductive line.

In some embodiments of the invention, the first conductive line and the second conductive line are substantially parallel.

In some embodiments of the present invention, the first conductive line and the second conductive line have a distance of 4 to 10 micrometers.

In some embodiments of the present invention, the organic dielectric layer has a first through hole and a second through hole. The first through hole exposes the exposed portion of the first conductive line, and the second through hole exposes the exposed portion of the second conductive line.

In some embodiments of the present invention, the line structure further comprises a first conductive pad layer and a second conductive pad layer. The first conductive pad layer covers sidewalls of the first through hole and an exposed portion of the first conductive line. The second conductive pad layer covers sidewalls of the second through hole and an exposed portion of the second conductive line.

In some embodiments of the present invention, the third conductive line contacts the first conductive pad layer and the fourth conductive line contacts the second conductive pad layer.

In some embodiments of the invention, the circuit structure further comprises an integrated circuit die. The integrated circuit chip is electrically connected with the first conducting wire and the second conducting wire. The first conductive via is horizontally spaced from the edge of the integrated circuit wafer by 300-600 microns, and the second conductive via is horizontally spaced from the edge of the integrated circuit wafer by 300-600 microns.

In some embodiments of the present invention, the organic dielectric layer includes an organic buffer layer and an organic gate isolation layer disposed on the organic buffer layer. The third wire is arranged between the organic buffer layer and the organic grid isolation layer, and the fourth wire is arranged on the organic grid isolation layer.

In some embodiments of the invention, the first and second wires comprise molybdenum, molybdenum-chromium alloy, aluminum-neodymium alloy, or titanium.

Another aspect of the present invention is to provide a circuit structure including a flexible substrate, an inorganic barrier layer, a first conductive line, a second conductive line, a third conductive line, a fourth conductive line, a fifth conductive line, an organic dielectric layer, a first conductive via, and a second conductive via. The inorganic barrier layer is disposed on the flexible substrate. The first conductive line, the second conductive line, and the third conductive line are disposed on the inorganic barrier layer and contact the inorganic barrier layer. The first conductive line, the second conductive line, and the third conductive line are separated from each other. The first conducting wire is provided with a first conducting connection area, the second conducting wire is provided with a second conducting connection area, and the third conducting wire is provided with a third conducting connection area and a fourth conducting connection area. The organic dielectric layer is disposed on the first conductive line and the second conductive line. The fourth conductive line is disposed in the organic dielectric layer. The fifth conductive line is disposed on the organic dielectric layer. The first conductive via is disposed in the organic dielectric layer and contacts the first conductive line and the fourth conductive line. The second conductive via is disposed in the organic dielectric layer and contacts the second conductive line and the fifth conductive line.

In some embodiments of the invention, the first, second, and third wires comprise titanium, nickel boride, or indium tin oxide.

In some embodiments of the invention, the line structure further comprises a protective layer. The passivation layer is disposed between the inorganic barrier layer and the organic dielectric layer and covers the first conductive line, the second conductive line, and the third conductive line. The passivation layer has a first through hole exposing the first conductive connection region of the first conductive line, a second through hole exposing the second conductive connection region of the second conductive line, a third through hole exposing the third conductive connection region of the third conductive line, and a fourth through hole exposing the fourth conductive connection region of the third conductive line.

In some embodiments of the present invention, the circuit structure further includes a first conductive pad layer, a second conductive pad layer, a third conductive pad layer, and a fourth conductive pad layer. The first conductive pad layer covers sidewalls of the first through hole and the first conductive connection region of the first conductive line. The second conductive pad layer covers sidewalls of the second through hole and a second conductive connection region of the second conductive line. The third conductive pad layer covers sidewalls of the third through hole and a third conductive connection region of the third conductive line. The fourth conductive pad layer covers sidewalls of the third through holes and a fourth conductive connection region of the third conductive line.

Compared with the prior art, the wire in the circuit structure has the beneficial effect of being not easy to break.

The above description will be described in detail by embodiments, and further explanation will be provided for the technical solution of the present invention.

Drawings

Fig. 1 is a schematic top view of a display device according to an embodiment of the invention.

Fig. 2 is a partially enlarged view of a region of the circuit structure of the display device of fig. 1.

Fig. 3A is a schematic cross-sectional view of a circuit structure along a cut line a-a' according to an embodiment of the invention.

Fig. 3B is a schematic cross-sectional view of the circuit structure along the line B-B' according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a single sub-pixel in a display area of a display device according to an embodiment of the invention.

Fig. 5A is a schematic cross-sectional view of a circuit structure along a cut line a-a' according to an embodiment of the invention.

Fig. 5B is a schematic cross-sectional view of the circuit structure along the line B-B' according to an embodiment of the present invention.

FIG. 6A is a schematic cross-sectional view of a trace structure along lines A-A 'and C-C' according to an embodiment of the present invention.

FIG. 6B is a cross-sectional view of a trace structure along lines B-B 'and C-C' according to an embodiment of the present invention.

FIG. 7A is a cross-sectional view of a trace structure along lines A-A 'and C-C' according to an embodiment of the present invention.

FIG. 7B is a cross-sectional view of a trace structure along lines B-B 'and C-C' according to an embodiment of the present invention.

Fig. 8A is a schematic top view of a display device according to an embodiment of the invention.

FIG. 8B is a cross-sectional view along line D-D' of a circuit structure according to an embodiment of the present invention.

Detailed Description

In order to make the description of the invention more complete and thorough, the following illustrative description is set forth in terms of embodiments and specific examples of the invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The embodiments disclosed below may be combined with or substituted for one another where appropriate, and additional embodiments may be added to one embodiment without further recitation or description. In the following description, numerous specific details are set forth to provide a thorough understanding of the following embodiments. However, embodiments of the invention may be practiced without these specific details.

The specific embodiments of the components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present invention. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, reference numerals and/or letters may be repeated in various embodiments of the present invention. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "beneath," "above," "over," and the like, are used herein for convenience in describing the relative relationship of one element or feature to another element or feature, as illustrated in the figures. The true meaning of these spatially relative terms encompasses other orientations. For example, when the drawings are turned over 180 degrees, the relationship of one element to another may change from "below" to "above" or "over". Spatially relative descriptors used herein should be interpreted as such.

The embodiments of the present invention will be described in detail below, but the present invention is not limited to the scope of the examples.

Fig. 1 is a schematic top view illustrating a display device 200 according to an embodiment of the invention. The display device 200 has a display area 202. The line structure 100A is located at the edge of the display device 200, for example, outside the display area 202. The integrated circuit chip 300 and the flexible circuit board 500 are located outside the display area 202.

Please refer to fig. 2, fig. 3A, and fig. 3B simultaneously. Fig. 2 is a partially enlarged view of a region R1 of the circuit structure 100A of the display device 200 of fig. 1. Fig. 3A and 3B are schematic cross-sectional views of the circuit structure 100A along the tangent line a-a 'and the tangent line B-B' of fig. 2 according to an embodiment of the invention.

The circuit structure 100A includes a flexible substrate 110, an inorganic barrier layer 114, a first conductive line 121, a second conductive line 122, a third conductive line 141, a fourth conductive line 142, an organic dielectric layer 130, an organic passivation layer 160, a first conductive via C1, and a second conductive via C2.

As shown in fig. 3A and 3B, the inorganic barrier layer 114 is disposed on the flexible substrate 110. In some embodiments, the flexible substrate 110 includes Polyimide (PI) or Polyethylene terephthalate (PET), but not limited thereto. In some embodiments, the inorganic barrier layer 114 includes silicon nitride or silicon oxide, but is not limited thereto.

The first conductive line 121 and the second conductive line 122 are disposed on the inorganic barrier layer 114 and contact the inorganic barrier layer 114. In addition, the first and second

conductive lines

121 and 122 are separated from each other. In some embodiments, the first conductive line 121 and the second conductive line 122 include a metal material such as molybdenum, molybdenum-chromium alloy, aluminum-neodymium alloy, or titanium, but not limited thereto. It is understood that since the inorganic barrier layer 114 is not an organic material, the first and second

conductive lines

121 and 122 on the inorganic barrier layer 114 have excellent adhesion to the inorganic barrier layer 114.

According to various embodiments, the integrated circuit die 300 used in the present invention may be an integrated driver die that integrates data line driving functions and gate line driving functions. Therefore, the integrated circuit chip 300 has a first metal bump 311 (labeled in fig. 3A) and a second metal bump 312 (labeled in fig. 3B). The first metal bump 311 and the second metal bump 312 may be, for example, chip pins, for electrically connecting to the data line and the gate line, respectively. In some embodiments, the first conductive line 121 is used to connect the metal bump 311 of the ic chip 300 and the third conductive line 141 (e.g., a data line), and the second conductive line 122 is used to connect the metal bump 312 of the ic chip 300 and the fourth conductive line 142 (e.g., a gate line). Specifically, as shown in fig. 2, the first conductive line 121 and the second conductive line 122 are substantially parallel, and the first conductive line 121 and the second conductive line 122 have a distance D1 therebetween. The distance D1 is 4-10 μm.

As shown in fig. 3A and 3B, the organic dielectric layer 130 is disposed on the inorganic barrier layer 114, and includes an organic buffer layer 131 and an organic gate isolation layer 132. The organic gate isolation layer 132 is disposed on the organic buffer layer 131. The organic protection layer 160 is disposed on the organic gate isolation layer 132. Specifically, the third conductive line 141 is disposed between the organic buffer layer 131 and the organic gate isolation layer 132, and the fourth conductive line 142 is disposed on the organic gate isolation layer 132. In some embodiments, the third conductive line 141 is, for example, a data line, and the fourth conductive line 142 is, for example, a gate line. In some embodiments, the third and fourth

conductive lines

141 and 142 include a metal material such as aluminum, copper, nickel, or silver.

The first conductive via C1 is disposed in the organic buffer layer 131, and two ends of the first conductive via C1 contact the first conductive line 121 and the third conductive line 141, respectively, so that the first conductive line 121 is electrically connected to the third conductive line 141. Similarly, the second conductive via C2 is disposed in the organic buffer layer 131 and the organic gate isolation layer 132, and two ends of the second conductive via C2 contact the second conductive line 122 and the fourth conductive line 142, respectively, so that the second conductive line 122 is electrically connected to the fourth conductive line 142.

It should be noted that, in the prior art, data lines and gate lines near the integrated circuit wafer 300 (e.g., within a horizontal distance of about 300 microns to 600 microns from the edge of the integrated circuit wafer 300) are prone to being pulled and broken. However, in the circuit structure 100A of the present invention, the first conductive line 121 and the second conductive line 122 are disposed on the inorganic barrier layer 114. As described above, the first and second

conductive lines

121 and 122 have excellent adhesion to the inorganic barrier layer 114. Thus, the problem that the wires near the integrated circuit wafer 300 are easily broken by pulling is avoided.

In detail, the horizontal distance D2 between the first conductive via C1 contacting the first conductive line 121 and the edge of the integrated circuit die 300 is 300 to 600 micrometers. And the second conductive via C2 contacting the second wire 122 is at a horizontal distance D3 from the edge of the integrated circuit die 300 of 300 microns to 600 microns. In other words, the horizontal distance between the end of the first conductive line 121 far from the ic die 300 and the edge of the ic die 300 is 300 to 600 microns. And the end of the second conductive line 122 away from the ic die 300 is horizontally spaced from the edge of the ic die 300 by 300-600 microns.

In order to electrically connect the first metal bump 311 of the integrated circuit chip 300 with the first conductive line 121 embedded under the organic buffer layer 131, the organic passivation layer 160, the organic gate isolation layer 132, and the organic buffer layer 131 together have the first through hole 172 exposing the exposed portion of the first conductive line 121. Thus, the first conductive trace 121 can be electrically connected to the first metal bump 311 through the first conductive pad layer 181 and the anisotropic conductive adhesive layer 410 covering the first conductive pad layer 181. Specifically, the first conductive pad layer 181 covers a portion of the organic protective layer 160, a sidewall of the first through-hole 172, and an exposed portion of the first wire 121. The anisotropic conductive adhesive layer 410 covers the first conductive pad layer 181 and fills the remaining portion of the first through hole 172.

Similarly, in order to electrically connect the second metal bump 312 of the integrated circuit chip 300 with the second conductive line 122 embedded under the organic buffer layer 131, the organic passivation layer 160, the organic gate isolation layer 132, and the organic buffer layer 131 further have the second through hole 174 exposing the exposed portion of the second conductive line 122. Thus, the second conductive trace 122 can be electrically connected to the second metal bump 312 through the second conductive pad layer 182 and the anisotropic conductive adhesive layer 410 covering the second conductive pad layer 182. Specifically, the second conductive pad layer 182 covers a portion of the organic protective layer 160, sidewalls of the second through hole 174, and an exposed portion of the second wire 122. The anisotropic conductive adhesive layer 410 covers the second conductive pad layer 182 and fills the remaining portion of the second through hole 174.

Referring to fig. 4, fig. 4 is a schematic cross-sectional view of a single sub-pixel 204 in the display area 202 of the display device 200 shown in fig. 1. As shown in fig. 4, the sub-pixel 204 includes a sub-pixel transistor and a pixel electrode 210. Specifically, the subpixel transistor includes a source/drain layer 150, a semiconductor layer 170, a photoresist layer 180, and a gate 194.

The source/drain layer 150 is disposed on the organic buffer layer 131 and has a separate source region 152 and drain region 154. The semiconductor layer 170 is disposed on a portion of the source region 152, a portion of the drain region 154, and the organic buffer layer 131 between the source region 152 and the drain region 154. The photoresist layer 180 is disposed on the semiconductor layer 170 and between the organic gate isolation layer 132 and the semiconductor layer 170. The Photoresist layer 180 includes an Organic material, which may be an Organic Photoresist (OPR) layer. The gate 194 is disposed on the organic gate isolation layer 132 and covered by the organic passivation layer 160.

The pixel electrode 210 is disposed on the organic protective layer 160. It should be noted that the third conductive line 141 in fig. 3A extends toward the display region 202 and is connected to the source/drain layer 150, such as the source region 152. In addition, the fourth conductive line 142 in fig. 3B extends toward the display region 202 and is connected to the gate 194.

Fig. 5A and 5B are schematic cross-sectional views of a circuit structure 100B along a tangent line a-a 'and a tangent line B-B' of fig. 2 according to another embodiment of the invention. In fig. 5A and 5B, the same or similar elements as those in fig. 3A and 3B are given the same reference numerals, and the description thereof is omitted. The circuit structure 100B of fig. 5A and 5B is similar to the circuit structure 100A of fig. 3A and 3B, except that the third conductive line 141 extends toward the first conductive pad layer 181 and contacts the first conductive pad layer 181, and the fourth conductive line 142 extends toward the second conductive pad layer 182 and contacts the second conductive pad layer 182 in fig. 5A and 5B. As such, compared to the circuit structure 100A, even if the first conductive line 121 of the circuit structure 100B is broken, the first metal bump 311 can still be electrically connected to the third conductive line 141. Similarly, even if the second conductive line 122 of the circuit structure 100B is broken, the second metal bump 312 can still be electrically connected to the fourth conductive line 142.

Fig. 6A is a schematic cross-sectional view of a circuit structure 100C according to another embodiment of the invention, taken along the cut lines a-a 'of fig. 2 and C-C' of fig. 1. Fig. 6B is a schematic cross-sectional view of the line structure 100C along the tangent line B-B 'of fig. 2 and the tangent line C-C' of fig. 1.

Referring to fig. 2, fig. 6A and fig. 6B, the circuit structure 100C includes a flexible substrate 110, an inorganic barrier layer 114, a first conductive line 121, a second conductive line 122, a third conductive line 123, a fourth conductive line 141, a fifth conductive line 142, an organic dielectric layer 130, an organic passivation layer 160, a first conductive via C1 and a second conductive via C2.

The inorganic barrier layer 114 is disposed on the flexible substrate 110. The first conductive line 121, the second conductive line 122, and the third conductive line 123 are disposed on the inorganic barrier layer 114 and contact the inorganic barrier layer 114. In addition, the first conductive line 121, the second conductive line 122, and the third conductive line 123 are separated from each other. It is understood that since the inorganic barrier layer 114 is not an organic material, the first conductive line 121, the second conductive line 122, and the third conductive line 123 on the inorganic barrier layer 114 have excellent adhesion to the inorganic barrier layer 114.

As shown in fig. 2, the first conductive line 121 and the second conductive line 122 are substantially parallel, and the first conductive line 121 and the second conductive line 122 have a distance D1 therebetween. The distance D1 is 4-10 μm.

As shown in fig. 6A and 6B, the first conductive trace 121 has a first conductive connection region R2a for electrically connecting to the first metal bump 311 of the integrated circuit chip 300 through the anisotropic conductive adhesive layer 410. The second conductive trace 122 has a second conductive connection region R2b for electrically connecting to the second metal bump 312 of the ic chip 300 through the anisotropic conductive adhesive layer 410. In addition, the third wire 123 has a third conductive connection region R3 and a fourth conductive connection region R4. The third conductive connection region R3 is electrically connected to the third metal bump 320 of the ic chip 300 through the anisotropic conductive adhesive layer 420. The fourth conductive connection region R4 is electrically connected to the flexible circuit board 500 through the anisotropic conductive adhesive layer 430.

Since a portion of the first conductive line 121, a portion of the second conductive line 122, and the third conductive line 123 are exposed to the outside, in some embodiments, the first conductive line 121, the second conductive line 122, and the third conductive line 123 include a corrosion-resistant metal such as titanium, nickel boride, or indium tin oxide. In some embodiments, the first lead 121, the second lead 122, and the third lead 123 may be a multi-layer structure in which the outermost layer includes a corrosion-resistant metal and covers the inner layer. In addition, the materials of the flexible substrate 110 and the inorganic barrier layer 114 are as described above and will not be described again.

As shown in fig. 6A and 6B, the organic dielectric layer 130 is disposed on the inorganic barrier layer 114, and includes an organic buffer layer 131 and an organic gate isolation layer 132. The organic gate isolation layer 132 is disposed on the organic buffer layer 131. The organic protection layer 160 is disposed on the organic gate isolation layer 132. Specifically, the fourth conductive line 141 is disposed between the organic buffer layer 131 and the organic gate isolation layer 132, and the fifth conductive line 142 is disposed on the organic gate isolation layer 132. In some embodiments, the fourth conductive line 141 is, for example, a data line, and the fifth conductive line 142 is, for example, a gate line. In some embodiments, the fourth conductive line 141 and the fifth conductive line 142 include a metal material such as aluminum, copper, nickel, or silver. It should be noted that the fourth conductive line 141 extends toward the display region 202 and is connected to the source/drain layer 150 in fig. 4, such as the source region 152. And the fifth conductive line 142 extends toward the display area 202 and is connected to the gate 194 in fig. 4.

The first conductive via C1 is disposed in the organic buffer layer 131, and two ends of the first conductive via C1 contact the first conductive line 121 and the fourth conductive line 141, respectively, so that the first conductive line 121 is electrically connected to the fourth conductive line 141. Similarly, the second conductive via C2 is disposed in the organic buffer layer 131 and the organic gate isolation layer 132, and two ends of the second conductive via C2 contact the second conductive line 122 and the fifth conductive line 142, respectively, so that the second conductive line 122 is electrically connected to the fifth conductive line 142.

Fig. 7A is a schematic cross-sectional view of a circuit structure 100D according to another embodiment of the invention, taken along the cut lines a-a 'of fig. 2 and C-C' of fig. 1. Fig. 7B is a schematic cross-sectional view of the line structure 100D along the tangent line B-B 'of fig. 2 and the tangent line C-C' of fig. 1. In fig. 7A and 7B, the same or similar elements as those in fig. 6A and 6B are given the same reference numerals, and the description thereof is omitted. The line structure 100D of fig. 7A and 7B is similar to the line structure 100C of fig. 6A and 6B, except that the line structure 100D of fig. 7A and 7B further includes a protective layer 190. The passivation layer 190 is disposed between the inorganic barrier layer 114 and the organic dielectric layer 130, and covers the first conductive line 121, the second conductive line 122, and the third conductive line 123.

In order to electrically connect the first metal bump 311 and the second metal bump 312 of the integrated circuit chip 300 with the first conductive line 121 and the second conductive line 122 embedded under the protection layer 190, the protection layer 190 has a first through hole 172 and a second through hole 174. The first through hole 172 exposes the first conductive connection region R2a of the first conductive line 121. The second through hole 174 exposes the second conductive connection region R2b of the second conductive line 122. Thus, the first conductive trace 121 can be electrically connected to the first metal bump 311 through the first conductive pad layer 181 and the anisotropic conductive adhesive layer 410 covering the first conductive pad layer 181. The second conductive trace 122 can be electrically connected to the second metal bump 312 through the second conductive pad layer 182 and the anisotropic conductive adhesive layer 410 covering the second conductive pad layer 182.

Specifically, the first conductive pad layer 181 covers a portion of the protective layer 190, a sidewall of the first through hole 172, and the first conductive connection region R2a of the first conductive line 121. The anisotropic conductive adhesive layer 410 covers the first conductive pad layer 181 and fills the remaining portion of the first through hole 172. The second conductive pad layer 182 covers a portion of the protective layer 190, sidewalls of the second through hole 174, and the second conductive connection region R2b of the second conductive line 122. The anisotropic conductive adhesive layer 410 covers the second conductive pad layer 182 and fills the remaining portion of the second through hole 174.

Similarly, in order to electrically connect the third metal bump 320 and the flexible circuit board 500 of the integrated circuit chip 300 with the third conductive wire 123 embedded under the passivation layer 190, the passivation layer 190 has a third through hole 172a and a fourth through hole 192. The third through hole 172a exposes the third conductive connection region R3 of the third conductive line 123. The fourth penetration hole 192 exposes the fourth conductive connection region R4 of the third conductive line 123. Thus, the third wire 123 can be electrically connected to the third metal bump 320 through the third conductive pad layer 181a and the anisotropic conductive adhesive layer 420 covering the third conductive pad layer 181 a. In addition, the third wire 123 can be electrically connected to the flexible circuit board 500 through the fourth conductive pad layer 181b and the anisotropic conductive adhesive layer 430 covering the fourth conductive pad layer 181 b.

Specifically, the third conductive pad layer 181a covers a portion of the protective layer 190, a sidewall of the third through hole 172a, and the third conductive connection region R3 of the third conductive line 123. The anisotropic conductive adhesive layer 420 covers the third conductive pad layer 181a and fills the remaining portion of the third through hole 172 a. The fourth conductive pad 181b covers a portion of the protective layer 190, a sidewall of the fourth through hole 192, and the fourth conductive connection region R4 of the third conductive line 123. The anisotropic conductive adhesive layer 430 covers the fourth conductive pad layer 181b and fills the remaining portion of the fourth through hole 192.

The circuit structure of the invention is also suitable for chip-on-film (COF) technology. Specifically, please refer to fig. 8A and 8B. Fig. 8A is a schematic top view of a display device 200 according to another embodiment of the invention, and fig. 8B is a schematic cross-sectional view of the circuit structure 100E along a cut line D-D' of fig. 8A. In fig. 8B, the same or similar elements as those in fig. 6A and 6B are given the same reference numerals, and the description thereof is omitted. The circuit structure 100E of fig. 8A and 8B is similar to the circuit structure 100C of fig. 6A and 6B, except that the ic chip 300 of the circuit structure 100E of fig. 8A and 8B is disposed on the flexible circuit board 500, and the first conductive wires 121 and the second conductive wires (not shown) are directly electrically connected to the flexible circuit board 500. Specifically, the first conductive trace 121 has a first conductive connection region R2a for electrically connecting with the flexible circuit board 500 through the anisotropic conductive adhesive layer 430. Similarly, the second conductive traces (not shown) have second conductive connection regions (not shown) for electrically connecting with the flexible circuit board 500 through the anisotropic conductive adhesive layer 430. Accordingly, the first conductive wires 121 and the second conductive wires (not shown) can be electrically connected to the first metal bumps 311 and the second metal bumps (not shown) of the ic chip 300 through the internal circuit of the flexible circuit board 500.

Although the present invention has been disclosed in the context of embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention, and it is intended that the scope of the invention be defined by the appended claims.

Claims

1. A wiring structure, comprising:

a flexible substrate;

an inorganic barrier layer disposed on the flexible substrate;

a first wire and a second wire disposed on the inorganic barrier layer and contacting the inorganic barrier layer, wherein the first wire and the second wire are separated from each other;

an organic dielectric layer disposed over the first conductive line and the second conductive line;

a third conductive line disposed in the organic dielectric layer;

a fourth conductive line disposed on the organic dielectric layer;

a first conductive via disposed in the organic dielectric layer and contacting the first conductive line and the third conductive line; and

a second conductive via disposed in the organic dielectric layer and contacting the second conductive line and the fourth conductive line;

the organic dielectric layer comprises an organic buffer layer and an organic grid isolation layer arranged on the organic buffer layer, the third conducting wire is arranged between the organic buffer layer and the organic grid isolation layer, and the fourth conducting wire is arranged on the organic grid isolation layer.

2. The wiring structure of claim 1, wherein said first conductor and said second conductor are substantially parallel.

3. The wiring structure of claim 2, wherein said first conductive line and said second conductive line have a distance of 4 to 10 microns therebetween.

4. The wiring structure of claim 1, wherein the organic dielectric layer has a first via exposing the exposed portion of the first conductive line and a second via exposing the exposed portion of the second conductive line.

5. The wiring structure of claim 4, further comprising:

a first conductive pad layer covering a sidewall of the first through hole and the exposed portion of the first conductive line; and

a second conductive pad layer covering sidewalls of the second through hole and the exposed portion of the second conductive line.

6. The circuit structure of claim 5, wherein said third wire contacts said first conductive pad layer and said fourth wire contacts said second conductive pad layer.

7. The wiring structure of claim 1, further comprising:

and the integrated circuit wafer is electrically connected with the first lead and the second lead, wherein the horizontal distance between the first conductive through hole and the edge of the integrated circuit wafer is 300-600 micrometers, and the horizontal distance between the second conductive through hole and the edge of the integrated circuit wafer is 300-600 micrometers.

8. The wiring structure of claim 1, wherein said first wire and said second wire comprise molybdenum, molybdenum-chromium alloy, aluminum-neodymium alloy, or titanium.

9. A wiring structure, comprising:

a flexible substrate;

an inorganic barrier layer disposed on the flexible substrate;

a first conductive line, a second conductive line, and a third conductive line disposed on the inorganic barrier layer and contacting the inorganic barrier layer, wherein the first conductive line, the second conductive line, and the third conductive line are separated from each other, the first conductive line has a first conductive connection region, the second conductive line has a second conductive connection region, and the third conductive line has a third conductive connection region and a fourth conductive connection region;

a fourth conductive line disposed in the organic dielectric layer;

a fifth conductive line disposed on the organic dielectric layer;

a first conductive via disposed in the organic dielectric layer and contacting the first conductive line and the fourth conductive line;

a second conductive via disposed in the organic dielectric layer and contacting the second conductive line and the fifth conductive line; and

and a passivation layer disposed between the inorganic barrier layer and the organic dielectric layer and covering the first wire, the second wire, and the third wire, wherein the passivation layer has a first through hole exposing the first conductive connection region of the first wire, a second through hole exposing the second conductive connection region of the second wire, a third through hole exposing the third conductive connection region of the third wire, and a fourth through hole exposing the fourth conductive connection region of the third wire.

10. The wiring structure of claim 9, wherein said first conductor and said second conductor are substantially parallel.

11. The wiring structure of claim 10, wherein said first conductive line and said second conductive line have a distance of 4 to 10 microns therebetween.

12. The wiring structure of claim 9, wherein the first, second, and third wires comprise titanium, nickel boride, or indium tin oxide.

13. The wiring structure of claim 9, further comprising:

a first conductive pad layer covering a sidewall of the first through hole and the first conductive connection region of the first conductive line;

a second conductive pad layer covering sidewalls of the second through hole and the second conductive connection region of the second conductive line;

a third conductive pad layer covering a sidewall of the third through hole and the third conductive connection region of the third conductive line; and

a fourth conductive pad covering sidewalls of the third through hole and the fourth conductive connection region of the third conductive line.