CN110867438A - Power semiconductor module substrate - Google Patents
Power semiconductor module substrate Download PDFInfo
- Publication number
- CN110867438A CN110867438A CN201910940010.6A CN201910940010A CN110867438A CN 110867438 A CN110867438 A CN 110867438A CN 201910940010 A CN201910940010 A CN 201910940010A CN 110867438 A CN110867438 A CN 110867438A
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- Prior art keywords
- power
- metallization
- semiconductor module
- module substrate
- signal terminal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
Abstract
The invention discloses a power semiconductor module substrate. The power semiconductor module substrate includes: the semiconductor device includes a first power metallization, a second power metallization, a third power metallization, a fourth power metallization, and an auxiliary metallization formed between the first power metallization and the second power metallization and between the third power metallization and the fourth power metallization, a gate signal terminal being formed on the auxiliary metallization, the auxiliary metallization extending in an arrangement direction of the transistor chips and the diode chips at least to a position facing a control electrode of the transistor chip located at an outermost edge in the arrangement direction. According to the invention, the stray inductance and the unevenness degree of the parallel chips can be reduced through reasonable arrangement of the driving loop.
Description
Technical Field
The present invention relates to a power semiconductor module substrate.
Background
In power semiconductor chips, transistor chips are commonly used. For a transistor chip with a control terminal, a schematic diagram of a driving circuit inside a power module is shown in fig. 3. Wherein Cg1, Cg2 and Cg3 respectively represent gate capacitances of three transistor chips connected in parallel, and the current capacity of the chips is determined by the voltage on the gate capacitances. Tg and Te are ports of the power semiconductor module to which an external driving circuit is connected, for receiving a driving signal. Rg0 and Lg0 are stray resistances and stray inductances, respectively, of the common part of the chip drive loop. The Rg1, the Lg1, the Rg2, the Lg2, the Rg3 and the Lg3 are respectively single stray resistance and stray inductance of three transistor chips caused by position distribution. In the process of turning on the power semiconductor module, the driving voltage applied to Tg and Te is increased from a specific negative value to a positive value, so that the voltage at two ends of a grid capacitor is increased, the current passing through a power terminal of the transistor is increased, and the transistor is turned on; during the turn-off of the power semiconductor module, the driving voltage applied to Tg and Te decreases from a specific positive value to a negative value, causing a voltage drop across the gate capacitor, causing a current through the power terminal of the transistor to drop and the transistor to turn off.
If the stray inductance value in the module driving loop is large, voltage oscillation between the stray inductance and the chip gate capacitor is easily caused in the module switching process, and if the voltage at two ends of the gate capacitor is lower than the threshold voltage for switching on the chip due to oscillation in the switching-on process, the chip is possibly switched off by mistake; if the voltage across the gate capacitor during the turn-off process is higher than the threshold voltage for turning off the chip due to oscillation, the chip may be turned on by mistake. Both of the above conditions are not conducive to reliable operation of the power semiconductor module. The grid capacitance is determined by the chip, and stray inductance of a driving loop is reduced as much as possible during design of the power module, so that the risk of mistaken turn-on and mistaken turn-off at high switching speed is reduced.
If the stray parameters of the parallel chips are inconsistent, the charging and discharging speeds of the gate capacitance are inconsistent in the switching process. Therefore, the power current passing through the chips is not uniform in the switching process, so that the loss on the chips connected in parallel is not uniform, and the temperature difference of the chips is reflected finally. Under the condition that the power module works at full power, the semiconductor element can be out of work due to over-temperature and over-current caused by uneven distribution of chip current, and the reliability and the output power of the module are influenced.
Therefore, it is becoming more and more urgent to reduce the stray inductance and the degree of unevenness of the parallel chips by a reasonable drive loop arrangement.
Disclosure of Invention
It is an object of the present invention to overcome the drawbacks of the prior art and to provide a power semiconductor module substrate that achieves a low stray inductance of the power module driving circuit and a balance of stray inductances between different chips.
In order to achieve the purpose, the invention provides the following technical scheme: a power semiconductor module substrate, comprising:
a first power metal coating on which N transistor chips and N diode chips belonging to a first bridge arm switch are arranged in parallel in two rows, N being a positive integer;
a second power metallization on which a first emitter signal terminal is formed;
a third power metal coating on which N transistor chips and N diode chips belonging to the second bridge arm switch are arranged in parallel in two rows;
a fourth power metallization on which a second emitter signal terminal is formed; and
an auxiliary metallization formed between the first power metallization and the second power metallization and between the third power metallization and the fourth power metallization, a gate signal terminal being formed on the auxiliary metallization,
the auxiliary metal coating extends in the arrangement direction of the transistor chips and the diode chips at least to a position facing the control electrode of the transistor chip located at the outermost edge in the arrangement direction.
Preferably, the distance between the diode chip and the gate signal terminal is greater than the distance between the transistor chip and the gate signal terminal.
Preferably, the power electrodes of the upper surfaces of the transistor chip and the diode chip are connected to one another and to further power metallizations by means of connecting means.
Preferably, the connecting means is a binding wire.
Preferably, the auxiliary metallization is insulated from the other power metallization.
Preferably, the first emitter signal terminal and the second emitter signal terminal are both close to the gate signal terminal.
According to the power semiconductor module substrate provided by the invention, the stray inductance and the unevenness degree of the parallel chips can be reduced through reasonable arrangement of the driving loop.
Drawings
Fig. 1 is a plan view of a power semiconductor module substrate of the present invention.
Fig. 2 is a schematic diagram of the bridge arm switch portion of fig. 1.
Fig. 3 is a schematic diagram of a prior art internal driving circuit of a power module.
Detailed Description
The technical solution of the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention.
A first embodiment of the present invention is a power semiconductor module substrate. As shown in fig. 1, the power semiconductor module substrate includes: a first power metallization, a second power metallization, a third power metallization, a fourth power metallization, and an auxiliary metallization.
Because the current capacity of a single power semiconductor chip is limited, in order to expand the power processing capacity of the power semiconductor module, the bridge arm switch is formed in the high-capacity power semiconductor module in a multi-chip parallel connection mode.
As shown in fig. 2, in each bridge arm switch, in order to realize bidirectional flow of current or reduce loss, a transistor chip whose switching state can be controlled by a control electrode and a diode chip with unidirectional conduction capability are generally used as chips connected in parallel. The transistor chip and the diode chip are connected in parallel at their power electrodes. In fig. 1 and 2, three transistor chips and three diode chips are shown within each bridge arm switch. However, the present invention is not limited to this, and other numbers of transistor chips and diode chips may be used.
Semiconductor chips belonging to the same bridge arm switch are arranged on the first power metallization, so that a first power potential region is formed on the first power metallization, and the three transistor chips and the three diode chips belonging to the first bridge arm switch are arranged in parallel in two rows in the manner shown in the drawing. The array of transistor chips is proximate to the gate control terminal on the auxiliary metallization, and the array of diode chips is distal from the gate control terminal. Although the distance between the diode chip and the gate signal terminal is greater than the distance between the transistor chip and the gate signal terminal in the present invention, the present invention is not limited to this, and other suitable arrangements may be adopted.
The transistor and diode upper surfaces are connected to each other and to other power metallizations (second and third power metallizations) by connecting means. The connecting means may be, for example, a binding wire, but is not limited thereto, and may be other various connecting members. The second metallization layer, the third metallization layer, the first metallization layer and the second metallization layer are insulated from each other, and the chip upper surface power electrode, the connection means, the second metallization layer and the third metallization layer form a second power potential area.
Semiconductor chips belonging to the same bridge arm switch are arranged on the third power metal coating, and three transistor chips and three diode chips belonging to the second bridge arm switch are arranged in two rows in parallel according to the mode shown in the figure.
The gate control terminal of the power module is arranged on an auxiliary metallization which is insulated from the remaining power metallization to form an auxiliary potential area.
The auxiliary metal coating extends along the arrangement direction of a row of chips close to the signal terminals, namely the arrangement direction (horizontal direction in fig. 1) of the transistor chips and the diode chips, at the edge of the chip, at least to the position (facing position) with the shortest distance to the control electrode of the chip, and the positions of the falling points of the control electrode connecting devices are all at the facing position. As shown in fig. 1, an auxiliary metallization layer is formed between the first power metallization layer and the second power metallization layer, and an auxiliary metallization layer is also formed between the third power metallization layer and the fourth power metallization layer.
The first emitter signal terminal of the power module is located on the second power metallization as close as possible to the gate signal terminal. The second emitter signal terminal of the power module is located on the fourth power metallization layer as close as possible to the gate signal terminal.
As described above, with the power semiconductor module substrate according to the first embodiment, since the auxiliary metal coating where the gate control terminal is located extends along the arrangement direction of the transistor chip array and at least extends to the position where the distance to the control electrode of the transistor chip is shortest, that is, the auxiliary metal coating has a balanced gate path, stray inductance of the internal drive circuit of the power semiconductor module can be reduced, and unbalanced degree of the stray parameters of the drive circuits of the power semiconductor chips connected in parallel can be reduced, so that the risk of false triggering of the power semiconductor module during high-speed switching is reduced, and the operational reliability of the module is improved.
It should be noted that, each unit mentioned in each device embodiment of the present invention is a logical unit, and physically, one logical unit may be one physical unit, or may be a part of one physical unit, or may be implemented by a combination of multiple physical units, and the physical implementation manner of these logical units itself is not the most important, and the combination of the functions implemented by these logical units is the key to solve the technical problem provided by the present invention. Furthermore, the above-mentioned embodiments of the apparatus of the present invention do not introduce elements that are less relevant for solving the technical problems of the present invention in order to highlight the innovative part of the present invention, which does not indicate that there are no other elements in the above-mentioned embodiments of the apparatus.
It is to be noted that in the claims and the description of the present patent, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims (7)
1. A power semiconductor module substrate, comprising:
a first power metal coating on which N transistor chips and N diode chips belonging to a first bridge arm switch are arranged in parallel in two rows, N being a positive integer;
a second power metallization on which a first emitter signal terminal is formed;
a third power metal coating on which N transistor chips and N diode chips belonging to the second bridge arm switch are arranged in parallel in two rows;
a fourth power metallization on which a second emitter signal terminal is formed; and
an auxiliary metallization formed between the first power metallization and the second power metallization and between the third power metallization and the fourth power metallization, a gate signal terminal being formed on the auxiliary metallization,
the auxiliary metal coating extends in the arrangement direction of the transistor chips and the diode chips at least to a position facing the control electrode of the transistor chip located at the outermost edge in the arrangement direction.
2. The power semiconductor module substrate of claim 1,
the distance between the diode chip and the grid signal terminal is larger than the distance between the transistor chip and the grid signal terminal.
3. The power semiconductor module substrate of claim 1,
the power electrodes on the upper surfaces of the transistor chip and the diode chip are connected to one another and to further power metals by means of connecting devices.
4. A power semiconductor module substrate according to claim 3, characterized in that the connection means are binding wires.
5. The power semiconductor module substrate of claim 1, wherein the auxiliary metallization layer is insulated from other power metallization layers.
6. The power semiconductor module substrate of claim 1, wherein the first emitter signal terminal and the second emitter signal terminal are both proximate to the gate signal terminal.
7. The power semiconductor module substrate of claim 1, wherein N is 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910940010.6A CN110867438A (en) | 2019-09-30 | 2019-09-30 | Power semiconductor module substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910940010.6A CN110867438A (en) | 2019-09-30 | 2019-09-30 | Power semiconductor module substrate |
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| CN110867438A true CN110867438A (en) | 2020-03-06 |
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| CN201910940010.6A Pending CN110867438A (en) | 2019-09-30 | 2019-09-30 | Power semiconductor module substrate |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111627899A (en) * | 2020-06-03 | 2020-09-04 | 成都森未科技有限公司 | Integrated IGBT packaging structure based on DBC layout |
| CN111682021A (en) * | 2020-06-17 | 2020-09-18 | 上海临港电力电子研究有限公司 | Power semiconductor module substrate and power semiconductor device using the same |
| CN112466819A (en) * | 2020-11-24 | 2021-03-09 | 浙江大学 | Power semiconductor module with auxiliary insulating substrate and manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102906874A (en) * | 2010-05-21 | 2013-01-30 | 三菱电机株式会社 | Power semiconductor module |
| CN107342313A (en) * | 2017-08-15 | 2017-11-10 | 杭州浙阳电气有限公司 | The spuious balanced substrate of gate pole and its power semiconductor modular |
| CN108447846A (en) * | 2018-06-06 | 2018-08-24 | 臻驱科技（上海）有限公司 | A kind of power semiconductor modular substrate and power semiconductor modular |
| CN108447847A (en) * | 2018-06-06 | 2018-08-24 | 臻驱科技（上海）有限公司 | A kind of power semiconductor modular substrate and power semiconductor modular |
-
2019
- 2019-09-30 CN CN201910940010.6A patent/CN110867438A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102906874A (en) * | 2010-05-21 | 2013-01-30 | 三菱电机株式会社 | Power semiconductor module |
| CN107342313A (en) * | 2017-08-15 | 2017-11-10 | 杭州浙阳电气有限公司 | The spuious balanced substrate of gate pole and its power semiconductor modular |
| CN108447846A (en) * | 2018-06-06 | 2018-08-24 | 臻驱科技（上海）有限公司 | A kind of power semiconductor modular substrate and power semiconductor modular |
| CN108447847A (en) * | 2018-06-06 | 2018-08-24 | 臻驱科技（上海）有限公司 | A kind of power semiconductor modular substrate and power semiconductor modular |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111627899A (en) * | 2020-06-03 | 2020-09-04 | 成都森未科技有限公司 | Integrated IGBT packaging structure based on DBC layout |
| CN111682021A (en) * | 2020-06-17 | 2020-09-18 | 上海临港电力电子研究有限公司 | Power semiconductor module substrate and power semiconductor device using the same |
| CN111682021B (en) * | 2020-06-17 | 2024-06-04 | 上海临港电力电子研究有限公司 | Power semiconductor module substrate and power semiconductor device using same |
| CN112466819A (en) * | 2020-11-24 | 2021-03-09 | 浙江大学 | Power semiconductor module with auxiliary insulating substrate and manufacturing method |
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Application publication date: 20200306 |