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CN110867387A - Bonding structure and manufacturing method thereof - Google Patents

Bonding structure and manufacturing method thereof Download PDF

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Publication number
CN110867387A
CN110867387A CN201911185772.6A CN201911185772A CN110867387A CN 110867387 A CN110867387 A CN 110867387A CN 201911185772 A CN201911185772 A CN 201911185772A CN 110867387 A CN110867387 A CN 110867387A
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CN
China
Prior art keywords
chip
bonded
wafer
cushion layer
packaging cushion
Prior art date
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Pending
Application number
CN201911185772.6A
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Chinese (zh)
Inventor
李乔伟
梁斐
胡胜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Wuhan Xinxin Semiconductor Manufacturing Corp
Original Assignee
Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Publication date
Application filed by Wuhan Xinxin Semiconductor Manufacturing Co Ltd filed Critical Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority to CN201911185772.6A priority Critical patent/CN110867387A/en
Publication of CN110867387A publication Critical patent/CN110867387A/en
Pending legal-status Critical Current

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Abstract

The embodiment of the application provides a bonding structure and a manufacturing method thereof, wherein an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure are formed in a chip to be bonded, the packaging cushion layer is exposed at the side edge of the chip to be bonded, bare chips arranged in an array are formed on a wafer to be bonded, and when the interconnection structure and the packaging cushion layer electrically connected with the interconnection structure are formed on the surface of the bare chip, the packaging cushion layer in the chip to be bonded is utilized to bond the chip to be bonded to the packaging cushion layer on the surface of the bare chip from the side edge so as to obtain a wafer structure. The method utilizes the packaging cushion layer to bond the chip to be bonded and the bare chip on the wafer to be bonded to form a wafer structure, the chip to be bonded can select products without defects, and compared with the bonding of the wafer and the wafer, the bonding between the chips with the defects on the wafer is avoided, the yield of the products is improved, and the manufacturing cost is further reduced.

Description

Bonding structure and manufacturing method thereof
Technical Field
The present invention relates to semiconductor devices and manufacturing methods thereof, and more particularly, to a bonding structure and a manufacturing method thereof.
Background
With the continuous development of semiconductor technology, 3D-IC (three-dimensional integrated circuit) technology is widely used, which utilizes wafer level packaging technology to bond wafers with different functions together in a stacked manner, and has the advantages of high performance, low cost and high integration. As the functional and performance requirements of integrated circuits are higher and higher, higher requirements are put forward on the bonding process, and the existing wafer level package cannot meet the requirements of high yield and low cost.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a bonding structure and a method for manufacturing the same, which can improve the yield of products and reduce the manufacturing cost.
In order to achieve the purpose, the technical scheme is as follows:
the embodiment of the application provides a manufacturing method of a bonding structure, which comprises the following steps:
providing a chip to be bonded, wherein an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure are formed in the chip to be bonded, and the packaging cushion layer is exposed at the side edge of the chip to be bonded;
providing a wafer to be bonded, wherein bare chips arranged in an array are formed on the wafer to be bonded, and an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure are formed on the surface of each bare chip;
and bonding the chip to be bonded to the packaging cushion layer on the surface of the bare chip from the side edge by using the packaging cushion layer of the chip to be bonded so as to obtain a wafer structure.
Optionally, the chip to be bonded is a chip stack, and the chip stack includes a plurality of chips bonded in sequence.
Optionally, the chip to be bonded passes a wafer level test; the forming method of the chip stack comprises the following steps:
sequentially bonding the wafers respectively provided with the chips to be bonded to form a wafer stack;
performing a wafer level test of the wafer stack;
and cutting the wafer stack, and exposing the packaging cushion layer at the side edge of the chip to be bonded so as to obtain the chip stack.
Optionally, the number of the chips to be bonded is multiple.
Optionally, the chip to be bonded is a single-layer chip, and the chip passes a wafer-level test.
Optionally, the method further includes: cutting the wafer structure to obtain an independent chip structure;
and packaging the chip structure.
Optionally, a lead-out pad is further formed on the die; before packaging, the method further comprises the following steps:
lead-out lines are formed from the lead-out pads.
An embodiment of the present application provides a bonding structure, including:
the chip to be bonded is provided with an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure, and the packaging cushion layer is exposed at the side edge of the chip to be bonded;
the wafer to be bonded is provided with bare chips arranged in an array, and the surface of each bare chip is provided with an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure;
wherein the packaging cushion layer of the side edge of the chip to be bonded is bonded to the packaging cushion layer of the surface of the bare chip.
Optionally, the chip to be bonded is a chip stack formed by a single layer or bonding, and the chip to be bonded passes a wafer level test.
An embodiment of the present application provides a bonding structure, including:
the chip to be bonded is provided with an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure, and the packaging cushion layer is exposed at the side edge of the chip to be bonded;
the die comprises a die, wherein an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure are formed on the surface of the die, and the packaging cushion layer of the side edge of the chip to be bonded is bonded to the packaging cushion layer of the surface of the die.
The embodiment of the application provides a bonding structure and a manufacturing method thereof, wherein an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure are formed in a chip to be bonded, the packaging cushion layer is exposed at the side edge of the chip to be bonded, bare chips arranged in an array are formed on a wafer to be bonded, the interconnection structure and the packaging cushion layer electrically connected with the interconnection structure are formed on the surface of the bare chip, and the chip to be bonded is bonded to the packaging cushion layer on the surface of the bare chip from the side edge by using the packaging cushion layer in the chip to be bonded so as to obtain a wafer structure. The method utilizes the packaging cushion layer to bond the chip to be bonded and the bare chip on the wafer to be bonded to form a wafer structure, the chip to be bonded can select products without defects, and compared with the bonding of the wafer and the wafer, the bonding between the chips with the defects on the wafer is avoided, the yield of the products is improved, and the manufacturing cost is further reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart illustrating a method for manufacturing a bonding structure according to an embodiment of the present disclosure;
FIG. 2 illustrates a top view of a wafer structure in an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of a wafer structure in an embodiment of the present application;
FIG. 4 is a schematic diagram of a wafer stack in an embodiment of the present application;
FIG. 5 is a schematic view of another wafer stack in an embodiment of the present application;
fig. 6 is a schematic diagram illustrating a chip stack provided by an embodiment of the present application;
FIG. 7 is a schematic diagram illustrating another chip stack provided by an embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of a wafer structure in an embodiment of the present application;
FIG. 9 is a schematic cross-sectional view of a bonding structure provided in an embodiment of the present application;
fig. 10 is a schematic cross-sectional view illustrating a bonding structure according to an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
Next, the present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present invention, and the drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background art, as the functional and performance requirements of integrated circuits are higher and higher, higher requirements are put on the bonding process, and the existing wafer level packaging technology has been unable to meet the requirements of high yield and low cost.
Based on this, the embodiments of the present application provide a bonding structure and a manufacturing method thereof, in which an interconnect structure and a package pad layer electrically connected to the interconnect structure are formed in a chip to be bonded, the package pad layer is exposed at a side edge of the chip to be bonded, dies arranged in an array are formed on a wafer to be bonded, the interconnect structure and the package pad layer electrically connected to the interconnect structure are formed on a surface of the die, and then the chip to be bonded is bonded to the package pad layer on the surface of the die from the side edge by using the package pad layer of the chip to be bonded, so that the chip to be bonded and the die on the wafer to be bonded are bonded together through the package pad layer in the chip to be bonded and the package pad layer on the surface of the die on the wafer to form a wafer structure, the chip to be bonded can select a product without defects, and compared with the bonding between the chips with the wafer, the yield of the product is improved, and the manufacturing cost is further reduced.
For better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail with reference to the accompanying drawings.
Referring to fig. 1, a flow chart of a method for manufacturing a bonding structure according to an embodiment of the present application is provided, where the method may include the following steps:
s01, providing a chip to be bonded 2100, wherein an interconnect structure and package pad layers 111 and 211 electrically connected to the interconnect structure are formed in the chip to be bonded 2100, and the package pad layers 111 and 211 are exposed to side edges of the chip to be bonded 2100, as shown in fig. 7.
In this embodiment, the chip 2100 to be bonded may be a single chip layer or a chip stack, where the chip stack may be a stack formed by two or more chips, each chip in the chip 2100 to be bonded may include a device structure (not shown), the device structure may include a MOS field effect transistor device, a memory device and/or other passive devices, the memory device may include a nonvolatile memory, a random access memory, or the like, the nonvolatile memory may include a floating gate field effect transistor such as a NOR flash memory or a NAND flash memory, or a ferroelectric memory, a phase change memory, or the like, the device structure may be a planar device or a stereoscopic device, and the stereoscopic device may include a FIN-FET (FIN field effect transistor), a three-dimensional memory, or the like.
Each layer of chips in the chips to be bonded may further include an interconnection structure (not shown) electrically connected to the device structure, and a package pad layer electrically connected to the interconnection structure, so that the package pad layer is interconnected to the device structure in the chips to be bonded, and the package pad layer may be used as an electrical connection layer for electrically connecting other chips, and may also be used for electrically connecting chips on other wafers, so as to electrically connect the device structures between the chips. The package pad layer is made of a conductive material, typically a metal material, such as copper. The package pad layer may be, for example, a metal wire or a metal pad.
Referring to fig. 7, the encapsulating pad layers 111 and 211 may be exposed to the side edges of the chip to be bonded 2100, for example, the encapsulating pad layers 111 and 211 may be formed at the left side edge of the chip to be bonded 2100 or in the chip to be bonded 2100, and then the side edges of the chip to be bonded 2100 are ground so that the encapsulating pad layers 111 and 211 are exposed to the side edges of the chip to be bonded 2100.
In this embodiment, the to-be-bonded chips 2100 may be single-layer chips that have passed through a wafer-level test, or may be chip stacks that have passed through wafer-level chips, the to-be-bonded chips 2100 may be one or more, a plurality of to-be-bonded chips 2100 may be the same single-layer chips or different single-layer chips, may be the same chip stacks or different chip stacks, or may be a combination of a single-layer chip and a chip stack, the number of the single-layer chip and the chip stack in the combination may be one or more, the number may be the same or different, and a plurality of to-be-bonded chips 2100 may have passed through a wafer-level test. Therefore, the bonding of chips with different functions and structures can be realized, and the design flexibility is better.
In this embodiment, the forming of the chip stack may include, in step S101, sequentially bonding wafers on which chips to be bonded are respectively formed to form a wafer stack 1100, which is shown in fig. 5.
In one embodiment, the number of the wafers may be two or more, each wafer has already completed a device manufacturing process, for example, a plurality of chips arranged in an array have been formed on the wafer, device structures have been formed in the chips, the device structures in the chips on different wafers may be the same or different, for example, different types of devices or the same type of devices having voltages that do not require operation may be used, and the device structures in the chips on the same wafer may be the same or different.
The chips on the wafer may have formed therein an interconnect structure electrically connected to the device structure and a package pad layer electrically connected to the interconnect structure, where package pads in different chips on the same wafer may be disposed on the same side of the chip, for example, the package pad layers may be disposed on the right side edge of the chip, and the package pad layers in different chips may also be disposed in edge regions in different directions, for example, the package pad layer in one of the chips in the wafer may be disposed in the left side edge region of the chip, and the package pad layers in other chips of the wafer may be disposed in the right side edge regions of the other chips, and the package pad layers in the chips on different wafers may be disposed on the same side of the chip or may be disposed in different regions of the chip.
Each wafer may have a first surface and an opposite second surface, where the second surface is a surface of a substrate, the substrate may be a semiconductor substrate, and specifically, may be a bulk substrate or a laminated substrate including a semiconductor material, such as a Si substrate, a Ge substrate, a SiGe substrate, or an SOI (Silicon-On-Insulator, Silicon On Insulator), and a plurality of chips arranged in an array are formed On the first surface of the substrate to form the first surface of the wafer.
In this embodiment, referring to fig. 2, fig. 2 is a schematic top view of a wafer structure, a plurality of chips 110 arranged in an array are formed on a wafer 100, the chips 110 include package pads 111 electrically connected to an interconnect structure, and referring to fig. 3, fig. 3 is a schematic cross-sectional view of the wafer structure provided in the embodiment of the present application, the wafer 100 has a first surface and a second surface, the first surface is formed with the plurality of chips 110 arranged in an array, and the second surface is a surface opposite to the first surface. Referring to fig. 4, a cross-sectional view of a wafer stack according to an embodiment of the present disclosure is shown, the wafer stack includes a first wafer 100 and a second wafer 200. The first wafer 100 includes a plurality of first chips 110, and the first chips 110 include package pads 111 electrically connected to the interconnect structure; the second wafer 200 includes a plurality of second chips 210 thereon, and the second chips 210 include package pad layers 211 electrically connected to the interconnect structures. The first surface of the first wafer 100 and the first surface of the second wafer 200 are bonded together, and in one embodiment, the first surface of the first wafer 100 and the second surface of the second wafer 200 may be bonded together.
In this embodiment, the bonding layer 120 on the surface of the wafer may be used to bond the first wafer 100 and the second wafer 200 together, the bonding may be achieved by an intermolecular chemical bonding technique of the bonding layer 120, the material of the bonding layer 120 may be silicon oxide, silicon nitride, or a stack thereof, the bonding layer 120 may be obtained after bonding layer bonds are formed on the first wafer 100 and the second wafer 200, and the wafers may be bonded together by a bonding apparatus.
It can be understood that when a plurality of wafers are stacked, the second surface of the uppermost wafer and the second surface of the lowermost wafer in the finally formed wafer stack can be made to face outwards, and in this structure, the first surface of each wafer is protected without performing an additional protection process on the first surface, thereby simplifying the process flow.
In this embodiment, before or after bonding the first wafer 100 and the second wafer 200, the first wafer 100 and the second wafer 200 may be thinned from the second surface, so as to reduce redundant components and reduce the device volume, specifically, after bonding, the second surface of the wafer facing outward may be thinned before or after bonding, for example, the first surface of the first wafer 100 and the second surface of the second wafer 200 may be opposite to each other, and after bonding through the bonding layer 120, the second surfaces of the first wafer 100 and the second wafer 200 may be thinned, respectively, as shown in fig. 5; accordingly, the wafer with the first surface facing outward after bonding may have the second surface thinned before bonding, for example, the wafer with the second surface covered with the bonding layer may be thinned from the second surface first and then covered with the bonding layer.
In this embodiment, the second surface of the wafer may be thinned by etching with an acid method, or thinned by chemical mechanical polishing, or etched from the second surface of the wafer by etching with an acid method to etch a part of the substrate material in the wafer, and then planarized by chemical mechanical polishing to realize thinning of the wafer.
In S102, a wafer level test of the wafer stack 1100 is performed.
After the wafer stack 1100 is obtained, a wafer level test is performed on the formed wafer stack 1100, during the process of forming the wafer stack 1100, the chips may have the problems of scratching and chipping, and if the chips with defects enter the subsequent bonding process, the bonded product is a poor product. Wafer level testing of the wafer stack 1100 may eliminate defective chips, including scratches, defects, etc. caused during stacking, as well as defects of the chips themselves, such as bridges, bumps, or voids, etc. generated during chip manufacturing. Before bonding, the formed wafer stack 1100 is subjected to wafer level testing, so that the defect chips are effectively prevented from entering the subsequent bonding process, and the yield of bonded products is improved. It should be noted that performance testing of chips on a wafer may also be performed before stacking the wafer 1100, thereby eliminating bad chips on the wafer, reducing bonding cost, and improving product yield.
In S103, the wafer stack 1100 is diced, and the package pad layers 111 and 211 at the side edges of the chip to be bonded 2100 are exposed, so as to obtain a chip stack, as shown in fig. 7.
In this embodiment, the wafer stack 1100 may be cut to obtain a chip stack, the package pads 111 and 211 are used to electrically connect to other chips, the package pads 111 and 211 may be formed on the side edge of the chip 2100 to be bonded, after the wafer stack 1100 is cut, the package pads 111 and 211 of the chip 2100 to be bonded are directly exposed to obtain a plurality of chip stacks, the package pads 111 and 211 may also be formed in the chip 2100 to be bonded, after the wafer is cut, the package pads 111 and 211 are not exposed, as shown in fig. 6, the side surface of the chip stack may be polished to expose the package pads 111 and 211 on the side edge of the chip 2100 to be bonded, as shown in fig. 7, the polishing may be acid etching or chemical mechanical polishing, or may be first acid etching and then chemical mechanical polishing.
Referring to fig. 7, a to-be-bonded chip 2100 according to an embodiment of the present disclosure is schematically illustrated, the to-be-bonded chip 2100 may be a chip stack, where one to-be-bonded chip 2100 includes a plurality of vertically interconnected chips, and may include a first chip 110 in a first wafer 100 and a second chip 210 in a second wafer 200. It is understood that the chips may belong to different wafers, respectively, and the number of chips in each chip stack is the same as the number of wafers in the wafer stack 1100.
In step S02, a wafer 500 to be bonded is provided, the wafer 500 to be bonded has dies 510 formed thereon in an array arrangement, and the dies 510 have interconnect structures and package pads 511 electrically connected to the interconnect structures formed on the surface thereof, as shown in fig. 8.
In the embodiment of the present application, the die (die)510 on the wafer 500 to be bonded may include a device structure (not shown), the device structure may include a MOS field effect transistor device, a memory device, and/or other passive devices, the memory device may include a non-volatile memory, such as a floating gate field effect transistor, such as a NOR flash memory, a NAND flash memory, or a ferroelectric memory, a phase change memory, or the like, the device structure may be a planar device or a stereoscopic device, and the stereoscopic device may be a FIN-FET (FIN field effect transistor), a three-dimensional memory, or the like.
An interconnect structure (not shown) electrically connected to the device structure and a package pad layer 511 electrically connected to the interconnect structure may be formed on the surface of the die 510 to be bonded, so that the package pad layer 511 is interconnected with the device structure in the die 510, and the package pad layer 511 on the surface of the die 510 to be bonded may be used as an electrical connection layer for electrically connecting other chips, and may also be used for electrically connecting chips on other wafers to electrically connect device structures between chips. The pad layer 511 is a conductive material, typically a metal material, such as copper. The package pad layer 511 may be a metal wire or a metal pad, for example.
The package pad layers 511 may be formed at the side edges of the dies 510 to be bonded, or at the middle region of the surfaces of the dies 510 to be bonded, and the package pad layers 511 in a row of dies 510 on the wafer 500 to be bonded may be located at the same side of the surfaces of the dies 510, for example, the package pad layers 511 in the dies 510 are all located at the right edge of the dies 510, although the package pad layers 511 on different surfaces of the dies 510 may also be located at different positions, for example, the package pad layer 511 on one surface of the die 510 is located at the left edge of the die 510, and the package pad layers 511 on other surfaces of the dies 510 are located at the middle region or the right edge of the surfaces of the other dies 510.
In step S03, the die 2100 to be bonded is bonded from the side edge to the pad layer 511 on the surface of the die 510 by using the pad layers 111 and 211 of the die to be bonded, so as to obtain a wafer structure, as shown in fig. 9, where fig. 9 is a schematic cross-sectional view of the bonding structure.
In the embodiment of the present application, a single layer of chips that have passed a wafer level test may be bonded to the package pad 511 on the surface of the die 510 on the wafer 500 to be bonded by using the package pads 111 and 211 in the chip 2100 to be bonded, a plurality of chips that have passed a wafer level test may be bonded to the package pad 511 on the surface of the die 510 on the wafer 500 to be bonded, respectively, or a plurality of chips that have passed a test and are sequentially bonded may be stacked and bonded to the package pad 511 on the surface of the die 510 arranged in an array on the wafer 500 to be bonded, so as to form a three-dimensional wafer bonding structure.
In this embodiment, the package pad layers 111 and 211 in the chip to be bonded 2100 and the package pad layer 511 on the surface of the die 510 on the wafer 500 to be bonded may be connected by direct soldering, for example, by forming solder balls or solder pads on the package pad layers 111 and 211 in the chip to be bonded 2100 and the package pad layer 511 on the surface of the die 510 on the wafer 500 to be bonded to achieve electrical connection therebetween, and the package pad layers 111 and 211 in the chip to be bonded 2100 and the package pad layer 511 on the surface of the die 510 on the wafer 500 to be bonded may also be connected by electrical wires, for example, electrical wires may be soldered to the package pad layers 111 and 211 in the chip to be bonded 2100 and the package pad layer 511 on the surface of the die 510 on the wafer 500 to be bonded; the package pad layers 111 and 211 in the chip to be bonded 2100 and the package pad layer 511 on the surface of the die 510 on the wafer 500 to be bonded can be electrically connected by a hybrid bonding technology.
In the embodiment of the application, before bonding, wafer-level testing is performed on the chip 2100 to be bonded to eliminate a defective chip, so that bonding between the defective chips on the wafer is avoided, and the wafer structure formed after bonding has high yield and low manufacturing cost.
After the wafer structure is formed, a cutting process may be performed on the wafer structure, for example, physical cutting or laser cutting may be employed to obtain an independent chip structure, and then the chip structure may be packaged to form a three-dimensional integrated product of different or the same kind of chips.
In this embodiment, referring to fig. 9, a lead pad 512 may be further formed on the die 510, where the lead pad 512 may be electrically connected to the package pad layers 111 and 211 in the chip 2100 to be bonded for electrical connection between the chips, and may also be electrically connected to an interconnect structure of a device structure in the die 510 for device lead-out, and the lead pad 512 is a conductive material, for example, an aluminum material.
To this end, a bonding structure of a chip bonded to a wafer is formed, as shown in fig. 9, by bonding package pad layers 111 and 211 of side edges of the chip to be bonded and package pad layers of a die surface of the wafer to be bonded.
Thereafter, the cutting of the bonded structure may be performed to obtain individual chip structures. Before the bonded structure is cut, a lead 513 may be formed from the lead pad 512, and the passivation layer 515 is covered on the bonded structure, where the lead 513 may lead out a device structure connected to the lead pad 512, the lead 513 may also lead out a device structure of the die-bonded chip 2100 to be bonded, and the lead 513 is a conductive material, and may be an aluminum material, for example; the passivation layer 515 may be, for example, silicon oxide, which is used to protect the formed device structure. During dicing, dicing may be performed along the dicing streets of the wafer to be bonded, so as to separate the wafer structure into individual chip structures, as shown in fig. 10, and thus, individual bonding structures are obtained. Thereafter, the chip structure obtained after dicing may be further packaged, for example, by plastic packaging or the like.
The above describes in detail a method for manufacturing a package structure according to an embodiment of the present application, and accordingly, the embodiment of the present application further provides a bonding structure, which is shown with reference to fig. 9 and includes:
a chip to be bonded 2100, wherein an interconnection structure and package pad layers 111 and 211 electrically connected with the interconnection structure are formed in the chip to be bonded 2100, and the package pad layers 111 and 211 are exposed to side edges of the chip to be bonded 2100;
a wafer 500 to be bonded, wherein a bare chip 510 arranged in an array is formed on the wafer 500 to be bonded, and an interconnection structure and a package pad layer 511 electrically connected with the interconnection structure are formed on the surface of the bare chip 510;
wherein the package pad layers 111, 211 at the side edges of the chip 2100 to be bonded are bonded to the package pad layer 511 at the surface of the die 510.
In the embodiment of the present application, the package pad layers 111 and 211 in the chip to be bonded 2100 are electrically connected to the package pad layer 511 on the surface of the die 510 on the wafer 500 to be bonded, so as to form a wafer structure. Taking the to-be-bonded chip 2100 as the chip stack 2100 for example, the package pad layer 111 of the first chip 110 in the chip stack 2100 is electrically connected to the package pad layer 511 on the surface of the corresponding die 510 on the to-be-bonded wafer 500, and the package pad layer 211 of the second chip 210 in the chip stack 2100 is electrically connected to the package pad layer 511 on the surface of the corresponding die 510 on the to-be-bonded wafer 500.
In this embodiment, the package pad layers 111, 211 in the chip stack 2100 may be located on the same side, such that the package pad layer 511 on the surface of the die 510 may be directly connected to the package pad layers 111, 211 in the chip stack 2100 through solder balls or intermolecular chemical bonding; the package pad layers 111, 211 in the chip stack 2100 may also be on different sides, and the package pad layer 511 on the surface of the die 510 may be electrically connected to the package pad layers 111, 211 in the chip stack 2100.
An embodiment of the present application provides another bonding structure, which is shown in fig. 10 and includes:
the chip to be bonded 2100 comprises an interconnection structure and packaging cushion layers 111 and 211 electrically connected with the interconnection structure, wherein the packaging cushion layers 111 and 211 are formed in the chip to be bonded 2100, and the packaging cushion layers 111 and 211 are exposed at the side edge of the chip to be bonded 2100;
the die 510, the die 510 having an interconnect structure and a package pad layer 511 electrically connected to the interconnect structure formed on a surface thereof, wherein the package pad layers 111 and 211 of the side edge of the chip 2100 to be bonded are bonded to the package pad layer 511 of the surface of the die 510.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the structural embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and for the relevant points, refer to the partial description of the method embodiment.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (10)

1. A method of manufacturing a bonded structure, comprising:
providing a chip to be bonded, wherein an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure are formed in the chip to be bonded, and the packaging cushion layer is exposed at the side edge of the chip to be bonded;
providing a wafer to be bonded, wherein bare chips arranged in an array are formed on the wafer to be bonded, and an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure are formed on the surface of each bare chip;
and bonding the chip to be bonded to the packaging cushion layer on the surface of the bare chip from the side edge by using the packaging cushion layer of the chip to be bonded so as to obtain a wafer structure.
2. The manufacturing method according to claim 1, wherein the chip to be bonded is a chip stack including a plurality of sequentially bonded chips.
3. The manufacturing method according to claim 2, wherein the chip to be bonded passes a wafer level test; the forming method of the chip stack comprises the following steps:
sequentially bonding the wafers respectively provided with the chips to be bonded to form a wafer stack;
performing a wafer level test of the wafer stack;
and cutting the wafer stack, and exposing the packaging cushion layer at the side edge of the chip to be bonded so as to obtain the chip stack.
4. The manufacturing method according to claim 1, wherein the chip to be bonded is plural.
5. The manufacturing method according to claim 1, wherein the chip to be bonded is a single-layer chip, and the chip passes a wafer-level test.
6. The manufacturing method according to any one of claims 1 to 5, further comprising: cutting the wafer structure to obtain an independent chip structure;
and packaging the chip structure.
7. The manufacturing method according to claim 6, wherein a lead-out pad is further formed on the die; before packaging, the method further comprises the following steps:
lead-out lines are formed from the lead-out pads.
8. A bonding structure, comprising:
the chip to be bonded is provided with an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure, and the packaging cushion layer is exposed at the side edge of the chip to be bonded;
the wafer to be bonded is provided with bare chips arranged in an array, and the surface of each bare chip is provided with an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure;
wherein the packaging cushion layer of the side edge of the chip to be bonded is bonded to the packaging cushion layer of the surface of the bare chip.
9. The bonding structure of claim 8, wherein the chip to be bonded is a single layer or a chip stack formed by bonding, and the chip to be bonded passes wafer level testing.
10. A bonding structure, comprising:
the chip to be bonded is provided with an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure, and the packaging cushion layer is exposed at the side edge of the chip to be bonded;
the die comprises a die, wherein an interconnection structure and a packaging cushion layer electrically connected with the interconnection structure are formed on the surface of the die, and the packaging cushion layer of the side edge of the chip to be bonded is bonded to the packaging cushion layer of the surface of the die.
CN201911185772.6A 2019-11-27 2019-11-27 Bonding structure and manufacturing method thereof Pending CN110867387A (en)

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