CN110854137A - Display panel, array substrate and manufacturing method thereof - Google Patents
Display panel, array substrate and manufacturing method thereof Download PDFInfo
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- CN110854137A CN110854137A CN201911154222.8A CN201911154222A CN110854137A CN 110854137 A CN110854137 A CN 110854137A CN 201911154222 A CN201911154222 A CN 201911154222A CN 110854137 A CN110854137 A CN 110854137A
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- 239000000758 substrate Substances 0.000 title claims abstract description 155
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000010409 thin film Substances 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 28
- 239000011810 insulating material Substances 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 14
- 229910044991 metal oxide Inorganic materials 0.000 claims description 10
- 150000004706 metal oxides Chemical class 0.000 claims description 10
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
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- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The disclosure relates to a display panel, an array substrate and a manufacturing method thereof, and relates to the technical field of display. The array substrate of the present disclosure includes a substrate, a buffer layer, a thin film transistor, a conductive layer and a routing layer, wherein: the buffer layer is arranged on one side of the substrate; the thin film transistor is arranged on one side of the buffer layer, which is far away from the substrate, and comprises an active layer, a gate insulating layer, a gate electrode and a source drain layer, wherein the source drain layer comprises a source electrode and a drain electrode which are connected to the active layer; the conducting layer is arranged on one side of the buffer layer, which is far away from the substrate; the wiring layer is arranged on one side, away from the substrate, of the conductive layer and is arranged on the same layer with the source drain layer, the wiring layer comprises a first wiring and a second wiring which are arranged at intervals, the first wiring and the second wiring are connected with the conductive layer, and the second wiring is connected with the source drain layer. The array substrate can prevent poor wiring lap joint and improve the product yield.
Description
Technical Field
The disclosure relates to the technical field of display, and particularly relates to a display panel, an array substrate and a manufacturing method of the array substrate.
Background
There are a large amount of thin film transistors and routes in the display panel generally, because circuit structure is complicated, and the area of same rete is limited in the display panel, therefore often need to be located the line connection of different retes, utilize the circuit that is located the line formation control thin film transistor of different retes, but, when connecting different retes, need to a plurality of retes sculpture, in order to form the via hole, the technology degree of difficulty is great, especially when carrying out the sculpture to the great insulating material's of thickness buffer layer, the accurate control of etching process, cause the difficult metal level overlap joint of walking the line of buffer layer top and buffer layer below bad easily, influence the normal work of circuit, make the product yield reduce.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to overcome the above-mentioned deficiencies in the prior art, and provides a display panel, an array substrate and a method for manufacturing the array substrate, which can prevent poor overlapping of traces and improve the yield of products.
According to an aspect of the present disclosure, there is provided an array substrate including:
a substrate;
the buffer layer is arranged on one side of the substrate;
the thin film transistor is arranged on one side, away from the substrate, of the buffer layer and comprises an active layer, a gate insulating layer, a gate electrode and a source drain layer, and the source drain layer comprises a source electrode and a drain electrode which are connected to the active layer;
the conducting layer is arranged on one side of the buffer layer, which is far away from the substrate;
the wiring layer is arranged on one side, away from the substrate, of the conducting layer and is arranged on the same layer with the source drain layer, the wiring layer comprises a first wiring and a second wiring which are arranged at intervals, the first wiring and the second wiring are connected with the conducting layer, and the second wiring is connected with the source drain layer.
In an exemplary embodiment of the present disclosure, the conductive layer and the active layer are disposed in the same layer and are made of the same material.
In an exemplary embodiment of the present disclosure, the conductive layer and the gate are disposed on the same layer and are made of the same material.
In an exemplary embodiment of the present disclosure, the active layer is disposed on a surface of the buffer layer facing away from the substrate, the gate insulating layer is disposed on a surface of the active layer facing away from the substrate, and the gate electrode is disposed on a surface of the gate insulating layer facing away from the substrate;
the thin film transistor further includes:
a dielectric layer covering the gate electrode, the buffer layer and the conductive layer;
the source drain layer and the routing layer are arranged on the surface, deviating from the substrate, of the dielectric layer, the source electrode and the drain electrode are connected with the active layer through different via holes, and the first routing layer and the second routing layer are connected with the conductive layer through different via holes.
In one exemplary embodiment of the present disclosure, the material of the active layer includes indium gallium zinc oxide.
According to an aspect of the present disclosure, there is provided a method of manufacturing an array substrate including a thin film transistor, the method including:
forming a buffer layer on one side of the substrate;
forming a conducting layer, an active layer of the thin film transistor, a gate insulating layer and a gate electrode on one side of the buffer layer, which is far away from the substrate;
forming a routing layer and a source drain layer of the thin film transistor which are arranged on the same layer on one side of the conducting layer, which is far away from the substrate, wherein the source drain layer comprises a source electrode and a drain electrode which are connected to the active layer; the wiring layer comprises a first wiring and a second wiring which are arranged at intervals, the first wiring and the second wiring are both connected with the conducting layer, and the second wiring is connected with the source drain layer.
In one exemplary embodiment of the present disclosure, the conductive layer is formed simultaneously with the active layer; alternatively, the conductive layer is formed simultaneously with the gate electrode.
In an exemplary embodiment of the present disclosure, forming a conductive layer and an active layer, a gate insulating layer and a gate electrode of the thin film transistor on a side of the buffer layer facing away from the substrate includes:
forming a metal oxide layer on the surface of the buffer layer, which is far away from the substrate, through a primary patterning process, wherein the metal oxide layer comprises an active region and a conductive region;
sequentially laminating a gate insulating layer and a gate in a partial area of the surface of the active area, which is far away from the substrate;
conducting treatment is carried out on the region of the active region exposed by the gate insulating layer and the conductive region to obtain an active layer and a conductive layer of the thin film transistor;
forming a dielectric layer covering the gate, the buffer layer and the conductive layer;
forming a routing layer arranged on the same layer and a source drain layer of the thin film transistor on one side of the conducting layer, which is deviated from the substrate, and the method comprises the following steps:
and forming a first routing wire, a second routing wire and a source electrode and a drain electrode of the thin film transistor on the surface of the dielectric layer, which is far away from the substrate, wherein the source electrode and the drain electrode are connected with the active layer through different via holes, the first routing wire and the second routing wire are connected with the conductive layer through different via holes, and the second routing wire is connected with the source electrode.
In an exemplary embodiment of the present disclosure, forming a conductive layer and an active layer, a gate insulating layer and a gate electrode of the thin film transistor on a side of the buffer layer facing away from the substrate includes:
forming an active layer of the thin film transistor on the surface of the buffer layer, which is far away from the substrate;
forming an insulating material layer covering the active layer and the buffer layer;
forming a gate material layer on the surface of the insulating material layer, which faces away from the substrate;
patterning the gate material layer and the insulating material layer by a one-step composition process to obtain an insulating layer and a conducting layer, and a gate insulating layer and a gate of the thin film transistor, wherein the conducting layer is positioned on the surface of the insulating layer, which is far away from the substrate, and the gate is positioned on the surface of the gate insulating layer, which is far away from the substrate;
forming a dielectric layer covering the gate, the buffer layer and the conductive layer;
forming a routing layer arranged on the same layer and a source drain layer of the thin film transistor on one side of the conducting layer, which is deviated from the substrate, and the method comprises the following steps:
and forming a first routing wire, a second routing wire and a source electrode and a drain electrode of the thin film transistor on the surface of the dielectric layer, which is far away from the substrate, wherein the source electrode and the drain electrode are connected with the active layer through different via holes, the first routing wire and the second routing wire are connected with the conductive layer through different via holes, and the second routing wire is connected with the source electrode.
According to an aspect of the present disclosure, there is provided a display panel including the array substrate of any one of the above.
According to the display panel, the array substrate and the manufacturing method of the display panel, the first wiring and the second wiring of the wiring layer can be connected through the conducting layer arranged on the different layer of the wiring layer, the second wiring is connected with the source drain layer of the thin film transistor, and therefore an electric signal can be applied to the thin film transistor through the wiring layer. Wherein, because the conducting layer is located the one side that the buffer layer deviates from the substrate, therefore can avoid seting up the via hole at the buffer layer, make the technology degree of difficulty reduce, reduce the risk that the line overlap joint is bad appears, be favorable to ensuring that the circuit normally works, make the product yield promote.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic view of an array substrate in the related art.
Fig. 2 is a schematic view of a first embodiment of an array substrate according to the present disclosure.
Fig. 3 is a schematic view of a second embodiment of an array substrate according to the present disclosure.
FIG. 4 is a flow chart of one embodiment of a method of manufacturing the present disclosure.
Fig. 5 is a flowchart of step S120 in the first embodiment of the manufacturing method of the present disclosure.
Fig. 6 is a schematic structural diagram of step S1230 in fig. 5.
Fig. 7 is a flowchart of step S120 in the second embodiment of the manufacturing method of the present disclosure.
Fig. 8 is a schematic structural diagram of step S1240 in fig. 7.
Description of reference numerals:
FIG. 1: 100. a substrate; 200. a light-shielding layer; 300. a buffer layer; 400. routing; 500. an active layer; 600. a gate insulating layer; 700. a gate electrode; 800. a dielectric layer; 900. and (6) routing.
Fig. 2 to 8: 1. a substrate; 2. a buffer layer; 3. a thin film transistor; 31. an active layer; 32. a gate insulating layer; 33. a gate electrode; 34. a source drain layer; 341. a source electrode; 342. a drain electrode; 35. a dielectric layer; 4. a conductive layer; 5. a wiring layer; 51. a first wire; 52. a second routing; 6. an insulating layer; 7. and a light shielding layer.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first" and "second" are used merely as labels, and are not limiting on the number of their objects.
In the related art, the display panel is divided into an lcd (liquid Crystal display) display panel and an oled (organic Light Emitting diode) display panel. The display panel includes an array substrate having a thin film transistor array and a trace, as shown in fig. 1, taking an OLED display panel using a top gate type thin film transistor as an example, the array substrate may include a substrate 100, a light shielding layer 200, a buffer layer 300, a thin film transistor and a trace 400, wherein:
the light-shielding layer 200 is disposed on one side of the substrate 100, and may have a thickness of 600 nm to 1000 nm. The buffer layer 300 covers the light-shielding layer 200, and is made of an insulating material such as silicon oxide or silicon nitride, and may have a thickness of 600 nm to 1000 nm.
The thin film transistor is disposed on a side of the buffer layer 300 away from the substrate 100, and includes an active layer 500, a gate insulating layer 600, a gate 700, a dielectric layer 800, and a source drain layer 900 stacked in sequence along a direction away from the substrate 100, where the source drain layer 900 includes a source and a drain, and the source and the drain are connected to the active layer 500.
The wiring 400 and the source drain layer 900 are arranged on the same layer and comprise a first section and a second section, the first section and the second section are both connected with the light shielding layer 200 through via holes penetrating through the dielectric layer 800 and the buffer layer 300, the second section is connected with the source drain layer 900, and electric signals can be transmitted to the thin film transistor through the first section, the light shielding layer 200 and the second section. Meanwhile, the first section and the second section of the trace 400 are connected through the light shielding layer 200, so that other lines of the trace can be avoided. However, in order to ensure the effect of the buffer layer 300 covering the light-shielding layer 200 and prevent the light-shielding layer 200 from short-circuiting with other film layers, the thickness of the buffer layer 300 is large, but this increases the difficulty of forming the via hole, and particularly when dry etching is performed, incomplete etching is likely to occur in the thick buffer layer 300, which causes poor overlapping between the trace 400 and the light-shielding layer 200; alternatively, over-etching may occur, which may damage the light-shielding layer 200 and may cause poor bonding between the trace 400 and the light-shielding layer 200.
The present disclosure provides an array substrate, as shown in fig. 2 and 3, which may include a substrate 1, a buffer layer 2, a thin film transistor 3, a conductive layer 4, and a routing layer 5, wherein:
the buffer layer 2 is provided on the substrate 1 side. The thin film transistor 3 is disposed on a side of the buffer layer 2 facing away from the substrate 1, and includes an active layer 31, a gate insulating layer 32, a gate electrode 33, and a source-drain layer 34, and the source-drain layer 34 includes a source electrode 341 and a drain electrode 342 connected to the active layer 31.
The conductive layer 4 is arranged on the side of the buffer layer 2 facing away from the substrate 1. The wiring layer 5 is arranged on one side of the conductive layer 4, which is far away from the substrate 1, and is arranged on the same layer as the source-drain layer 34, the wiring layer 5 comprises a first wiring 51 and a second wiring 52 which are spaced, the first wiring 51 and the second wiring 52 are both connected with the conductive layer 4, and the second wiring 52 is connected with the source-drain layer 34.
According to the array substrate of the embodiment of the present disclosure, the first wire 51 and the second wire 52 of the wire layer 5 can be connected through the conductive layer 4 disposed in a different layer from the wire layer 5, and the second wire 52 is connected with the source drain layer 34 of the thin film transistor 3, so that an electrical signal can be applied to the thin film transistor 3 through the wire layer 5. Wherein, because conducting layer 4 is located the one side that buffer layer 2 deviates from substrate 1, therefore can avoid seting up the via hole at buffer layer 2, make the technology degree of difficulty reduce, reduce the risk that the line overlap joint is bad to appear, be favorable to ensuring that the circuit normally works, make the product yield promote.
The following describes portions of an array substrate according to an embodiment of the present disclosure:
as shown in fig. 2 and 3, the substrate 1 may be made of flexible or hard material such as PI (polyimide), PET (polyethylene terephthalate), or glass, and is not particularly limited.
As shown in fig. 2 and fig. 3, the buffer layer 2 may be disposed on one side of the substrate 1, and the material and thickness of the buffer layer 2 are not particularly limited herein, for example, the material of the buffer layer 2 may include at least one of silicon oxide and silicon nitride, and the thickness of the buffer layer 2 is 600 to 1000 nm.
As shown in fig. 2 and fig. 3, the thin film transistor 3 is disposed on a side of the buffer layer 2 away from the substrate 1, and includes an active layer 31, a gate insulating layer 32, a gate electrode 33, and a source drain layer 34, where the active layer 31 may be made of Indium Gallium Zinc Oxide (IGZO) or other metal oxides, or may be made of other conductive materials.
The gate insulating layer 32 is positioned between the active layer 31 and the gate electrode 33, the source and drain layers 34 include a source electrode 341 and a drain electrode 342 connected to the active layer 31, and the material of the gate electrode 33 may be a metal, for example, copper or an alloy of copper. The thin film transistor 3 may have a top gate structure, and the active layer 31, the gate insulating layer 32, and the gate electrode 33 may be sequentially stacked on a surface of the buffer layer 2 facing away from the substrate 1 in a direction facing away from the substrate 1. Of course, the thin film transistor 3 may have a bottom gate structure, and the gate electrode 33, the gate insulating layer 32, and the active layer 31 may be sequentially stacked on a surface of the buffer layer 2 facing away from the substrate 1 in a direction facing away from the substrate 1.
As shown in fig. 2 and 3, the conductive layer 4 is disposed on a side of the buffer layer 2 facing away from the substrate 1, and is located outside the thin film transistor 3, i.e., in a direction perpendicular to the substrate 1, and has no overlapping area with the thin film transistor 3. The material of the conductive layer 4 may be a metal such as copper or molybdenum, or a metal oxide such as indium gallium zinc oxide, as long as it is conductive, and the material is not particularly limited. Further, in order to simplify the process, the conductive layer 4 may be disposed in the same layer as the active layer 31 and may be made of the same material, so that it may be formed by a single patterning process with the active layer 31; alternatively, the conductive layer 4 may be provided in the same layer as the gate electrode 33 and may be formed of the same material as the gate electrode 33 by a single patterning process.
As shown in fig. 2 and fig. 3, the routing layer 5 is disposed on a side of the conductive layer 4 away from the substrate 1, and is disposed on the same layer as the source drain layer 34, the routing layer 5 may include a first routing line 51 and a second routing line 52 at intervals, both the first routing line 51 and the second routing line 52 are connected to the conductive layer 4, and the second routing line 52 is connected to the source drain layer 34, so that an electrical signal can be transmitted to the thin film transistor 3 through a path formed by the first routing line 51, the conductive layer 4 and the second routing line 52, and the path does not need to pass through the buffer layer 2, thereby avoiding forming a via hole in the buffer layer 2, reducing the process difficulty, and reducing the risk of poor overlap joint of the.
The array substrate of the present disclosure is exemplified below by taking the thin film transistor 3 as a top gate type structure as an example:
as shown in fig. 2, in the first embodiment of the array substrate of the present disclosure, the active layer 31 of the thin film transistor 3 is disposed on the surface of the buffer layer 2 facing away from the substrate 1, and the material of the active layer 31 may be IGZO. The gate insulating layer 32 is disposed on a surface of the active layer 31 facing away from the substrate 1, the gate electrode 33 is disposed on a surface of the gate insulating layer 32 facing away from the substrate 1, and the conductive layer 4 may be disposed on a surface of the buffer layer 2 facing away from the substrate 1, and may be formed simultaneously with the active layer 31, and has the same material and thickness as the active layer 31. Meanwhile, the thin film transistor 3 may further include a dielectric layer 35 made of an insulating material, and the dielectric layer 35 covers the gate electrode 33, the buffer layer 2 and the conductive layer 4. The source drain layer 34 and the routing layer 5 are arranged on the surface of the dielectric layer 35, which is far away from the substrate 1, the source 341 and the drain 342 are connected with the active layer 31 through via holes penetrating through the dielectric layer 35, and the source 341 and the drain 342 are connected with the active layer 31 through different via holes; the first trace 51 and the second trace 52 are connected to the conductive layer 4 through a via penetrating the dielectric layer 35, and the first trace 51 and the second trace 52 are connected to the conductive layer 4 through different vias.
As shown in fig. 3, in the second embodiment of the array substrate of the present disclosure, the active layer 31, the gate insulating layer 32, and the gate electrode 33 of the thin film transistor 3 may be disposed in the same manner as in the first embodiment. The conductive layer 4 may be disposed on the same layer as the gate 33, and may have the same material and thickness, so as to be formed simultaneously with the gate 33, specifically, the insulating layer 6 may be formed on a region of the buffer layer 2 facing away from the substrate 1, where the region corresponds to the gate 33, the insulating layer 6 and the gate insulating layer 32 may have the same material and thickness, and may be formed through the same patterning process, and the gate 33 may be disposed on a surface of the insulating layer 6 facing away from the substrate 1, so as to form the gate 33 simultaneously through one etching process after sequentially forming the insulating material layer and the gate material layer. A gate insulating layer 32, an insulating layer 6, and a conductive layer 4 to simplify the process. Meanwhile, the thin film transistor 3 may further include a dielectric layer 35 made of an insulating material, and the dielectric layer 35 covers the gate electrode 33, the buffer layer 2 and the conductive layer 4. The source drain layer 34 and the routing layer 5 may be disposed in the same manner as in the first embodiment, and are not described herein again.
It should be noted that the routing layers in fig. 2 and 3 are only schematically illustrated in connection relationship, and do not limit the shape and specific structure thereof.
In the third embodiment of the present disclosure, the structure of the thin film transistor 3 and the arrangement of the routing layer 5 may be the same as those of the first embodiment, but the difference is that in this embodiment, the conductive layer 4 may be directly arranged on the surface of the buffer layer 2 away from the substrate 1, without the insulating layer 6, and after the gate insulating layer 32 is formed by a patterning process, the gate electrode 33 and the conductive layer 4 are simultaneously formed by a patterning process.
In addition, in some embodiments of the present disclosure, such as the first and second embodiments described above, as shown in fig. 2 and 3, the array substrate may further include a light shielding layer 7, which may be disposed on a side of the substrate 1 adjacent to the buffer layer 2 and covered by the buffer layer 2. The material of the light shielding layer 7 may be a light-shielding metal material, which is located at a position corresponding to the thin film transistor 3, so that external light can be prevented from affecting the electrical performance of the thin film transistor 3. Meanwhile, although the light-shielding layer may be provided at a position corresponding to the conductive layer 4, since the wiring layer 5 is connected through the conductive layer 4 without depending on the light-shielding layer, the light-shielding layer may not be provided at a position corresponding to the conductive layer 4, thereby simplifying the structure.
The embodiment of the present disclosure provides a method for manufacturing an array substrate, as shown in fig. 4, the array substrate may be the array substrate of any of the above embodiments, and the array substrate includes a thin film transistor. The manufacturing method of the disclosed embodiment may include steps S110 to S130, in which:
step S110, forming a buffer layer on one side of a substrate;
step S120, forming a conducting layer, an active layer of the thin film transistor, a gate insulating layer and a gate electrode on one side of the buffer layer, which is far away from the substrate;
step S130, forming a routing layer and a source drain layer of the thin film transistor which are arranged on the same layer on one side of the conducting layer, which is far away from the substrate, wherein the source drain layer comprises a source electrode and a drain electrode which are connected to the active layer; the wiring layer comprises a first wiring and a second wiring which are arranged at intervals, the first wiring and the second wiring are both connected with the conducting layer, and the second wiring is connected with the source drain layer.
The manufacturing method of the present disclosure has the advantages that reference is made to the above embodiments of the array substrate, and details are not repeated herein.
The following describes the steps of the manufacturing method according to the embodiment of the present disclosure:
in steps S110 to S130, as shown in fig. 2 and 3, the structure of the substrate 1, the buffer layer 2, the thin film transistor 3, the conductive layer 4 and the routing layer 5 can refer to the above embodiment of the array substrate, and will not be described in detail here. Wherein the conductive layer 4 may be formed simultaneously with one of the active layer 31 or the gate electrode 33 in order to simplify the process.
In the first embodiment of the manufacturing method of the present disclosure, as shown in fig. 2, the thin film transistor 3 is a top gate structure, and the conductive layer 4 and the active layer 31 are disposed in the same layer and formed at the same time. Specifically, as shown in fig. 5, step S120 may include steps S1210 to S1250, in which:
step 1210, forming a metal oxide layer on a surface of the buffer layer, which is far away from the substrate, through a primary patterning process, wherein the metal oxide layer comprises an active region and a conductive region;
the material of the metal oxide layer may include IGZO, and a metal oxide material may be formed on the surface of the buffer layer 2 facing away from the substrate 1, and patterned to obtain an active region for forming the active layer 31 and a conductive region for forming the conductive layer 4.
And step 1220, sequentially laminating a gate insulating layer and a gate electrode on a partial area of the surface of the active area, which is far away from the substrate.
The gate electrode 33 is located on a surface of the gate insulating layer 32 facing away from the substrate 1, and the structure of the gate insulating layer 32 and the gate electrode 33 can refer to the above embodiment of the array substrate, and will not be described in detail here.
Step S1230, conducting treatment is performed on the region of the active region exposed by the gate insulating layer and the conductive region to obtain an active layer and a conductive layer of the thin film transistor.
As shown in fig. 6, the region of the active region not covered by the gate insulating layer and the conductive region may be conducted using plasma, which may make H2He or NH3And the like. The active layer 31 is obtained when the active region is made conductive, and the conductive layer 4 is obtained when the conductive region is made conductive.
Step S1240, forming a dielectric layer covering the cover gate, the buffer layer, and the conductive layer.
As shown in fig. 2, the structure of the dielectric layer 35 can refer to the above embodiments of the array substrate, and will not be described in detail here.
Step S1250, forming a first trace, a second trace, and a source and a drain of the thin film transistor on a surface of the dielectric layer away from the substrate, where the source and the drain are connected to the active layer through different via holes, the first trace and the second trace are connected to the conductive layer through different via holes, and the second trace is connected to the source.
As shown in fig. 2, the source electrode 341 and the drain electrode 342 are connected to the active layer 31 through a via penetrating the dielectric layer 35, and the source electrode 341 and the drain electrode 342 are connected to the active layer 31 through different vias; the first trace 51 and the second trace 52 are connected to the conductive layer 4 through a via penetrating the dielectric layer 35, and the first trace 51 and the second trace 52 are connected to the conductive layer 4 through different vias.
The via hole can be formed by dry etching, wherein the adopted process gas can comprise SF6、CF4、O2And the material of the gate electrode 33 may be copper or copper alloy so as not to etch the process gas.
In the second embodiment of the manufacturing method of the present disclosure, as shown in fig. 3, the thin film transistor 3 is a top gate structure, and the conductive layer 4 and the gate electrode 33 are disposed in the same layer and formed at the same time. Specifically, as shown in fig. 7, step S120 may include steps S1210 to S1250, in which:
and step S1210, forming an active layer of the thin film transistor on the surface of the buffer layer, which is far away from the substrate.
Step S1220, forming an insulating material layer covering the active layer and the buffer layer.
Step S1230, forming a gate material layer on the surface of the insulating material layer away from the substrate.
Step S1240, patterning the gate material layer and the insulating material layer by a one-step patterning process to obtain an insulating layer and a conductive layer, and a gate insulating layer and a gate of the thin film transistor, where the conductive layer is located on a surface of the insulating layer away from the substrate, and the gate is located on a surface of the gate insulating layer away from the substrate.
As shown in fig. 8, the gate insulating layer 32 and the insulating layer 6 are both located on the surface of the buffer layer 2 away from the substrate 1, the gate electrode 33 is stacked on the surface of the gate insulating layer 32 away from the substrate 1, and the conductive layer 4 is stacked on the surface of the insulating layer 6 away from the substrate 1.
Step S1250, forming a dielectric layer covering the gate, the buffer layer and the conductive layer.
Accordingly, step S130 includes:
and forming a first routing wire, a second routing wire and a source electrode and a drain electrode of the thin film transistor on the surface of the dielectric layer, which is far away from the substrate, wherein the source electrode and the drain electrode are connected with the active layer through different via holes, the first routing wire and the second routing wire are connected with the conductive layer through different via holes, and the second routing wire is connected with the source electrode.
The structure of the array substrate formed in this embodiment mode can refer to the second embodiment mode of the array substrate, as shown in fig. 3, and the structure thereof is not described in detail herein.
In the third embodiment of the manufacturing method of the present disclosure, the steps of the array substrate are the same as those of the second embodiment, but the difference is that in this embodiment, the conductive layer 4 can be directly disposed on the surface of the buffer layer 2 away from the substrate 1 without the insulating layer 6, and after the gate insulating layer 32 is formed by a patterning process, the gate electrode 33 and the conductive layer 4 are simultaneously formed by a single patterning process.
Further, in some embodiments of the manufacturing method of the present disclosure, before step S110, the manufacturing method may further include:
a light-shielding layer is formed on one side of the substrate 1.
As shown in fig. 2 and fig. 3, the structure of the light shielding layer 7 can refer to the light shielding layer 7 in the above embodiments of the array substrate, and is not described herein again. After the light-shielding layer 7 is formed, step S110 is performed again so that the buffer layer 2 covers the light-shielding layer 7.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
The embodiment of the disclosure also provides a display panel which can be used for electronic equipment such as mobile phones, tablet computers, electronic paper and the like. The display panel of the present disclosure may include the array substrate of any of the above embodiments, and thus has the same technical effects as the array substrate described above. The display panel may be an OLED display panel, and in addition to the array substrate, the display panel may further include an OLED light emitting device disposed on the array substrate, the light emitting device may include an anode, a light emitting layer, and a cathode stacked in a direction away from the array substrate, and the thin film transistor of the array substrate may be connected to the anode of the OLED light emitting device for driving the light emitting layer to emit light. Of course, the display panel of the present disclosure may also be an LCD display panel, and the specific structure thereof will not be described in detail herein.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (10)
1. An array substrate, comprising:
a substrate;
the buffer layer is arranged on one side of the substrate;
the thin film transistor is arranged on one side, away from the substrate, of the buffer layer and comprises an active layer, a gate insulating layer, a gate electrode and a source drain layer, and the source drain layer comprises a source electrode and a drain electrode which are connected to the active layer;
the conducting layer is arranged on one side of the buffer layer, which is far away from the substrate;
the wiring layer is arranged on one side, away from the substrate, of the conducting layer and is arranged on the same layer with the source drain layer, the wiring layer comprises a first wiring and a second wiring which are arranged at intervals, the first wiring and the second wiring are connected with the conducting layer, and the second wiring is connected with the source drain layer.
2. The array substrate of claim 1, wherein the conductive layer and the active layer are disposed on a same layer and are made of a same material.
3. The array substrate of claim 1, wherein the conductive layer and the gate are disposed on the same layer and are made of the same material.
4. The array substrate of claim 1, wherein the active layer is disposed on a surface of the buffer layer facing away from the substrate, the gate insulating layer is disposed on a surface of the active layer facing away from the substrate, and the gate electrode is disposed on a surface of the gate insulating layer facing away from the substrate;
the thin film transistor further includes:
a dielectric layer covering the gate electrode, the buffer layer and the conductive layer;
the source drain layer and the routing layer are arranged on the surface, deviating from the substrate, of the dielectric layer, the source electrode and the drain electrode are connected with the active layer through different via holes, and the first routing layer and the second routing layer are connected with the conductive layer through different via holes.
5. The array substrate of claim 1, wherein the active layer comprises indium gallium zinc oxide.
6. A manufacturing method of an array substrate, wherein the array substrate comprises a thin film transistor, the manufacturing method comprising:
forming a buffer layer on one side of the substrate;
forming a conducting layer, an active layer of the thin film transistor, a gate insulating layer and a gate electrode on one side of the buffer layer, which is far away from the substrate;
forming a routing layer and a source drain layer of the thin film transistor which are arranged on the same layer on one side of the conducting layer, which is far away from the substrate, wherein the source drain layer comprises a source electrode and a drain electrode which are connected to the active layer; the wiring layer comprises a first wiring and a second wiring which are arranged at intervals, the first wiring and the second wiring are both connected with the conducting layer, and the second wiring is connected with the source drain layer.
7. The manufacturing method according to claim 6, wherein the conductive layer is formed simultaneously with the active layer; alternatively, the conductive layer is formed simultaneously with the gate electrode.
8. The manufacturing method according to claim 6, wherein forming a conductive layer and an active layer, a gate insulating layer, and a gate electrode of the thin film transistor on a side of the buffer layer facing away from the substrate comprises:
forming a metal oxide layer on the surface of the buffer layer, which is far away from the substrate, through a primary patterning process, wherein the metal oxide layer comprises an active region and a conductive region;
sequentially laminating a gate insulating layer and a gate in a partial area of the surface of the active area, which is far away from the substrate;
conducting treatment is carried out on the region of the active region exposed by the gate insulating layer and the conductive region to obtain an active layer and a conductive layer of the thin film transistor;
forming a dielectric layer covering the gate, the buffer layer and the conductive layer;
forming a routing layer arranged on the same layer and a source drain layer of the thin film transistor on one side of the conducting layer, which is deviated from the substrate, and the method comprises the following steps:
and forming a first routing wire, a second routing wire and a source electrode and a drain electrode of the thin film transistor on the surface of the dielectric layer, which is far away from the substrate, wherein the source electrode and the drain electrode are connected with the active layer through different via holes, the first routing wire and the second routing wire are connected with the conductive layer through different via holes, and the second routing wire is connected with the source electrode.
9. The manufacturing method according to claim 6, wherein forming a conductive layer and an active layer, a gate insulating layer, and a gate electrode of the thin film transistor on a side of the buffer layer facing away from the substrate comprises:
forming an active layer of the thin film transistor on the surface of the buffer layer, which is far away from the substrate;
forming an insulating material layer covering the active layer and the buffer layer;
forming a gate material layer on the surface of the insulating material layer, which faces away from the substrate;
patterning the gate material layer and the insulating material layer by a one-step composition process to obtain an insulating layer and a conducting layer, and a gate insulating layer and a gate of the thin film transistor, wherein the conducting layer is positioned on the surface of the insulating layer, which is far away from the substrate, and the gate is positioned on the surface of the gate insulating layer, which is far away from the substrate;
forming a dielectric layer covering the gate, the buffer layer and the conductive layer;
forming a routing layer arranged on the same layer and a source drain layer of the thin film transistor on one side of the conducting layer, which is deviated from the substrate, and the method comprises the following steps:
and forming a first routing wire, a second routing wire and a source electrode and a drain electrode of the thin film transistor on the surface of the dielectric layer, which is far away from the substrate, wherein the source electrode and the drain electrode are connected with the active layer through different via holes, the first routing wire and the second routing wire are connected with the conductive layer through different via holes, and the second routing wire is connected with the source electrode.
10. A display panel comprising the array substrate according to any one of claims 1 to 5.
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