CN110828542A - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN110828542A CN110828542A CN201810925081.4A CN201810925081A CN110828542A CN 110828542 A CN110828542 A CN 110828542A CN 201810925081 A CN201810925081 A CN 201810925081A CN 110828542 A CN110828542 A CN 110828542A
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- metal silicide
- layer
- blocking layer
- silicide blocking
- region
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 147
- 239000002184 metal Substances 0.000 claims abstract description 147
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 140
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 140
- 230000000903 blocking effect Effects 0.000 claims abstract description 104
- 239000000463 material Substances 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 239000011810 insulating material Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 46
- 210000000746 body region Anatomy 0.000 claims description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052710 silicon Inorganic materials 0.000 claims description 31
- 239000010703 silicon Substances 0.000 claims description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 239000005543 nano-size silicon particle Substances 0.000 claims description 21
- 235000012239 silicon dioxide Nutrition 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 20
- 238000005229 chemical vapour deposition Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 13
- 239000002096 quantum dot Substances 0.000 claims description 11
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 17
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 238000009826 distribution Methods 0.000 abstract description 8
- 239000002131 composite material Substances 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 description 32
- 230000008569 process Effects 0.000 description 17
- 238000002955 isolation Methods 0.000 description 13
- 239000012535 impurity Substances 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 150000003376 silicon Chemical class 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- NWLLPIVESIULPG-UHFFFAOYSA-N dysprosium indium Chemical compound [In].[Dy] NWLLPIVESIULPG-UHFFFAOYSA-N 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The embodiment of the invention provides a semiconductor device and a forming method thereof, wherein a first metal silicide blocking layer made of an insulating material and a second metal silicide blocking layer made of a conductive material or a semiconductor material are formed on the side wall and the upper surface of a part of a grid electrode structure of an LDMOS transistor device and the surface of a drift region, so that the composite structure of the metal silicide blocking layers can be equivalent to a plurality of floating gates at the same time, the electric field distribution of the device can be uniform, and the breakdown voltage can be improved. Meanwhile, the metal silicide barrier layer is arranged in the boundary area of the grid electrode and the drift region, so that the size of the device can be reduced.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
Laterally Diffused Metal Oxide Semiconductor (LDMOS) is widely used in power integrated circuits because it is more compatible with Complementary Metal Oxide Semiconductor (CMOS) logic processes. LDMOS transistors have significant advantages in key device characteristics such as gain, linearity, switching performance, thermal dissipation, and reduced order.
In the existing LDMOS transistor device, one or two floating gates are formed on the surface of a Shallow Trench Isolation (STI) between a gate and a drain to adjust electric field distribution. However, the breakdown voltage of the conventional LDMOS still needs to be increased.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor device and a method for forming the same to improve the breakdown voltage of an LDMOS transistor device.
The embodiment of the invention provides a method for forming a semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein a body region and a drift region which are separated from each other are formed in the semiconductor substrate;
forming a gate structure overlapping a portion of the body region and a portion of the drift region;
forming a source region in the body region and a drain region in the drift region;
forming a first metal silicide blocking layer, wherein the first metal silicide blocking layer covers the drift region and a part of the grid electrode structure close to one side of the drift region; and
forming a second metal silicide blocking layer on the first metal silicide blocking layer;
the first metal silicide blocking layer is made of an insulating material, and the second metal silicide blocking layer is made of a conductive material or a semiconductor material.
Furthermore, the second metal silicide barrier layer is made of nano silicon quantum dots.
Further, the forming the second metal silicide blocking layer comprises:
depositing a polysilicon layer; and
and thermally oxidizing the polycrystalline silicon layer to form a nano silicon quantum dot layer.
Further, the thickness of the polycrystalline silicon layer is 2 nm-5 nm.
Further, the method for depositing the polycrystalline silicon layer is a chemical vapor deposition method.
Furthermore, the number of the second metal silicide barrier layers is one or more.
Furthermore, the first metal silicide blocking layer is made of silicon-rich silicon dioxide.
Further, the area of the second metal silicide blocking layer is smaller than or equal to the area of the first metal silicide blocking layer.
According to a second aspect of embodiments of the present invention, there is provided a semiconductor device including:
a semiconductor substrate including a body region and a drift region separated from each other;
a source region formed in the body region;
a drain region formed in the drift region;
a gate structure overlapping the body region and the drift region;
the first metal silicide blocking layer covers the drift region and a part of the grid structure close to one side of the drift region; and
a second metal silicide blocking layer overlying the first metal silicide blocking layer;
the first metal silicide blocking layer is made of an insulating material, and the second metal silicide blocking layer is made of a conductive material or a semiconductor material.
Furthermore, the second metal silicide barrier layer is made of nano silicon quantum dots.
Furthermore, the first metal silicide blocking layer is made of silicon-rich silicon dioxide.
Furthermore, the number of the second metal silicide barrier layers is one or more.
Further, the area of the second metal silicide blocking layer is smaller than or equal to the area of the first metal silicide blocking layer.
According to the embodiment of the invention, the first metal silicide blocking layer made of the insulating material and the second metal silicide blocking layer made of the conducting material or the semiconductor material are formed on the side wall and the upper surface of the partial grid electrode structure of the LDMOS transistor device and the surface of the drift region, so that the composite structure of the metal silicide blocking layers can be simultaneously equivalent to a plurality of floating gates, the electric field distribution of the device can be uniform, and the breakdown voltage can be improved. Meanwhile, the metal silicide barrier layer is arranged in the boundary area of the grid electrode and the drift region, so that the size of the device can be reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention;
fig. 2 to 9 are schematic views of structures formed at respective steps of a method of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to". In the description of the present invention, "multi-layer" means two or more layers unless otherwise specified.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Spatial relationship terms such as "below …", "below", "lower", "above …", "above", and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may assume other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly.
Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection.
Fig. 1 is a flow chart of a method of forming a semiconductor device according to an embodiment of the invention. As shown in fig. 1, the forming method of the embodiment of the present invention includes the steps of:
s100, providing a semiconductor substrate, wherein a body region and a drift region which are separated from each other are formed in the semiconductor substrate.
And S200, forming a gate structure overlapped with the body region and the drift region.
And S300, forming a source region in the body region, and forming a drain region in the drift region.
S400, forming a first metal silicide blocking layer, wherein the first metal silicide blocking layer covers the drift region and a part of the grid electrode structure close to one side of the drift region.
And S500, forming a second metal silicide blocking layer on the first metal silicide blocking layer. As shown in fig. 2, in step S100, a semiconductor substrate 10 is provided. A body region 12 and a drift region 11 are formed in the semiconductor substrate 10 to be separated from each other. The semiconductor substrate 10 provided in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 10 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-stacked-germanium (S-SiGeOI), a silicon-on-insulator-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. And a plurality of epitaxial interface layers or strain layers and other structures can be formed on the surface of the semiconductor substrate so as to improve the electrical performance of the semiconductor device. Isolation regions are formed in the semiconductor substrate 10. As an example, the isolation region is a Shallow Trench Isolation (STI) region or a Local Oxidation of Silicon (LOCOS) isolation region. The isolation region may divide the semiconductor substrate 10 into several active regions, etc. In addition, a predetermined circuit structure is formed on the semiconductor substrate 10. It is to be understood that the isolation regions and circuit structures are not shown in order to more clearly demonstrate the nature of the present invention.
The body region 12 and the drift region 11 within the semiconductor 10 are formed by an ion implantation process. In an alternative implementation manner, when the formed LDMOS is a P-type LDMOS, the drift region 11 is doped with P-type impurity ions, and the body region 12 is doped with N-type impurity ions. In another alternative implementation manner, when the LDMOS is formed as an N-type LDMOS, the drift region 11 is doped with N-type impurity ions, and the body region 12 is doped with P-type impurity ions. The N-type impurity ions are one or more of phosphorus (P) ions, arsenic (As) ions and antimony (Te) ions; the P-type impurity ions are one or more of boron (B) ions, indium (In) ions and gallium (Ga) ions. The drift region 11 has a low doping concentration and a high resistance, and can withstand a higher voltage. Meanwhile, the drift region 11 plays a role in buffering between the channel and the drain region, and the short-channel effect of the LDMOS is weakened.
More specifically, the process of forming the drift region 11 includes: before forming the drift region 11, a mask layer is formed on the semiconductor substrate 10, the mask layer exposes a region to be implanted, and corresponding ion implantation is performed on the region to be implanted. The process of forming body region 12 includes: before forming the body region 12, a mask layer is formed on the semiconductor substrate 10, the mask layer exposes a region to be implanted, and corresponding ion implantation is performed on the region to be implanted.
It is to be understood that the body region 12 may be formed after the drift region 11 is formed, and the body region 12 may also be formed before the drift region 11 is formed.
It is to be understood that well regions may also be formed on the semiconductor substrate prior to forming the body region 12 and the drift region 11, which are not shown in order to make the present invention more clear. Referring to fig. 3, in step S200, a gate structure 20 overlapping a portion of the body region 12 and a portion of the drift region 11 is formed. The gate structure 20 overlaps the body region 12 and the drift region 11. The gate structure 20 includes a gate dielectric layer 21 and a gate electrode 22 overlying the gate dielectric layer 21.
Alternatively, the material of the gate dielectric layer 21 may be silicon dioxide (SiO)2) Or high-K dielectric materials, e.g. zirconium oxide (ZrO)2) Alumina (Al)2O3) Or hafnium oxide (HfO)2) And the like. Preferably, the gate dielectric layer 21 may include a stacked silicon oxide layer and a high-K dielectric material layer. The material of the gate electrode 22 may be polysilicon and metal such as tungsten (W), copper (Cu), aluminum (Al), and the like.
In an alternative implementation, the material of the gate electrode 22 is polysilicon. The forming process of the gate structure 20 is as follows: forming a gate dielectric material layer covering the surface of the semiconductor substrate 10; forming a gate electrode material layer on the gate dielectric material layer; and forming a patterned mask layer on the gate electrode material layer, and etching the gate electrode material layer and the gate dielectric material layer by taking the patterned mask layer as a mask to form a gate structure 20 which is stacked on a part of the body region 12 and a part of the drift region 11 and a region between the body region 12 and the drift region 11.
Preferably, a side wall structure (not shown in the figure) is further formed on the side wall of the gate structure 20, the side wall structure can protect the side wall of the gate structure 20 from being damaged by implantation in the subsequent source/drain region ion implantation process, and the side wall structure controls the position of a source region formed in the body region subsequently.
Referring to fig. 4, in step S300, a source region 14 is formed in the body region 12 on a side close to the gate structure 20, and a drain region 13 is formed in the drift region 11 on a side far from the gate structure 20. The depth of the source region 14 is smaller than that of the body region 12, and the depth of the drain region 13 is smaller than that of the drift region 11.
The drift region 11 acts as a buffer between the gate structure 20 and the drain region 13, and the length of the drift region from the drain region 13 to the gate structure 20 affects the breakdown voltage and the on-resistance of the LDMOS.
The source region 14 and the drain region 13 may be formed by source-drain ion implantation. In an alternative implementation manner, when the formed LDMOS is a P-type LDMOS, P-type impurity ions are doped in the drain region 13 and the source region 14; in another alternative implementation, when the LDMOS is formed as an N-type LDMOS, the drain region 13 and the source region 14 are doped with N-type impurity ions. The N-type impurity ions are one or more of phosphorus (P) ions, arsenic (As) ions and antimony (Te) ions; the P-type impurity ions are one or more of boron (B) ions, indium (In) ions and gallium (Ga) ions.
In an optional implementation manner, when the impurity ions implanted by the source-drain ion implantation are one or more of phosphorus (P) ions, arsenic (As) ions and antimony (Te) ions, the implantation angle of the source-drain ion implantation is 0-5 degrees, and the implantation dose is 5E13atom/cm2～5E15atom/cm2The implantation energy is 6Kev to 50 Kev. In another optional implementation manner, when the impurity ions injected by the source-drain ion injection are one or more of boron (B) ions, indium (In) ions and gallium (Ga) ions, the injection angle of the source-drain ion injection is 0-5 degrees, and the injection dose is 5E13atom/cm2～5E15atom/cm2The implantation energy is 12Kev to 50 Kev.
Referring to fig. 5, in step S400, a first metal silicide blocking Layer (SAB) 17 is formed. The first metal silicide blocking layer 17 covers the drift region 11 and a portion of the gate structure 20 near one side of the drift region 11. Preferably, as shown in fig. 6, the first metal silicide blocking layer 17 may also further extend to a portion of the surface of the drain region. Preferably, the first metal silicide blocking layer 17 has a step-shaped structure, and the first metal silicide blocking layer 17 covers a portion of the sidewall and the upper surface of the gate structure 20 and a portion of the upper surface of the drain region 13, so that the gate structure 20 and the drift region 11 can be better isolated.
The first metal silicide blocking layer 17 is an insulating material, and the material of the first metal silicide blocking layer 17 may be silicon oxide (SiO)2) Silicon nitride (SiN), Silicon oxynitride (SiON), and the like, preferably Silicon rich Silicon dioxide (SRO). Silicon-rich silicon dioxide has a higher extinction coefficient than silicon dioxide and thus can avoid the influence on the semiconductor substrate 10 in the subsequent dry etching process.
The first metal silicide barrier layer 17 may be formed by any conventional technique known to those skilled in the art, and preferably by a Chemical Vapor Deposition (CVD) method, such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like.
In an alternative implementation manner, the method for forming the first metal silicide blocking layer 17 is to deposit a silicon-rich silicon dioxide layer on the surface of the drift region 11 and on the sidewall and the surface of the portion of the gate structure 20 close to one side of the drift region 11, and the specific steps include: and forming a silicon-rich silicon dioxide layer which completely covers the surface of the device by adopting a chemical vapor deposition method. Then coating photoresist to form a patterned mask layer, then performing dry etching and removing the photoresist to finally obtain the structure shown in FIG. 5The structure shown. The technological parameters of the chemical vapor deposition method for depositing the silicon-rich silicon dioxide layer are as follows: by using N2O and SiH4As a reaction gas, N2O and SiH4The flow ratio of (2) is 8.1: 1-8.5: 1, a silicon-rich silicon dioxide layer is deposited in the exposed area. Preferably, said N is2O and SiH4The flow ratio of (2) is 8.3: 1, the thickness of the silicon-rich silicon dioxide layer is 315-385 angstroms.
Referring to fig. 7, in step S500, a second metal silicide blocking layer 18 is formed on the first metal silicide blocking layer 17. The material of the second metal silicide blocking layer 18 is a conductive material or a semiconductor material, and the material of the second metal silicide blocking layer 18 may be silicon, silicon carbide, silicon phosphide, polysilicon, or the like. In an alternative implementation, the second metal silicide block layer 18 has a nano-silicon quantum dot layer.
The second metal silicide blocking layer 18 may cover all of the first metal silicide blocking layer 17 or may cover only a portion of the first metal silicide blocking layer 17. Preferably, as shown in fig. 8, the second metal silicide blocking layer 18 may cover the entire first metal silicide blocking layer 17 and have the same stepped structure, the same length and width dimensions as the first metal silicide blocking layer 17, and the first metal silicide layer 17 and the second metal silicide layer 18 are coextensive over a portion of the drain region 13. Since the first metal silicide layer 17 and the second metal silicide layer 18 extend to the drain region 13 together, a capacitance is formed with the first metal silicide layer 17 as a dielectric layer and the drain region 13 and the second metal silicide layer 18 as electrodes, and thus the electric field of the drain region 13 can be adjusted. Meanwhile, the overlapped first metal silicide blocking layer 17 and the second metal silicide blocking layer 18 formed on the partial upper surface of the gate structure 20 and the side wall surface adjacent to the drift region are also equivalent to forming a capacitor structure with the gate structure 20 and the second metal silicide blocking layer 18 as electrodes and the first metal silicide blocking layer 17 as a dielectric layer, so that the distribution of electric fields can be further adjusted. The overlapped first metal silicide blocking layer 17 and the second metal silicide blocking layer 18 formed on the partial upper surface of the gate structure 20 and the side wall surface adjacent to the drift region do not occupy the lateral dimension while adjusting the distribution of the electric field, so that the LDMOS transistor structure can have a smaller area while improving the breakdown voltage, and further the production efficiency can be improved. The stepped structure of the second metal silicide blocking layer 18 can reduce the electric field peak at the edge of the second metal silicide blocking layer 18.
Since the first metal silicide blocking layer 17 and the second metal silicide blocking layer 18 have the same overall dimension, the same mask layer can be adopted in the process of depositing the silicon-rich silicon dioxide layer in the step S400 and the process of depositing the polysilicon layer in the step S500, so that the mask is saved, and the production efficiency is improved. Furthermore, the process conditions for depositing the silicon-rich silicon dioxide layer are similar to those for depositing the polysilicon layer, and the process conditions can be completed in the same chemical vapor deposition equipment, so that the conversion flow among the working procedures is reduced, and the production efficiency is further improved.
In an optional implementation manner, a first metal silicide blocking layer material layer made of silicon-rich silicon dioxide and covering the whole semiconductor structure is deposited by a chemical vapor deposition method, then a second metal silicide blocking layer material layer including a nano silicon quantum dot layer and covering the first metal silicide blocking layer material layer is deposited by a chemical vapor deposition method, finally photoresist is coated to form a patterned mask layer, the uncovered area of the mask layer is etched, and a first metal silicide blocking layer 17 and a second metal silicide blocking layer 18 which are sequentially overlapped are formed.
The second metal silicide barrier layer 18 may be formed by any conventional technique known to those skilled in the art, and preferably by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), etc.
In an alternative implementation, the second metalThe silicide-block layer 18 comprises a layer of nano-silicon quantum dots. The second metal silicide blocking layer 18 covers the entire first metal silicide blocking layer 17 and has the same outer dimensions as the first metal silicide blocking layer 17. Specifically, the method for forming the nano silicon quantum dots comprises the following steps: depositing a polysilicon layer; and thermally oxidizing the polysilicon layer to form a nano-silicon quantum dot layer. Optionally, a chemical vapor deposition method is used to deposit a polysilicon layer, and the thickness of the deposited polysilicon layer is very thin, preferably 2-5 nm. The specific process parameters can be as follows: the process gas being Silane (SiH)4) The gas flow is 40 sccm-200 sccm, the gas pressure is 150 mtorr-250 mtorr, and the temperature is 500 ℃ -600 ℃. Subsequently, the polysilicon layer is thermally oxidized such that 10% to 80% of the polysilicon is converted into silicon oxide. The specific process parameters may be: the process gas is oxygen (O)2) And nitrogen (N)2) Oxygen (O)2) Gas flow of 1600sccm, nitrogen (N)2) The gas flow of the reactor is 8000sccm, and the temperature is 700-1100 ℃; the air pressure is standard atmospheric pressure. The thickness of the silicon nano-silicon quantum dot layer can be controlled by repeating the steps of depositing a polysilicon layer and thermally oxidizing the polysilicon layer a plurality of times. Preferably, the deposition of the polycrystalline silicon layer and the thermal oxidation of the polycrystalline silicon layer are repeated for 2-3 times.
The second metal silicide blocking layer 18 may prevent formation of metal silicide between the gate structure 20 and the drain region 13 during subsequent deposition of a metal layer to form metal silicide. Meanwhile, the nano silicon quantum dot layer is the polysilicon nano particles which are isolated from each other, which is equivalent to forming a plurality of floating gates on the surface of the first metal silicide blocking layer 17, so that the electric field distribution is uniform, the transverse electric field of the LDMOS transistor device is considered to be adjusted, and the withstand voltage of the device is improved. Meanwhile, the stepped structure of the second metal silicide blocking layer 18 can reduce the electric field peak value at the edge of the second metal silicide blocking layer 18. Since the nano silicon quantum dots make the electric field distribution uniform, the distance from the gate structure 20 to the drain region 13 and the length of the gate structure 20 can be reduced without forming an electric field peak.
As shown in fig. 9, after forming the second metal silicide blocking layer 18, a Salicide formation process (Salicide) is performed to form a metal silicide 30 on the surfaces of the source region 14, the drain region 13 and the gate structure 20, so as to reduce the contact resistance between the active region of the device and the metal interconnect structure, wherein the metal silicide 30 is not formed on the upper surface and the sidewall of the gate structure and the surface of the drift region, which are covered by the first metal silicide blocking layer 17 and the second metal silicide blocking layer 18.
The self-aligned silicide formation process comprises the following steps: first, a metal layer, such as nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt), or a combination thereof, is deposited. Annealing, preferably Rapid annealing (RTA), is performed to react the deposited metal layer with the silicon on the surface of the source and drain regions to form a metal silicide. An etchant is then used that attacks the metal layer, but not the metal silicide regions, to remove the unreacted metal layer.
Different from the prior art that the breakdown voltage is improved by forming the STI between the drain region and the gate structure, the embodiment of the invention greatly improves the breakdown voltage of the formed LDMOS transistor by forming the first metal silicide blocking layer and the second metal silicide blocking layer on the surface and the side wall of part of the gate structure and the surface of the drift region. Meanwhile, compared with the prior art, STI is not formed in the embodiment of the invention, so that the on-resistance can be greatly reduced, and the performance of the LDMOS transistor device is comprehensively improved. Meanwhile, due to the improvement of the breakdown voltage of the embodiment of the invention, under the condition of the same breakdown voltage, the LDMOS transistor device formed by the embodiment of the invention can have a smaller area than that of the LDMOS transistor device formed by the prior art.
In the embodiment of the invention, a first metal silicide barrier layer made of silicon-rich silicon dioxide and a second metal silicide barrier layer made of nano silicon quantum dots are formed on the side wall and the upper surface of a part of a grid electrode structure of the LDMOS transistor device and the surface of a drift region. The second metal silicide blocking layer comprising the nano silicon quantum dot layer plays a role of a floating gate, so that the electric field is uniformly distributed. And the distance between the grid structure and the drain and the length of the grid can be reduced, an electric field peak value can not be formed, and the area of a chip is reduced.
As shown in fig. 9, an embodiment of the present invention further provides an LDMOS transistor device, which includes a semiconductor substrate 10, a source region 14, a drain region 13, a gate structure 20, a first metal silicide blocking layer 17, a second metal silicide blocking layer 18, and a metal silicide layer 30 on the surface of the source region 14, the drain region 13, and the gate structure 20.
The semiconductor substrate 10 includes a body region 12 and a drift region 11, and the body region 12 and the drift region 11 are separated from each other. The semiconductor substrate 10 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 10 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-stacked-germanium (S-SiGeOI), a silicon-on-insulator-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. And a plurality of epitaxial interface layers or strain layers and other structures can be formed on the surface of the semiconductor substrate so as to improve the electrical performance of the semiconductor device. Isolation regions are formed in the semiconductor substrate 10. As an example, the isolation region is a Shallow Trench Isolation (STI) region or a local oxidation of silicon (LOCOS) isolation region. The isolation region may divide the semiconductor substrate 10 into several active regions, etc. In addition, a predetermined circuit structure is formed on the semiconductor substrate 10. It is to be understood that the isolation regions and circuit structures are not shown in order to more clearly demonstrate the nature of the present invention.
The source region 14 is formed in the body region 12 near one end of the gate structure 20.
The drain region 13 is formed in the drift region 11 at an end remote from the gate structure 20.
The gate structure 20 overlaps the body region 12 and the drift region 11. The gate structure 20 includes a gate dielectric layer 21 and a gate electrode 22 stacked in sequence. The material of the gate dielectric layer 21 may be silicon dioxide (SiO)2) And high-K dielectric materials, such as zirconium oxide (ZrO)2) Or aluminum oxide (Al)2O3) And hafnium oxide (HfO)2) Etc., preferably, the gateThe dielectric layer 21 may include a stacked silicon oxide layer and a high-K dielectric material layer. The material of the gate electrode 22 may be polysilicon and metal such as tungsten (W), copper (Cu), aluminum (Al), and the like.
The first metal silicide blocking layer 17 covers the drift region 11 and a portion of the gate structure 20 near one side of the drift region 11, and the material of the first metal silicide blocking layer 17 is an insulating material, and may be silicon Oxide, silicon nitride, silicon oxynitride, or the like, and is preferably silicon-rich silicon dioxide (SRO).
The second metal silicide blocking layer 18 is overlapped on the first metal silicide blocking layer 17, and the material of the second metal silicide blocking layer 18 is a conductive material or a semiconductor material, and may be silicon, silicon carbide, silicon phosphide, or the like, preferably is polysilicon, and more preferably is nano-silicon quantum dots.
In an alternative implementation, the LDMOS transistor device is an N-type LDMOS, and includes a semiconductor substrate 10 made of monocrystalline silicon, where the semiconductor substrate 10 is P-type doped or has a P-type doped well region. In the semiconductor substrate 10 there is a P-doped body region 12 and an N-doped drift region 11 separated from each other. The body region 12 has a different doping concentration than the semiconductor substrate 10. In the body region 12 there is a source region 14 of N-type doping and in the drift region 11 there is a drain region 13 of N-type doping. The drift region 11 and the drain region 13 have different doping concentrations. The depth of the source region 14 is smaller than that of the body region 12, and the depth of the drain region 13 is smaller than that of the drift region 11. A gate structure 20 is arranged on the surface of the body region 12 and the surface of a part of the drift region 11, and on the surface of the semiconductor substrate between the body region 12 and the drift region 11, and the gate structure 20 comprises a gate dielectric layer 21 and a gate electrode 22 which are sequentially overlapped. The gate dielectric layer 21 is made of silicon oxide, and the gate electrode 22 is made of polysilicon. On the surface of the drift region 11 and on the upper surface and on the sidewalls of the gate structure 20 near the drift region 11 there is a first metal silicide blocking layer 17 and a second metal silicide blocking layer 18, which are stacked in sequence. The first metal silicide blocking layer 17 is made of SRO, and the second metal silicide blocking layer 18 includes a nano silicon quantum dot layer. The first metal silicide blocking layer 17 and the second metal silicide blocking layer 18 have the same outer dimension, extend to the drain region 13, and have a stepped structure.
In the embodiment of the invention, a first metal silicide barrier layer made of silicon-rich silicon dioxide and a second metal silicide barrier layer made of nano silicon quantum dots are formed on the side wall and the upper surface of a part of a gate structure of the LDMOS transistor device and the surface of a drift region. The second metal silicide barrier layer made of the nano silicon quantum dots plays a role of a floating gate, so that the electric field is uniformly distributed, and the breakdown voltage is reduced. And the distance between the grid structure and the drain and the length of the grid can be reduced, an electric field peak value can not be formed, and the area of a chip is reduced.
According to the embodiment of the invention, the first metal silicide blocking layer made of the insulating material and the second metal silicide blocking layer made of the conducting material or the semiconductor material are formed on the side wall and the upper surface of the partial grid electrode structure of the LDMOS transistor device and the surface of the drift region, so that the composite structure of the metal silicide blocking layers can be simultaneously equivalent to a plurality of floating gates, the electric field distribution of the device can be uniform, and the breakdown voltage can be improved. Meanwhile, the metal silicide barrier layer is arranged in the boundary area of the grid electrode and the drift region, so that the size of the device can be reduced.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein a body region and a drift region which are separated from each other are formed in the semiconductor substrate;
forming a gate structure overlapping a portion of the body region and a portion of the drift region;
forming a source region in the body region and a drain region in the drift region;
forming a first metal silicide blocking layer, wherein the first metal silicide blocking layer covers the drift region and a part of the grid electrode structure close to one side of the drift region; and
forming a second metal silicide blocking layer on the first metal silicide blocking layer;
the first metal silicide blocking layer is made of an insulating material, and the second metal silicide blocking layer is made of a conductive material or a semiconductor material.
2. The method of forming of claim 1, wherein the second metal silicide block layer comprises a nano-silicon quantum dot layer.
3. The method of forming of claim 2, wherein the forming of the second metal silicide barrier layer comprises:
depositing a polysilicon layer; and
and thermally oxidizing the polysilicon layer to form the nano-silicon quantum dot layer.
4. The method of forming of claim 3, wherein the polysilicon layer has a thickness of 2nm to 5 nm.
5. The method of claim 3, wherein the method of depositing the polysilicon layer is a chemical vapor deposition method.
6. The method of claim 2, wherein the number of layers of the nano-silicon quantum dots is one or more.
7. The method of claim 1, wherein the first metal silicide blocking layer is silicon-rich silicon dioxide.
8. The method of forming of claim 1, wherein an area of the second metal silicide barrier layer is less than or equal to an area of the first metal silicide barrier layer.
9. A semiconductor device, comprising:
a semiconductor substrate including a body region and a drift region separated from each other;
a source region formed in the body region;
a drain region formed in the drift region;
a gate structure overlapping the body region and the drift region;
the first metal silicide blocking layer covers the drift region and a part of the grid structure close to one side of the drift region; and
a second metal silicide blocking layer overlying the first metal silicide blocking layer;
the first metal silicide blocking layer is made of an insulating material, and the second metal silicide blocking layer is made of a conductive material or a semiconductor material.
10. The device of claim 9, wherein the second metal silicide block layer comprises a nano-silicon quantum dot layer.
11. The device of claim 9, wherein the first metal silicide blocking layer is silicon-rich silicon dioxide.
12. The device of claim 9, wherein the number of layers of the second metal silicide blocking layer is one or more.
13. The device of claim 9, wherein an area of the second metal silicide barrier layer is less than or equal to an area of the first metal silicide barrier layer.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790088A (en) * | 2012-07-20 | 2012-11-21 | 昆山华太电子技术有限公司 | Breakdown voltage-adjustable RF-LDMOS device |
| CN103515191A (en) * | 2012-06-20 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN104409500A (en) * | 2014-11-11 | 2015-03-11 | 上海华虹宏力半导体制造有限公司 | Radio frequency LDMOS (lateral diffused metal oxide semiconductor) and manufacturing method thereof |
| CN105529362A (en) * | 2014-09-30 | 2016-04-27 | 世界先进积体电路股份有限公司 | High-voltage semiconductor device and manufacturing method thereof |
| CN107978635A (en) * | 2016-10-21 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic device |
-
2018
- 2018-08-14 CN CN201810925081.4A patent/CN110828542B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515191A (en) * | 2012-06-20 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN102790088A (en) * | 2012-07-20 | 2012-11-21 | 昆山华太电子技术有限公司 | Breakdown voltage-adjustable RF-LDMOS device |
| CN105529362A (en) * | 2014-09-30 | 2016-04-27 | 世界先进积体电路股份有限公司 | High-voltage semiconductor device and manufacturing method thereof |
| CN104409500A (en) * | 2014-11-11 | 2015-03-11 | 上海华虹宏力半导体制造有限公司 | Radio frequency LDMOS (lateral diffused metal oxide semiconductor) and manufacturing method thereof |
| CN107978635A (en) * | 2016-10-21 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115084245A (en) * | 2022-07-25 | 2022-09-20 | 北京芯可鉴科技有限公司 | LDMOS device, preparation method thereof and chip |
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