CN110828497B - Vertical gate CMOS image sensor and manufacturing method - Google Patents
Vertical gate CMOS image sensor and manufacturing method Download PDFInfo
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Abstract
The invention provides a vertical grid CMOS image sensor and a manufacturing method thereof, wherein a transfer tube is positioned on an epitaxial layer, and a photodiode is arranged on one side of the transfer tube and in the epitaxial layer; the vertical grid of the transfer tube extends into the epitaxial layer and extends to the depth of the photodiode; the reset tube is positioned on the epitaxial layer and on the other side of the transfer tube; n + regions are respectively arranged in the epitaxial layers on the two sides of the reset tube grid; one of the N + regions adjacent to the transfer tube forms a floating diffusion point; the area of the vertical grid of the transfer tube, which is close to the photodiode, is a convex surface, and the area, which is close to the floating diffusion point, is a concave surface. The invention forms a convex surface which is close to the photodiode region and is easy to collect, and a concave surface which is close to the floating diffusion point and is easy to form an electron gathering effect, can collect electrons in the largest area, and can transfer the electrons in a centralized way when transferring towards the floating diffusion point, thereby reducing loss. Thereby achieving an overall improvement in the versatility of electron transfer to collection.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a vertical gate CMOS image sensor and a manufacturing method thereof.
Background
CMOS image sensors have been developed rapidly over the last decade, and are now widely used in the fields of mobile phones, computers, digital cameras, and the like. To meet the market demand, more pixel units are integrated in a unit area, and the pixel size of the CMOS image sensor has been gradually reduced from 5.6mm to 1.0 mm. However, the reduction in pixel size cannot be simply equivalent to reducing the size of a Photodiode (Photodiode) in each direction due to the limitation of the Photodiode effective Full Well Capacity (FWC). If the size is too small to store enough electrons, the image quality may be severely degraded.
The basic structure of a conventional 4T CMOS image sensor is shown in fig. 1, and includes a Photodiode (PD), a transfer transistor (Tx), a reset transistor (RST), a source follower transistor (SF), and a row selection transistor (RS). In the process of sensing light when the Tx is turned off, the P-N junction captures sunlight to generate electrons and holes, the photo-generated electrons are accumulated to the top under the action of an electric field built in the P-N junction, and when the Transfer Gate is turned on, the photo-generated electrons are transmitted to a Floating Diffusion region (Floating Diffusion) through a surface channel and then are read, and the Transfer path of the electrons is shown in fig. 2. The electron transmission mode has a small path, and electrons at the deep position of the photodiode need to pass through the whole junction region, so that the electrons are easily recombined to cause low extraction efficiency. Moreover, electrons at the P-N junction depth require a certain amount of time and voltage to complete the transmission, which is not conducive to fast reading. The development of a Three-Dimensional (Three-Dimensional) pixel region to replace the conventional two-Dimensional channel structure in order to increase the speed and efficiency of electron transfer is an effective approach to solve the above-mentioned problems. As shown in fig. 3, the development of Vertical gates can extend the channel deep into the photodiode. Fig. 4 is a schematic top view of a conventional vertical gate 01. Fig. 5a and 5d are schematic diagrams of a conventional vertical gate, in which electrons move along the same potential plane AA 'BB' (or AA ') and along the floating diffusion point region plane CC' DD ', and in fig. 5b and 5e, the electrons are not easily collected near the floating diffusion point along the same potential plane AA' BB '(or AA'). In fig. 5c and 5f, the entire area is uniform along the floating diffusion point region plane CC 'DD', and the transfer speed is slow. The electron transmission channel is changed from a plane channel to a three-dimensional channel, the transmission channel of electrons is multiplied, the transmission rate of photo-generated electrons is greatly increased, the deep of the channel can reduce the electron residue in the diode, the utilization rate of the photo-generated electrons is improved, and finally the full-well capacity of the photodiode is improved. However, due to the even lateral potential of the solid, electrons still have the chance to be not easily transferred.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a vertical gate CMOS image sensor and a method for manufacturing the same, which are used to solve the problems that the vertical gate in the prior art uses a structure in which the sidewalls are planar, the potential of the entire plane is uniform after receiving electrons, and the potential at the same height becomes a separate area after transfer, and thus effective transfer of electrons cannot be achieved.
To achieve the above and other related objects, the present invention provides a vertical gate CMOS image sensor, comprising:
a transfer tube positioned on the epitaxial layer and a photodiode positioned on one side of the transfer tube and in the epitaxial layer; the vertical grid of the transfer tube extends into the epitaxial layer and extends to the depth of the photodiode;
the reset tube is positioned on the epitaxial layer and on the other side of the transfer tube; n + regions are respectively arranged in epitaxial layers on two sides of a grid electrode of the reset tube; the N + region is positioned in a P well in the epitaxial layer, and a floating diffusion point is formed in one N + region adjacent to the transfer tube;
the area of the vertical grid of the transfer tube, which is close to the photodiode, is a convex surface, and the area of the vertical grid of the transfer tube, which is close to the floating diffusion point, is a concave surface.
Preferably, the part of the vertical gate of the transfer tube extending into the epitaxial layer is a cylinder with a concave side wall, wherein the side wall close to the floating diffusion point is a concave surface, and the other parts are convex surfaces.
Preferably, the cross-sectional concave portion of the vertical grid of concave cylindrical bodies of the side walls forms a sector with an area smaller than 1/3 which is circular in the whole cross-section.
Preferably, the cylindrical transfer pipe vertical grid groove with the concave side wall formed in the third step has a circular angle of 60-120 degrees, and the concave part of the cross section of the cylindrical transfer pipe vertical grid groove forms a fan shape.
Preferably, an upper surface of the photodiode is provided with a pinning layer.
Preferably, a part of the vertical gate of the transfer tube, which is located on the epitaxial layer, is provided with a side wall.
Preferably, the N + region on the floating diffusion point is connected with an amplifying tube, the amplifying tube is connected with a selection tube, and the grid electrode of the selection tube is connected with a voltage VDD; and the N + region on the other side of the reset tube is connected with a voltage VDD.
The invention provides a method for manufacturing a vertical gate CMOS image sensor, which at least comprises the following steps:
providing an epitaxial layer, and forming a P well and two N + regions which are positioned in the P well and are transversely spaced on the epitaxial layer;
step two, forming a photodiode in the epitaxial layer; one of the N + regions adjacent to the photodiode forms a floating diffusion point;
etching the epitaxial layer between the photodiode and the floating diffusion point to form a vertical gate groove of a transfer tube; the depth of the vertical grid groove extends to the depth of the photodiode, the area close to the photodiode is a convex surface, and the area close to the floating diffusion point is a concave surface;
depositing polycrystalline silicon on the epitaxial layer and filling the polycrystalline silicon in the vertical gate groove;
and fifthly, etching the polycrystalline silicon on the epitaxial layer to form a transfer tube vertical gate between the photodiode and the floating diffusion point and a reset tube gate between the two N + regions.
Preferably, in the first step, the P-well is formed by sequentially performing photolithography, etching and ion implantation; and sequentially carrying out photoetching, etching and N-type ion implantation to form the two N + regions.
Preferably, in the second step, the photodiode is formed by sequentially performing photolithography, etching, and ion implantation.
Preferably, the method further comprises a sixth step of forming a pinning layer by ion implantation in an epitaxial layer on the photodiode.
Preferably, the vertical gate trench of the transfer tube formed in step three is in the shape of a cylinder with a concave side wall, wherein the side wall close to the floating diffusion point is a concave surface, and the other parts are convex surfaces.
The cylindrical transfer pipe vertical grid groove with the concave side wall formed in the step three has the sector area formed by the concave part of the cross section of the cylindrical transfer pipe vertical grid groove which is smaller than 1/3 with the circular cross section.
And forming a cylindrical transfer pipe vertical grid groove with an inwards concave side wall in the third step, wherein the concave part in the cross section of the cylindrical transfer pipe vertical grid groove forms a fan-shaped circular angle of 60-120 degrees.
As described above, the vertical gate CMOS image sensor and the manufacturing method of the present invention have the following advantages: the invention forms a convex surface which is close to the photodiode region and is easy to collect, and a concave surface which is close to the floating diffusion point and is easy to form an electron gathering effect, can collect electrons in the largest area, and can transfer the electrons in a centralized way when transferring towards the floating diffusion point, thereby reducing loss. Thereby achieving an overall improvement in the versatility of electron transfer to collection.
Drawings
FIG. 1 is a circuit diagram of a pixel unit in the prior art;
fig. 2 is a schematic diagram of a planar 4-pixel cell in the prior art;
FIG. 3 is a schematic diagram of a vertical 4-pixel cell in the prior art;
FIG. 4 is a schematic diagram of a prior art vertical gate top view;
FIG. 5a is a schematic diagram of a three-dimensional structure of a vertical gate in the prior art;
FIG. 5b is a schematic diagram showing the movement of electrons in the vertical gate potential plane AA 'BB' of FIG. 5 a;
FIG. 5c is a schematic view of the electrons moving along the surface CC 'DD' of the floating diffusion point region in FIG. 5 b;
FIG. 5d is a schematic diagram of a three-dimensional structure of a small-sized vertical gate in the prior art;
FIG. 5e is a schematic diagram showing the movement of electrons in the vertical gate potential plane AA' of FIG. 5 d;
FIG. 5f is a schematic view of the electrons moving along the floating diffusion point region CC 'DD' in FIG. 5 d;
FIG. 6a is a schematic view of a three-dimensional structure of a large-sized vertical gate according to the present invention;
FIG. 6b is a schematic diagram showing the movement of electrons in the vertical gate potential plane AA 'BB' of FIG. 6 a;
FIG. 6c is a schematic view of the electrons moving along the surface CC' of the floating diffusion point region in FIG. 6 a;
FIG. 7a is a schematic view of a three-dimensional structure of a small-sized vertical gate according to the present invention;
FIG. 7b is a schematic diagram showing the movement of electrons in the vertical gate potential plane AA' of FIG. 7 a;
fig. 7c shows the electrons moving along the surface BB' of the floating diffusion point region in fig. 7 a.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 6a to fig. 7 c. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present invention provides a vertical gate CMOS image sensor, which in this embodiment comprises (see fig. 1): a transfer tube positioned on the epitaxial layer and a photodiode positioned on one side of the transfer tube and in the epitaxial layer; the epitaxial layer is a P-type epitaxial layer, (see fig. 3) the vertical gate of the transfer tube extends into the epitaxial layer and extends to the depth of the photodiode; (see fig. 1) a reset tube positioned on the epitaxial layer and on the other side of the transfer tube; n + regions are respectively arranged in epitaxial layers on two sides of a grid electrode of the reset tube; the N + region is positioned in a P well in the epitaxial layer, and a floating diffusion point is formed in one N + region adjacent to the transfer tube; (see also fig. 6a and 6 b.) the area of the vertical gate of the transfer tube near the photodiode is convex and the area near the floating diffusion point is concave.
As shown in fig. 6a, fig. 6a is a schematic view showing a three-dimensional structure of a large-sized vertical gate according to the present invention, that is, the structure of the vertical gate CMOS image sensor according to the present invention is different from the prior art in that a region of the vertical gate close to the photodiode is convex, and a region close to the floating diffusion point is concave. Wherein fig. 6b shows the movement of electrons in the vertical gate potential plane AA ' BB ' in fig. 6a, and fig. 6c shows the movement of electrons along the floating diffusion point region plane CC ' in fig. 6 a. In the invention, for the large-size vertical grid, the polysilicon close to the PD region of the photodiode is a convex surface, and the polysilicon close to the FD region of the floating diffusion point is a concave surface, so that the polysilicon can be collected in the largest area during collection, and can be transferred in a concentrated manner when being transferred to the FD point of the floating diffusion point, thereby reducing the loss. For large sized vertical gates, electrons tend to collect near the floating diffusion point after transfer along the same potential plane AA 'BB'. The potential in the central region along the direction CC' of the floating diffusion point region is strong, and the electrons are easy to transfer all the way into the floating diffusion point FD along the central region.
In the invention, the area of the sector formed by the concave part of the cross section of the vertical grid of the cylinder with the concave side wall is smaller than 1/3 with the circular cross section. For the small-size vertical grid, the concave part is called as a small-size vertical grid, the cross section of the cylinder is circular, the sector area formed by the cross section of the concave part is smaller than 1/3, and further, the central angle of the sector formed by the cross section of the concave part is 60-120 degrees. As shown in fig. 7a, fig. 7a is a schematic diagram illustrating a three-dimensional structure of a small-sized vertical gate in the present invention. The part of the vertical grid of the transfer tube extending into the epitaxial layer is a cylinder with a concave side wall, wherein the side wall close to the floating diffusion point is a concave surface, and the other parts are convex surfaces. That is, the small-sized vertical gate of the present invention has a structure as shown in fig. 7a, in which one side of the cylinder is a concave surface facing the floating diffusion point, and the side of the cylinder facing the photodiode is a convex surface. As shown in fig. 7b, fig. 7b is a schematic diagram showing the movement of electrons in the plane AA' perpendicular to the gate potential in fig. 7 a. After the electrons are transferred along the same potential direction AA', the electrons are easy to gather near the floating diffusion point. As shown in fig. 7c, fig. 7c is a schematic diagram showing the movement of electrons along the floating diffusion point region plane BB' in fig. 7 a. The potential of the central region is strong in the floating diffusion point region surface direction BB', and the electrons easily transfer all the way to the floating diffusion point FD along the central region.
Further, the upper surface of the photodiode is provided with a pinning layer. Furthermore, a side wall is arranged on the part, located on the epitaxial layer, of the vertical grid of the transfer tube. The N + region on the floating diffusion point is connected with an amplifying tube, the amplifying tube is connected with a selection tube, and the grid electrode of the selection tube is connected with a voltage VDD; and the N + region on the other side of the reset tube is connected with a voltage VDD.
The invention also provides a manufacturing method of the vertical gate CMOS image sensor, which at least comprises the following steps:
providing an epitaxial layer, and forming a P well and two N + regions which are positioned in the P well and are transversely spaced on the epitaxial layer; further, in the first step, the P well is formed through photoetching, etching and ion implantation in sequence; and sequentially carrying out photoetching, etching and N-type ion implantation to form the two N + regions.
Step two, forming a photodiode in the epitaxial layer; one of the N + regions adjacent to the photodiode forms a floating diffusion point; furthermore, the photodiode is formed in the second step through photoetching, etching and ion implantation in sequence.
Etching the epitaxial layer between the photodiode and the floating diffusion point to form a vertical gate groove of a transfer tube; the depth of the vertical grid groove extends to the depth of the photodiode, the area close to the photodiode is a convex surface, and the area close to the floating diffusion point is a concave surface; the invention further provides the cylindrical transfer pipe vertical grid groove with the concave side wall formed in the third step, wherein the area of the sector formed by the concave part in the cross section is smaller than 1/3 with the circular cross section. For the small-size vertical grid, the concave part is called as a small-size vertical grid, the cross section of the cylinder is circular, the sector area formed by the cross section of the concave part is smaller than 1/3, and further, the central angle of the sector formed by the cross section of the concave part is 60-120 degrees. For the small-sized vertical gate, the shape of the vertical gate groove of the transfer tube formed in the third step is a cylinder with an inward-concave side wall, wherein the side wall close to the floating diffusion point is a concave surface, and other parts are convex surfaces. As shown in fig. 7a, fig. 7a is a schematic diagram illustrating a three-dimensional structure of a small-sized vertical gate in the present invention. The part of the vertical grid of the transfer tube extending into the epitaxial layer is a cylinder with a concave side wall, wherein the side wall close to the floating diffusion point is a concave surface, and the other parts are convex surfaces. That is, the small-sized vertical gate of the present invention has a structure as shown in fig. 7a, in which one side of the cylinder is a concave surface facing the floating diffusion point, and the side of the cylinder facing the photodiode is a convex surface. As shown in fig. 7b, fig. 7b is a schematic diagram showing the movement of electrons in the plane AA' perpendicular to the gate potential in fig. 7 a. After the electrons are transferred along the same potential direction AA', the electrons are easy to gather near the floating diffusion point. As shown in fig. 7c, fig. 7c is a schematic diagram showing the movement of electrons along the floating diffusion point region plane BB' in fig. 7 a. The potential of the central region is strong in the floating diffusion point region surface direction BB', and the electrons easily transfer all the way to the floating diffusion point FD along the central region.
Depositing polycrystalline silicon on the epitaxial layer and filling the polycrystalline silicon in the vertical gate groove;
and fifthly, etching the polycrystalline silicon on the epitaxial layer to form a transfer tube vertical gate between the photodiode and the floating diffusion point and a reset tube gate between the two N + regions.
Still further, the method further comprises a sixth step of forming a pinning layer by performing ion implantation in an epitaxial layer on the photodiode.
In summary, the invention forms the convex surface near the photodiode region for easy collection and the concave surface near the floating diffusion point for easy formation of electron collection effect, so as to collect electrons in the largest area, and concentrate and transfer the electrons when transferring to the floating diffusion point, thereby reducing loss. Thereby achieving an overall improvement in the versatility of electron transfer to collection. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A vertical gate CMOS image sensor, comprising at least:
a transfer tube positioned on the epitaxial layer; a photodiode on one side of the transfer tube and in the epitaxial layer; the vertical grid of the transfer tube extends into the epitaxial layer and extends to the depth of the photodiode;
the reset tube is positioned on the epitaxial layer and on the other side of the transfer tube; n + regions are respectively arranged in epitaxial layers on two sides of a grid electrode of the reset tube; the N + region is positioned in a P well in the epitaxial layer, and a floating diffusion point is formed in one N + region adjacent to the transfer tube;
the area of the vertical grid of the transfer tube, which is close to the photodiode, is a convex surface, and the area of the vertical grid of the transfer tube, which is close to the floating diffusion point, is a concave surface.
2. The vertical gate CMOS image sensor of claim 1, wherein: the part of the vertical grid of the transfer tube extending into the epitaxial layer is a cylinder with a concave side wall, wherein the side wall close to the floating diffusion point is a concave surface, and the other parts are convex surfaces.
3. The vertical gate CMOS image sensor of claim 2, wherein: the cross section of the concave part of the vertical grid of the cylinder with the concave side wall is formed into a sector with an area smaller than 1/3 with a circular cross section.
4. The vertical gate CMOS image sensor of claim 3, wherein: the cross section of the vertical grid of the cylinder with the concave side wall is concave, and the concave part of the cross section of the vertical grid forms a fan-shaped circular angle of 60-120 degrees.
5. The vertical gate CMOS image sensor of claim 1, wherein: the upper surface of the photodiode is provided with a pinning layer.
6. The vertical gate CMOS image sensor of claim 1, wherein: and the part of the vertical grid of the transfer tube, which is positioned on the epitaxial layer, is provided with a side wall.
7. The vertical gate CMOS image sensor of claim 1, wherein: the N + region on the floating diffusion point is connected with an amplifying tube, the amplifying tube is connected with a selection tube, and the grid electrode of the selection tube is connected with a voltage VDD; and the N + region on the other side of the reset tube is connected with a voltage VDD.
8. The method of fabricating a vertical gate CMOS image sensor according to any one of claims 1 to 7, characterized in that the method comprises at least the steps of:
providing an epitaxial layer, and forming a P well and two N + regions which are positioned in the P well and are transversely spaced on the epitaxial layer;
step two, forming a photodiode in the epitaxial layer; one of the N + regions adjacent to the photodiode forms a floating diffusion point;
etching the epitaxial layer between the photodiode and the floating diffusion point to form a vertical gate groove of a transfer tube; the depth of the vertical grid groove extends to the depth of the photodiode, the area close to the photodiode is a convex surface, and the area close to the floating diffusion point is a concave surface;
depositing polycrystalline silicon on the epitaxial layer and filling the polycrystalline silicon in the vertical gate groove;
and fifthly, etching the polycrystalline silicon on the epitaxial layer to form a transfer tube vertical gate between the photodiode and the floating diffusion point and a reset tube gate between the two N + regions.
9. The method of manufacturing a vertical gate CMOS image sensor according to claim 8, wherein: in the first step, the P trap is formed through photoetching, etching and ion implantation in sequence; and sequentially carrying out photoetching, etching and N-type ion implantation to form the two N + regions.
10. The method of manufacturing a vertical gate CMOS image sensor according to claim 8, wherein: and in the second step, the photodiode is formed by photoetching, etching and ion implantation in sequence.
11. The method of manufacturing a vertical gate CMOS image sensor according to claim 8, wherein: the method further comprises a sixth step of carrying out ion implantation in an epitaxial layer on the photodiode to form a pinning layer.
12. The method of manufacturing a vertical gate CMOS image sensor according to claim 8, wherein: the shape of the vertical grid groove of the transfer tube formed in the third step is a cylinder with an inwards concave side wall, wherein the side wall close to the floating diffusion point is a concave surface, and other parts are convex surfaces.
13. The method of manufacturing a vertical gate CMOS image sensor according to claim 12, wherein: the cylindrical transfer pipe vertical grid groove with the concave side wall formed in the third step has the sector area formed by the concave part of the cross section, which is smaller than 1/3 with the circular cross section.
14. The method of manufacturing a vertical gate CMOS image sensor of claim 13, wherein: and forming a cylindrical transfer pipe vertical grid groove with an inwards concave side wall in the third step, wherein the concave part in the cross section of the cylindrical transfer pipe vertical grid groove forms a fan-shaped circular angle of 60-120 degrees.
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| CN201911133006.5A CN110828497B (en) | 2019-11-19 | 2019-11-19 | Vertical gate CMOS image sensor and manufacturing method |
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