CN110828379A

CN110828379A - Manufacturing method of thin film transistor, thin film transistor and display panel

Info

Publication number: CN110828379A
Application number: CN201910980595.4A
Authority: CN
Inventors: 张猛; 周玮; 闫岩; 王文; 郭海成
Original assignee: Shenzhen University
Current assignee: Shenzhen University
Priority date: 2019-10-15
Filing date: 2019-10-15
Publication date: 2020-02-21

Abstract

The application provides a manufacturing method of a thin film transistor, the thin film transistor and a display panel, wherein the manufacturing method comprises the steps of preparing a silicon wafer; arranging a low-temperature isolation layer on a silicon chip; sequentially arranging a low-temperature grid dielectric layer and a grid layer on a silicon chip; arranging a source drain layer in a silicon wafer; arranging a low-temperature passivation layer on the low-temperature grid dielectric layer and the grid layer; and arranging metal layers on the low-temperature passivation layer, the gate layer and the source drain layer, wherein the metal layers are connected with the gate layer and the source drain layer. By the method, the manufacturing cost can be reduced, and the success rate of manufacturing the thin film transistor in high-resolution display is improved.

Description

Manufacturing method of thin film transistor, thin film transistor and display panel

Technical Field

The invention relates to a manufacturing method of a thin film transistor, the thin film transistor and a display panel.

Background

Currently, high resolution Flat Panel Displays (FPDs) play an important role in modern information exchange and communication processes. Two mainstream technologies of smart phones, televisions, and notebook computers are Active Matrix Liquid Crystal Displays (AMLCDs) and Active Matrix Organic Light Emitting Diode (AMOLED) displays, respectively. Both AMOLED and AMOLED displays require a backplane containing an array of source switches to control the switching state of the pixels. Such a matrix is typically made up of thin film transistors fabricated on a large glass substrate.

The pixels of the FPD are determined by the pixels per inch (ppi). For high-end smart phones, ppi is typically greater than 300, for example, the ppi of Apple iPhone is 326, and the ppi of SONY XPeria Z5 Premium is 806; for the near-eye domain, such as AR and VR, ppi greater than 500 is necessary. To prevent the wood grain effect, the ppi of the OLED display is 3000 or more, for example, GOOVIS G1, 3147ppi of neider optics, pixel size 8.1 μm × 8.1 μm, and panel size 0.6 inch. Because of the poor and non-uniform electrical characteristics of TFTs, larger width-to-length ratio or more TFTs should be used in a pixel to meet the current requirements or to compensate for non-uniformity.

Therefore, it is very challenging to fabricate a screen with ppi > 800 with a TFT backplane. In near-to-eye applications, such panels are manufactured based on well established modern IC manufacturing processes-single crystal silicon wafer processing. Some high temperature processes are involved, including thermal oxidation, dopant diffusion, post annealing to activate dopants, etc. These process temperatures are mostly 9001000 ℃. The small size and high temperature process make the wafer processing cost far more expensive than the preparation of FDRTFT backplanes. Aiming at the prior art, how to design and develop a manufacturing process for manufacturing an FPD with ppi > 1000 using lower cost is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

The present invention provides a method for manufacturing a thin film transistor, a thin film transistor and a display panel.

The invention adopts a technical scheme for solving the technical problems that: a manufacturing method of a thin film transistor, wherein the manufacturing method comprises:

preparing a silicon wafer;

arranging a low-temperature isolation layer on the silicon chip;

sequentially arranging a low-temperature grid dielectric layer and a grid layer on the silicon chip;

arranging a source drain layer in the silicon wafer;

arranging a low-temperature passivation layer on the low-temperature grid dielectric layer and the grid layer;

and arranging metal layers on the low-temperature passivation layer, the grid layer and the source drain layer, wherein the metal layers are connected with the grid layer and the source drain layer.

Another technical solution adopted by the present invention to solve the above technical problems is: provided is a thin film transistor, wherein the thin film transistor includes:

the low-temperature isolation layer is formed on one side of the silicon wafer;

the low-temperature grid dielectric layer is formed on one side of the silicon wafer close to the low-temperature isolation layer;

the grid layer is formed on one side, away from the silicon wafer, of the low-temperature grid dielectric layer;

the source drain layer is formed in the silicon wafer;

the low-temperature passivation layer is formed on the low-temperature grid dielectric layer and the grid layer;

and the metal layer is formed on the low-temperature passivation layer, the grid layer and the source drain layer and is connected with the grid layer and the source drain layer.

The invention adopts another technical scheme for solving the technical problems as follows: a display panel is provided, wherein the display panel comprises the thin film transistor.

Compared with the prior art, the invention has the beneficial effects that: the application provides a manufacturing method of a thin film transistor, the thin film transistor and a display panel, wherein the manufacturing method comprises the steps of preparing a silicon wafer; arranging a low-temperature isolation layer on a silicon chip; sequentially arranging a low-temperature grid dielectric layer and a grid layer on a silicon chip; arranging a source drain layer in a silicon wafer; arranging a low-temperature passivation layer on the low-temperature grid dielectric layer and the grid layer; and arranging metal layers on the low-temperature passivation layer, the gate layer and the source drain layer, wherein the metal layers are connected with the gate layer and the source drain layer. The low-temperature isolation layer, the low-temperature grid dielectric layer, the grid layer, the source drain layer, the low-temperature passivation layer and the metal layer are arranged on the silicon chip in a low-temperature state, so that the problems of low success rate and high cost of manufacturing a high-resolution thin film transistor in the prior art are solved.

Drawings

In order to more clearly illustrate the technical solution in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced, wherein:

fig. 1 is a schematic structural diagram of an embodiment of a thin film transistor according to the present application;

FIG. 2 is a schematic flow chart diagram illustrating an embodiment of a method for fabricating a thin film transistor according to the present application;

FIG. 3 is a schematic flow chart diagram illustrating another embodiment of a method for fabricating a thin film transistor according to the present application;

FIG. 4 is a schematic structural diagram of another embodiment of a thin film transistor of the present application;

FIG. 5 is a schematic flow chart diagram illustrating a method of fabricating a thin film transistor according to yet another embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of a thin film transistor according to yet another embodiment of the present application;

FIG. 7 is a schematic flow chart diagram illustrating a method of fabricating a thin film transistor according to yet another embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of a TFT according to another embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of an embodiment of a display panel according to the present application.

Detailed Description

The invention will be further described with reference to the accompanying drawings and specific embodiments. In the preferred embodiments, the terms "upper", "lower", "left", "right", "middle" and "a" are used for clarity of description only, and are not used to limit the scope of the invention, and the relative relationship between the terms and the terms is not changed or modified substantially without changing the technical content of the invention.

Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of an embodiment of a thin film transistor of the present application, and fig. 2 is a schematic flow chart of an embodiment of a method for manufacturing a thin film transistor of the present application.

The thin film transistor 100 comprises a silicon wafer 11, a low-temperature isolation layer 12, a low-temperature gate dielectric layer 13, a gate layer 14, a source drain layer 15, a low-temperature passivation layer 16 and a metal layer 17. Wherein, the low-temperature isolation layer 12 is formed on one side of the silicon chip 11; a low-temperature gate dielectric layer 13 formed on one side of the silicon wafer 11 close to the low-temperature isolation layer 12; the gate layer 14 is formed on one side of the low-temperature gate dielectric layer 13, which is far away from the silicon wafer 11; a source drain layer 15 formed in the silicon wafer 11; a low-temperature passivation layer 16 formed on the low-temperature gate dielectric layer 13 and the gate layer 14; and a metal layer 17 formed on the low-temperature passivation layer 16, the gate layer 14 and the source/drain layer 15, and connecting the gate layer 14 and the source/drain layer 15.

To manufacture the thin film transistor 100 shown in fig. 1, the method disclosed in this embodiment may specifically include the following steps:

s11: a silicon wafer is prepared.

In the embodiment, a low-temperature Metal-Oxide-Semiconductor (MOS) process is adopted, and a Complementary Metal-Oxide-Semiconductor (CMOS) process is a mature modern integrated circuit process.

The CMOS process includes an NMOS (N-Metal-Oxide-Semiconductor) process and a PMOS (positive channel MOS transistor) process, and generally, the circuit design may be implemented by a single NMOS process or a single PMOS process, or by a process in which an NMOS and a PMOS are combined, that is, a CMOS process.

The maximum temperature of the CMOS process is about 9001000 ℃, while the Flat Panel Display (FPD) Thin Film Transistor (TFT) process is usually fabricated on a large-area glass substrate, and the process temperature is usually below 600 ℃. Although the electrical characteristics of the TFT are inferior to those of a monocrystalline silicon device, the TFT can be applied to large-area low-cost manufacturing, a high-performance TFT substrate can meet the application requirements of televisions and mobile phones, and the pixel density (ppi for short) can reach 800-2500. Near-eye applications such as Augmented Reality (AR)/Virtual Reality (VR) require higher pixel densities to avoid particle effects, and high-end near-eye application display screens ppi exceed 3000 and can only be made with silicon technology.

In the present embodiment, the silicon wafer 11 is used as a substrate, and the silicon wafer 11 may be a silicon wafer, such as an IC-grade silicon wafer, a PV-grade silicon wafer, or the like. The manufacturing method disclosed in the embodiment can be carried out in a low-temperature state, realizes a low-temperature CMOS process, a low-temperature NMOS process and a low-temperature PMOS process, is low in manufacturing cost, and can be manufactured in a large area.

S12: a low temperature isolation layer is disposed on the silicon wafer.

Depositing a low-temperature isolation layer material on one side of the silicon wafer 11, carrying out patterning and other treatments on the low-temperature isolation layer material by adopting a low-temperature process to form a low-temperature isolation layer 12, wherein the low-temperature isolation layer 12 is used as a field oxide on the silicon wafer 11 to isolate devices from each other. Wherein the material of the low temperature isolation layer 12 can be a low dielectric constant material, such as SiO₂(silicon oxide), SiNx (silicon nitride), and the like.

S13: and sequentially arranging a low-temperature grid dielectric layer and a grid layer on the silicon chip.

Depositing a low-temperature gate dielectric layer material on the silicon wafer 11, and obtaining the low-temperature gate dielectric layer 13 by using a low-temperature process, wherein the low-temperature gate dielectric layer material may be a gate oxide material, such as silicon dioxide, silicon nitride, a high dielectric constant material, and the like.

And depositing a gate material on the side of the low-temperature gate dielectric layer 13 away from the silicon wafer 11, and patterning the gate material to obtain the gate layer 14, wherein the gate material is a metal, such as Mo (molybdenum), Al (aluminum), Cu (copper), W (tungsten), and the like.

S14: and arranging a source drain layer in the silicon wafer.

When the source/drain layer 15 is formed on the silicon wafer 11, according to the difference between the low-temperature CMOS process, the low-temperature NMOS process, and the low-temperature PMOS process, a desired ion is selected and injected into the silicon wafer 11 to form the source/drain layer 15, for example, a P-type ion, an N-type ion, or a mixed ion of a P-type ion and an N-type ion may be selected. Through an ion doping process of injecting one or two ions, a source drain layer 15 is formed on one side, close to the low-temperature grid dielectric layer 13, of the silicon wafer 11, and the source drain layer 15 is connected with the low-temperature grid dielectric layer 13.

S15: and arranging a low-temperature passivation layer on the low-temperature grid dielectric layer and the grid layer.

And depositing a low-temperature passivation layer material on the low-temperature gate dielectric layer 13 and the gate layer 14, and performing curing treatment by using a low-temperature process to obtain the low-temperature passivation layer 16, wherein the low-temperature passivation layer material can be silicon nitride and/or silicon dioxide, and the low-temperature passivation layer 16 can protect the gate layer 14, prevent the gate layer 14 from being oxidized, and simultaneously protect the device from factors such as external humidity.

S16: and arranging metal layers on the low-temperature passivation layer, the gate layer and the source drain layer, wherein the metal layers are connected with the gate layer and the source drain layer.

After the low-temperature passivation layer 16 is obtained, a metal material is deposited on the low-temperature passivation layer 16, the gate layer 14 and the source/drain layer 15, and the metal material is patterned into a metal layer 17, which serves as a connection line and a test pad of the thin film transistor 100.

The application provides a manufacturing method of a thin film transistor, which comprises the steps of preparing a silicon wafer; arranging a low-temperature isolation layer on a silicon chip; sequentially arranging a low-temperature grid dielectric layer and a grid layer on a silicon chip; arranging a source drain layer in a silicon wafer; arranging a low-temperature passivation layer on the low-temperature grid dielectric layer and the grid layer; and arranging metal layers on the low-temperature passivation layer, the gate layer and the source drain layer, wherein the metal layers are connected with the gate layer and the source drain layer. By arranging the low-temperature isolation layer, the low-temperature grid dielectric layer, the grid layer, the source drain layer, the low-temperature passivation layer and the metal layer on the silicon chip in a low-temperature state, the manufacturing cost can be reduced, and the success rate of manufacturing the thin film transistor in high-resolution display is improved.

On the basis of the foregoing embodiments, the present application provides three other embodiments of a thin film transistor, and the method disclosed in this embodiment is described in terms of a low-temperature CMOS process, a low-temperature PMOS process, and a low-temperature NMOS process, respectively, and details of the same parts in this embodiment as described above are not repeated herein.

Referring to fig. 3 and 4 together, fig. 3 is a schematic flow chart of another embodiment of a method for manufacturing a thin film transistor according to the present application, and fig. 4 is a schematic structural diagram of another embodiment of a thin film transistor according to the present application. In the low-temperature CMOS process, the method for manufacturing the thin film transistor 200 may specifically include the following steps:

s21: and preparing a P-type silicon wafer.

In this example, the silicon wafer used was a P-type silicon wafer 21, and the P-type silicon wafer 21 was used as a substrate.

S22: and arranging a first silicon dioxide layer on the P-type silicon wafer.

A silicon dioxide film is grown on the P-type silicon wafer 21 to serve as a first silicon dioxide layer, and the first silicon dioxide layer serves as a sacrificial oxide layer to protect the surface. The first silicon dioxide layer here can be formed by LPCVD (Low pressure Chemical vapor deposition), PECVD (Plasma Enhanced Chemical vapor deposition), etc., for example, the method of LPCVD at 425 ℃ is used in the present embodiment, and the thickness of the first silicon dioxide layer is 50 nm.

S23: and arranging photoresist on the first silicon dioxide layer, carrying out patterning treatment, injecting first N-type ions to form an N well between the P-type silicon wafer and the first silicon dioxide layer, and removing the photoresist.

And (3) coating a layer of Photoresist (PR) on the side of the first silicon dioxide layer, which is far away from the P-type silicon wafer 21, carrying out patterning treatment by using a mask, and implanting N-type ions to form an N well 22(N-well) on the side, which is close to the first silicon dioxide layer, of the P-type silicon wafer 21. The N-type ions injected into the N-well 22 may be phosphorus ions or arsenic ions, and in this embodiment, phosphorus ions are used for doping. Because the substrate uses the P-type silicon wafer 21, the P-type silicon wafer 21 is a natural P-well, and after the photoresist is removed, the P-type silicon wafer 21 with the N-well 22 and the P-well is obtained.

S24: and arranging photoresist on the first silicon dioxide layer, carrying out patterning treatment, injecting first P-type ions to form a P field between the P-type silicon wafer and the first silicon dioxide layer, and removing the photoresist and the first silicon dioxide layer.

And photoresist is arranged on the first silicon dioxide layer and is subjected to patterning treatment, and first P-type ions are injected to form a P field 23 between the P-type silicon wafer 21 and the first silicon dioxide layer, namely, a photoetching process is used for defining the injection range of the P-type ions, so that electric leakage among different devices can be prevented. Wherein at least one P-field 23 is arranged adjacent to the N-well 22. After the P field 23 is obtained, the photoresist and the first silicon dioxide layer as a sacrificial oxide layer are stripped.

S25: and depositing silicon dioxide on the P-type silicon wafer, carrying out patterning treatment on the silicon dioxide layer to obtain a second silicon dioxide layer, and carrying out patterning treatment on the second silicon dioxide layer to obtain the low-temperature isolation layer.

And depositing silicon dioxide on the side of the P-type silicon wafer 21 close to the N-well 22, wherein the deposition mode can be a Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), sputtering or other processes. In this embodiment, the thickness of the second silicon dioxide layer is greater than or equal to 500 nm.

The second silicon oxide layer is patterned to form a low temperature isolation layer 24 to expose the device region, and the low temperature isolation layer 24 serves as a field oxide on the P-type silicon wafer 21 to isolate the devices from each other. In the present embodiment, the low temperature isolation layer 24 is disposed adjacent to the P field 23.

S26: and sequentially arranging a low-temperature grid dielectric layer and a grid layer on the P-type silicon wafer.

S261: and depositing a grid medium on the P-type silicon wafer, and patterning the grid medium to form a low-temperature grid medium layer.

S262: and depositing a gate metal on the low-temperature gate dielectric layer to form a gate layer.

In this embodiment, step S26 may include steps S261 to S262, which are described together as follows:

silicon dioxide is deposited on the P-type silicon wafer 21 by a low-temperature process to obtain the low-temperature gate dielectric Layer 25, wherein the Deposition mode may be low-pressure chemical vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), sputtering, or the like. In the present embodiment, the thickness of the low-temperature gate dielectric layer 25 is 70nm, and the heating temperature is 425 ℃ by the LPCVD method.

And depositing a gate material molybdenum metal on the side of the low-temperature gate dielectric layer 25, which is far away from the P-type silicon wafer 21, in a sputtering or evaporation mode, and patterning the molybdenum metal to obtain the gate layer 26. In the present embodiment, the thickness of the gate layer 26 is 200 nm. The gate layer 26 may be disposed between two adjacent low temperature isolation layers 24.

S27: and arranging a source drain layer in the P-type silicon wafer.

S271: and injecting second P-type ions into the N well to perform doping treatment to obtain a first source drain layer.

S272: and injecting N-type ions into the P-type silicon wafer to perform doping treatment to obtain a second source drain electrode layer.

In this embodiment, step S27 may include steps S271 to S272, which are described below:

when the source drain layer 27 is formed on the P-type silicon wafer 21, the source drain layer 27 needs to be respectively disposed on the N-well 22 and the P-well, that is, the source drain layer 27 of the N-well 22 and the source drain layer 27 of the P-well are respectively formed through two ion doping processes. Wherein, the ion doping can be realized by an ion implanter or an ion bombardment mode.

Specifically, the second P-type ions are implanted into the N-well 22 for doping, the photoresist is patterned by setting the photoresist to expose the source/drain (S/D) region of the PMOS device and the body contact region of the NMOS device, and then the photoresist is used as a mask to block the doping and doping of the P-type ions. And after the P-type ion doping is finished, removing the photoresist to obtain a first source drain layer 271, wherein the first source drain layer 271 is arranged in the N well 22 and between the N well 22 and the low-temperature gate dielectric layer 25, and the first source drain layer 271 is also distributed on two sides of the gate layer 26.

And setting photoresist again, injecting N-type ions into the P-type silicon wafer 21 for doping treatment, defining a source-drain (S/D) area of the NMOS device and a body contact area of the PMOS device, and obtaining a second source-drain electrode layer 272, wherein the second source-drain electrode layer 272 is formed in the P-type silicon wafer 21 and is arranged between the P-type silicon wafer 21 and the low-temperature gate dielectric layer 25, and the second source-drain electrode layers 272 are also distributed on two sides of the gate layer 26.

S28: and arranging a low-temperature passivation layer on the low-temperature grid dielectric layer and the grid layer.

S281: and sequentially depositing silicon nitride and silicon oxide on the low-temperature isolation layer, the gate layer and the low-temperature gate dielectric layer, and performing rapid thermal annealing treatment on the silicon nitride and the silicon oxide to obtain a low-temperature passivation layer, wherein the heating temperature is less than or equal to 600 ℃.

S282: and carrying out patterning treatment on the low-temperature passivation layer to obtain a contact hole so as to expose the gate layer, the first source drain layer and the second source drain layer.

In this embodiment, step S28 may include steps S281 to S282, which are described below:

silicon nitride and silicon oxide are sequentially deposited on the low-temperature isolation layer 24, the low-temperature gate dielectric layer 25 and the gate layer 26 to serve as low-temperature passivation layer materials, and the silicon nitride layer is used for preventing metal of the gate layer 26 from being oxidized in a subsequent process and protecting a device from external moisture and the like.

After the deposition of the low-temperature passivation layer material, the P-type silicon wafer 21 is heated to activate the low-temperature passivation layer material, and the activation process may be rapid thermal annealing at a temperature not exceeding 600 ℃ or annealing by a heating stage.

After obtaining the low-temperature passivation layer 28, a patterning process is performed on the low-temperature passivation layer 28 to form a contact hole and an island body on both sides of the contact hole, and the gate layer 26, the first source drain layer 271, and the second source drain layer 272 are exposed at the contact hole.

S29: and arranging metal layers on the low-temperature passivation layer, the gate layer and the source drain layer, wherein the metal layers are connected with the gate layer and the source drain layer.

S291: and depositing metal on the low-temperature passivation layer and the contact hole, and carrying out patterning treatment on the metal.

S292: and carrying out synthetic gas annealing treatment on the metal layer.

In this embodiment, step S29 may include steps S291 to S292, which are described below:

and depositing a metal layer material in the low-temperature passivation layer 28 and the contact hole, patterning the metal material to form a metal layer 29, wherein the metal layer 29 is arranged on the low-temperature passivation layer 28, the gate layer 26 and the source drain layer 27 and is connected with the low-temperature gate dielectric layer 25 in the two island bodies, and patterning the metal layer material into a connecting line and a test pad. The metal layer material may be a mixture of silicon and aluminum, for example, the metal layer material is a mixture of aluminum and silicon, silicon (Si) occupies 1% of the metal layer material, and the thickness of the metal layer 29 is 700 nm. The metal layer 29 is patterned by annealing with Forming gas (Forming gas), which improves the contact between aluminum and silicon.

On the basis of the foregoing embodiments, please refer to fig. 5 and fig. 6 together, in which fig. 5 is a schematic flowchart of another embodiment of a method for manufacturing a thin film transistor according to the present application, and fig. 6 is a schematic structural diagram of another embodiment of a thin film transistor according to the present application. In the low temperature PMOS process, the method for manufacturing the thin film transistor 300 may specifically include the following steps:

s31: an N-type silicon wafer is prepared.

In the low temperature PMOS process, silicon wafer 31 is an N-type silicon wafer 31, so there is no need to form N-wells and P-fields.

S32: a low temperature isolation layer is disposed on the silicon wafer.

A low temperature isolation layer 32 is provided on the N-type silicon wafer 31 to define the active devices.

S33: and arranging a body doping region on the silicon wafer, wherein the body doping region is arranged on one side of the silicon wafer facing the low-temperature isolation layer.

In the low temperature PMOS process, the body contact region is doped N-type, which is similar to the source-drain (S/D) doping of NMOS in the low temperature CMOS process described above. In the embodiment, the N-type silicon wafer 31 is patterned to obtain the first bulk doped region 33, wherein the first bulk doped region 33 is disposed on a side of the N-type silicon wafer 31 facing the low temperature isolation layer 32.

S34: and carrying out thermal annealing treatment on the bulk doping region, wherein the heating temperature is 600 ℃.

After the formation of the body-doped region 33, the N-type silicon wafer 31 is subjected to a thermal annealing process at a temperature of more than 600 ℃.

S35: and sequentially arranging a low-temperature grid dielectric layer and a grid layer on the silicon chip.

S351: and arranging a low-temperature grid dielectric layer on the silicon chip and the low-temperature isolation layer.

S352: and depositing grid metal on the low-temperature grid dielectric layer, and carrying out dry etching treatment on the grid metal to form a grid layer in a graphical mode.

In this embodiment, step S35 may include steps S351 to S352, which are described below:

the low-temperature gate dielectric layer 34 is disposed on the N-type silicon wafer 31 and the low-temperature isolation layer 32, and similar to the above-mentioned low-temperature CMOS process, gate metal is deposited on the low-temperature gate dielectric layer 34, and patterning of the gate metal is to transfer a photoresist pattern onto the metal layer 38, and then dry etching is performed to pattern the photoresist pattern to form the gate layer 35.

S36: and arranging a source drain layer in the silicon wafer.

And injecting third P-type ions into the N-type silicon wafer 31 for doping, and exposing a source/drain (S/D) region to a P-type ion injector or ion bombardment to obtain a third source/drain layer 36, similar to the source/drain (S/D) doping process of the PMOS device in the low-temperature CMOS process, wherein the third source/drain layer 36 is formed in the N-type silicon wafer 31 and is disposed between the low-temperature gate dielectric layer 34 and the N-type silicon wafer 31.

S37: and arranging a low-temperature passivation layer on the low-temperature grid dielectric layer and the grid layer.

And depositing silicon nitride and silicon oxide on the gate layer 35 and the low-temperature gate dielectric layer 34 in sequence to obtain a low-temperature passivation layer 37.

S38: and arranging metal layers on the low-temperature passivation layer, the gate layer and the source drain layer, wherein the metal layers are connected with the gate layer and the source drain layer.

Similar to the low-temperature CMOS process, a metal layer material is disposed on the low-temperature passivation layer 37, the gate layer 35, and the source/drain layer 36, and a metal layer 38 is obtained after curing.

On the basis of the foregoing embodiments, please refer to fig. 7 and fig. 8 together, in which fig. 7 is a schematic flowchart of a manufacturing method of a thin film transistor according to another embodiment of the present application, and fig. 8 is a schematic structural diagram of a thin film transistor according to another embodiment of the present application. In the low temperature NMOS process, the method for manufacturing the thin film transistor 400 may specifically include the following steps:

s41: and preparing a P-type silicon wafer.

In the low temperature NMOS process, the silicon wafer 41 is a P-type silicon wafer 41.

S42: a low temperature isolation layer is disposed on the silicon wafer.

S43: and arranging a body doping region on the silicon wafer, wherein the body doping region is arranged on one side of the silicon wafer facing the low-temperature isolation layer.

Different from the low temperature PMOS process, the body region of the low temperature NMOS is doped with a P-type dopant, that is, fourth P-type ions are implanted into the P-type silicon wafer 41 to perform body doping treatment to obtain a second body doped region 43, wherein the second body doped region 43 is disposed on a side of the P-type silicon wafer 41 facing the low temperature isolation layer 42.

S44: and carrying out thermal annealing treatment on the bulk doping region, wherein the heating temperature is more than 600 ℃.

S45: and sequentially arranging a low-temperature grid dielectric layer and a grid layer on the silicon chip.

S451: and arranging a low-temperature grid dielectric layer on the silicon chip and the low-temperature isolation layer.

S452: and depositing grid metal on the low-temperature grid dielectric layer, and carrying out dry etching treatment on the grid metal to form a grid layer in a graphical mode.

S46: and arranging a source drain layer in the silicon wafer.

Different from the low-temperature PMOS process, the source drain layer 46 is doped N-type, that is, the P-type silicon wafer 41 is patterned to obtain a fourth source drain layer 46, wherein the fourth source drain layer 46 is formed in the P-type silicon wafer 41 and is disposed between the low-temperature gate dielectric layer 44 and the P-type silicon wafer 41.

S47: and arranging a low-temperature passivation layer on the low-temperature grid dielectric layer and the grid layer.

And sequentially depositing silicon nitride and silicon oxide on the gate layer 45 and the low-temperature gate dielectric layer 44, and performing thermal annealing treatment on the silicon nitride and the silicon oxide to activate an N-type dopant to obtain a low-temperature passivation layer 47.

S48: and arranging metal layers on the low-temperature passivation layer, the gate layer and the source drain layer, wherein the metal layers are connected with the gate layer and the source drain layer.

Similar to the low-temperature CMOS process, a metal material is disposed on the low-temperature passivation layer 47, the gate layer 45, and the source/drain layer 46, and a metal layer 48 is obtained after curing.

The present application provides a low temperature metal oxide semiconductor process for high resolution displays, a commercial TFT backplane capable of handling FPDs with PPI < 1000, an expensive silicon chip process capable of handling small size FPDs with PPI > 1000, and no cost effective FPD industry compatible process for manufacturing ultra high PPI displays. The manufacturing cost of the silicon-based display panel is reduced, the production cost and the processing time are shortened, and the blank between the IC technology and the TFT panel technology is filled.

The technical scheme disclosed in the application can realize the low-temperature, low-cost and industrially compatible silicon MOSFET manufacturing process, namely a low-temperature CMOS process, a low-temperature PMOS process and a low-temperature NMOS process. Through the three low-temperature processes, the thin film transistor can be manufactured in a large area at low cost, and then high-resolution virtual reality/augmented reality equipment including a micro OLED projector is manufactured, so that a silicon-based liquid crystal display becomes possible.

In response to the above method, the present application provides a thin film transistor, please refer to fig. 1, where fig. 1 is a schematic structural diagram of an embodiment of the thin film transistor according to the present application. The thin film transistor 100 disclosed by the application comprises a silicon wafer 11, a low-temperature isolation layer 12, a low-temperature grid dielectric layer 13, a grid layer 14, a source drain layer 15, a low-temperature passivation layer 16 and a metal layer 17.

Specifically, the low-temperature isolation layer 12 is formed on one side of the silicon wafer 11; a low-temperature gate dielectric layer 13 formed on one side of the silicon wafer 11 close to the low-temperature isolation layer 12; the gate layer 14 is formed on one side of the low-temperature gate dielectric layer 13, which is far away from the silicon wafer 11; a source drain layer 15 formed in the silicon wafer 11; a low-temperature passivation layer 16 formed on the low-temperature gate dielectric layer 13 and the gate layer 14; and a metal layer 17 formed on the low-temperature passivation layer 16, the gate layer 14 and the source/drain layer 15, and connecting the gate layer 14 and the source/drain layer 15.

The present application provides a thin film transistor 100 that can reduce manufacturing cost and improve the success rate of manufacturing a thin film transistor in high resolution display.

Corresponding to the thin film transistor 100, a display panel 500 is provided, please refer to fig. 9, and fig. 9 is a schematic structural diagram of an embodiment of the display panel. The display panel 500 disclosed in the present application includes the thin film transistor 51, and the detailed description of the thin film transistor 51 is omitted here for the sake of the similarity described above.

The present application provides a display panel 500 that can reduce manufacturing cost and improve the success rate of manufacturing thin film transistors in high resolution display.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention by those skilled in the art are within the technical scope of the present invention without departing from the technical spirit of the present invention.

Claims

1. A method of manufacturing a thin film transistor, the method comprising:

preparing a silicon wafer;

arranging a low-temperature isolation layer on the silicon chip;

arranging a source drain layer in the silicon wafer;

2. The method of claim 1, wherein the silicon wafer is a P-type silicon wafer, and the step of providing a low temperature isolation layer on the silicon wafer comprises:

arranging a first silicon dioxide layer on the P-type silicon wafer;

arranging photoresist on the first silicon dioxide layer, carrying out patterning treatment, injecting first N-type ions to form an N well between the P-type silicon wafer and the first silicon dioxide layer, and removing the photoresist;

arranging the photoresist on the first silicon dioxide layer, carrying out graphical treatment, injecting first P-type ions to form a P field between the P-type silicon wafer and the first silicon dioxide layer, and removing the photoresist and the first silicon dioxide layer;

the step of providing a low temperature isolation layer on the silicon wafer comprises:

depositing silicon dioxide on the P-type silicon wafer, carrying out graphical treatment on the silicon dioxide layer to obtain a second silicon dioxide layer, and carrying out graphical treatment on the second silicon dioxide layer to obtain the low-temperature isolation layer.

3. The method of claim 2, wherein the step of sequentially disposing a low temperature gate dielectric layer and a gate layer on the silicon wafer comprises:

depositing a grid electrode medium on the P-type silicon wafer, and patterning the grid electrode medium to form the low-temperature grid electrode medium layer;

depositing a gate metal on the low-temperature gate dielectric layer to form the gate layer;

the step of arranging the source drain layer in the silicon wafer comprises the following steps:

injecting second P-type ions into the N well to perform doping treatment to obtain a first source drain layer;

and injecting N-type ions into the P-type silicon wafer to perform doping treatment, so as to obtain a second source drain electrode layer.

4. The method of claim 3, wherein the step of disposing a low temperature passivation layer on the low temperature gate dielectric layer and the gate layer comprises:

sequentially depositing silicon nitride and silicon oxide on the low-temperature isolation layer, the gate layer and the low-temperature gate dielectric layer, and performing rapid thermal annealing treatment on the silicon nitride and the silicon oxide to obtain the low-temperature passivation layer, wherein the heating temperature is less than or equal to 600 ℃;

patterning the low-temperature passivation layer to obtain a contact hole so as to expose the gate layer, the first source drain layer and the second source drain layer;

arranging metal layers on the low-temperature passivation layer, the gate layer and the source drain layer, wherein the metal layers are connected with the gate layer and the source drain layer, and the metal layers comprise the following steps:

depositing metal on the low-temperature passivation layer and the contact hole, and carrying out patterning treatment on the metal;

and carrying out synthetic gas annealing treatment on the metal layer.

5. The method of claim 1, wherein the step of sequentially disposing a low temperature gate dielectric layer and a gate layer on the silicon wafer comprises:

arranging a body doping region on the silicon wafer, wherein the body doping region is arranged on one side of the silicon wafer facing the low-temperature isolation layer;

carrying out thermal annealing treatment on the body doping area, wherein the heating temperature is higher than 600 ℃;

the step of sequentially arranging a low-temperature grid dielectric layer and a grid layer on the silicon chip comprises the following steps:

arranging the low-temperature grid dielectric layer on the silicon wafer and the low-temperature isolation layer;

depositing grid metal on the low-temperature grid dielectric layer, and carrying out dry etching treatment on the grid metal to form the grid layer in a graphical mode;

the step of arranging a low-temperature passivation layer on the low-temperature gate dielectric layer and the gate layer comprises the following steps:

and sequentially depositing silicon nitride and silicon oxide on the gate layer and the low-temperature gate dielectric layer to obtain the low-temperature passivation layer.

6. The method of claim 5, wherein the silicon wafer is an N-type silicon wafer, and a bulk doped region is disposed on the silicon wafer, wherein the step of disposing the bulk doped region on a side of the silicon wafer facing the low temperature isolation layer comprises:

carrying out graphical processing on the N-type silicon wafer to obtain a first integral doping area, wherein the first integral doping area is arranged on one side, facing the low-temperature isolation layer, of the N-type silicon wafer;

the step of arranging the low-temperature grid dielectric layer on the silicon chip and the low-temperature isolation layer comprises the following steps:

arranging the low-temperature grid dielectric layer on the N-type silicon wafer and the low-temperature isolation layer;

and injecting third P-type ions into the N-type silicon wafer to carry out doping treatment to obtain a third source drain electrode layer, wherein the third source drain electrode layer is formed in the N-type silicon wafer.

7. The method of claim 5, wherein the silicon wafer is a P-type silicon wafer, and a bulk doped region is disposed on the silicon wafer, wherein the step of disposing the bulk doped region on a side of the silicon wafer facing the low temperature isolation layer comprises:

injecting fourth P-type ions on the P-type silicon wafer to perform body doping treatment to obtain a second body doping area, wherein the second body doping area is arranged on one side, facing the low-temperature isolation layer, of the P-type silicon wafer;

and injecting N-type ions into the P-type silicon wafer to perform doping treatment to obtain a fourth source drain electrode layer, wherein the fourth source drain electrode layer is formed in the silicon wafer.

8. The method of claim 7, wherein the step of disposing a low temperature passivation layer on the low temperature gate dielectric layer and the gate layer comprises:

and sequentially depositing silicon nitride and silicon oxide on the gate layer and the low-temperature gate dielectric layer, and performing thermal annealing treatment on the silicon nitride and the silicon oxide to obtain the low-temperature passivation layer.

9. A thin film transistor, comprising:

the low-temperature isolation layer is formed on one side of the silicon wafer;

the source drain layer is formed in the silicon wafer;

10. A display panel comprising the thin film transistor according to claim 9.