CN110828379A - Manufacturing method of thin film transistor, thin film transistor and display panel - Google Patents

Abstract

The present application provides a method for manufacturing a thin film transistor, a thin film transistor and a display panel, the manufacturing method includes preparing a silicon wafer; disposing a low temperature isolation layer on the silicon wafer; disposing a low temperature gate dielectric layer and a gate electrode layer on the silicon wafer in sequence; A source and drain layer is arranged in the silicon wafer; a low temperature passivation layer is arranged on the low temperature gate dielectric layer and the gate layer; a metal layer is arranged on the low temperature passivation layer, the gate layer and the source and drain layers, and the metal layer is connected to the gate electrode layer and source and drain layers. In the above manner, the manufacturing cost can be reduced, and the success rate of manufacturing thin film transistors in high-resolution displays can be improved.

Description

Manufacturing method of thin film transistor, thin film transistor and display panel

technical field

The invention relates to a manufacturing method of a thin film transistor, a thin film transistor and a display panel.

Background technique

Currently, high-resolution flat panel displays (FPDs) play an important role in modern information exchange and communication processes. The two mainstream technologies for smartphones, TVs and laptops are Active Matrix Liquid Crystal Displays (AMLCDs) and Active Matrix Organic Light Emitting Diode (AMOLED) displays. Both AMOLED and AMOLED displays require a backplane containing an array of active switches to control the switching states of pixels. Such matrices typically consist of thin-film transistors fabricated on large glass substrates.

The pixels of an FPD are determined by pixels per inch (ppi). For high-end smartphones, ppi is usually greater than 300, for example, the ppi of Apple iPhone is 326, and the ppi of SONY Xperia Z5 Premium is 806; for near-eye fields, such as AR and VR, ppi greater than 500 is necessary. In order to prevent the wood grain effect, the ppi of the OLED display should be more than 3000, for example, GOOVIS G1 of Ned Optical Company, 3147ppi, pixel size=8.1μm×8.1μm, and the panel size is 0.6 inches. Due to poor electrical characteristics and non-uniformity of TFTs, a larger aspect ratio or more TFTs should be used in a pixel to meet current requirements or for non-uniformity compensation.

Therefore, it is very challenging to make a ppi>800 screen with a TFT backplane. For near-eye applications, the panels are based on a well-established modern IC manufacturing process - monocrystalline silicon wafer processing. A number of high temperature processes are involved, including thermal oxidation, dopant diffusion, post-annealing to activate dopants, etc. These process temperatures are mostly in the range of 9001000°C. The small size and high temperature process make the processing cost of the silicon wafer far more expensive than the preparation of the FDRTFT backplane. In view of the prior art, how to design and develop a manufacturing process for manufacturing an FPD with ppi>1000 at a lower cost is a technical problem to be solved urgently by those skilled in the art.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to overcome the above-mentioned deficiencies of the prior art, and to provide a method for manufacturing a thin film transistor, a thin film transistor and a display panel.

A technical solution adopted by the present invention to solve the above-mentioned technical problems is: a method for manufacturing a thin film transistor, wherein the manufacturing method includes:

prepare silicon wafers;

A low temperature isolation layer is arranged on the silicon wafer;

A low-temperature gate dielectric layer and a gate layer are sequentially arranged on the silicon wafer;

Disposing source and drain layers in the silicon wafer;

A low-temperature passivation layer is provided on the low-temperature gate dielectric layer and the gate layer;

A metal layer is provided on the low-temperature passivation layer, the gate layer and the source and drain layers, and the metal layer connects the gate layer and the source and drain layers.

Another technical solution adopted by the present invention to solve the above technical problem is to provide a thin film transistor, wherein the thin film transistor comprises:

a silicon wafer and a low temperature isolation layer formed on one side of the silicon wafer;

a low temperature gate dielectric layer, formed on the side of the silicon wafer close to the low temperature isolation layer;

a gate layer, formed on the side of the low-temperature gate dielectric layer away from the silicon wafer;

source and drain layers, formed in the silicon wafer;

a low-temperature passivation layer, formed on the low-temperature gate dielectric layer and the gate layer;

A metal layer is formed on the low temperature passivation layer, the gate layer and the source and drain layers, and connects the gate layer and the source and drain layers.

Another technical solution adopted by the present invention to solve the above technical problem is to provide a display panel, wherein the display panel includes the above-mentioned thin film transistor.

Compared with the prior art, the beneficial effects of the present invention are: the present application provides a method for manufacturing a thin film transistor, a thin film transistor and a display panel, the manufacturing method includes preparing a silicon wafer; disposing a low temperature isolation layer on the silicon wafer; A low-temperature gate dielectric layer and a gate layer are arranged on the chip in sequence; a source and drain layer is arranged in the silicon wafer; a low-temperature passivation layer is arranged on the low-temperature gate dielectric layer and the gate layer; A metal layer is arranged on the source and drain layers, and the metal layer connects the gate layer and the source and drain layers. By arranging a low-temperature isolation layer, a low-temperature gate dielectric layer, a gate layer, a source-drain layer, a low-temperature passivation layer and a metal layer on the silicon wafer in a low-temperature state, it solves the problem of manufacturing high-resolution thin films in the prior art. The problem of low success rate and high cost of transistors.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments, wherein:

FIG. 1 is a schematic structural diagram of an embodiment of a thin film transistor of the present application;

FIG. 2 is a schematic flowchart of an embodiment of a method for manufacturing a thin film transistor of the present application;

3 is a schematic flowchart of another embodiment of a method for manufacturing a thin film transistor of the present application;

FIG. 4 is a schematic structural diagram of another embodiment of a thin film transistor of the present application;

FIG. 5 is a schematic flowchart of another embodiment of a method for manufacturing a thin film transistor of the present application;

FIG. 6 is a schematic structural diagram of another embodiment of a thin film transistor of the present application;

FIG. 7 is a schematic flowchart of still another embodiment of a method for manufacturing a thin film transistor of the present application;

8 is a schematic structural diagram of still another embodiment of a thin film transistor of the present application;

FIG. 9 is a schematic structural diagram of an embodiment of a display panel of the present application.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Terms such as "up", "down", "left", "right", "middle" and "one" quoted in the preferred embodiment are only for the convenience of description and clarity, and are not intended to limit the scope of the present invention. The scope of implementation, the change or adjustment of the relative relationship, and the technical content without substantial change, shall also be regarded as the scope of the present invention.

Please refer to FIG. 1 and FIG. 2 , FIG. 1 is a schematic structural diagram of an embodiment of a thin film transistor of the present application, and FIG. 2 is a schematic flowchart of an embodiment of a manufacturing method of a thin film transistor of the present application.

The thin film transistor 100 includes a silicon wafer 11 , a low temperature isolation layer 12 , a low temperature gate dielectric layer 13 , a gate layer 14 , a source and drain layer 15 , a low temperature passivation layer 16 and a metal layer 17 . Among them, the low temperature isolation layer 12 is formed on one side of the silicon wafer 11; the low temperature gate dielectric layer 13 is formed on the side of the silicon wafer 11 close to the low temperature isolation layer 12; the gate layer 14 is formed on the low temperature gate dielectric layer 13 away from One side of the silicon wafer 11; the source and drain layers 15 are formed in the silicon wafer 11; the low temperature passivation layer 16 is formed on the low temperature gate dielectric layer 13 and the gate layer 14; the metal layer 17 is formed on the low temperature passivation layer On the layer 16 , the gate layer 14 and the source and drain layers 15 , the gate layer 14 and the source and drain layers 15 are connected.

In order to manufacture the thin film transistor 100 shown in FIG. 1 , the method disclosed in this embodiment may specifically include the following steps:

S11: Prepare the silicon wafer.

In this embodiment, a low temperature Metal-Oxide-Semiconductor (MOS, Metal-Oxide-Semiconductor) process is used, and a Complementary Metal Oxide Semiconductor (CMOS, Complementary Metal Oxide Semiconductor) is a mature modern integrated circuit process.

CMOS process includes NMOS (N-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) process and PMOS (positive channel Metal Oxide Semiconductor, P-channel MOS transistor) process. Generally speaking, circuit design can use a separate NMOS process It can be realized by a separate PMOS process, or it can be realized by a combination of NMOS and PMOS processes at the same time, that is, a CMOS process.

The maximum temperature of the CMOS process is about 9001000°C, while the Flat-panel displays (FPD, Thin-Film Transistor) process is usually fabricated on a large-area glass substrate, and the process temperature is usually below 600°C. Although the electrical properties of TFTs are inferior to those of single-crystal silicon devices, they can be used in large-area and low-cost manufacturing. High-performance TFT substrates can meet the needs of TV and mobile phone applications. The pixel per inch (ppi) can be as high as 800-2500. Near-eye applications such as new augmented reality (AR)/virtual reality (VR) require higher pixel density to avoid particle effects, and high-end near-eye application displays with a ppi of more than 3000 can only be fabricated with silicon processes.

In this embodiment, the silicon wafer 11 is used as the substrate, and the silicon wafer 11 may be a silicon wafer, for example, an IC-level silicon wafer, a PV-level silicon wafer, and the like. The manufacturing method disclosed in this embodiment can be performed in a low temperature state, realizes a low temperature CMOS process, a low temperature NMOS process and a low temperature PMOS process, has low manufacturing cost, and can be manufactured in a large area.

S12: A low temperature isolation layer is arranged on the silicon wafer.

A low temperature isolation layer material is deposited on one side of the silicon wafer 11, and the low temperature isolation layer material is patterned by a low temperature process to form a low temperature isolation layer 12. The low temperature isolation layer 12 acts as a field oxide on the silicon wafer 11 to make the devices mutually isolation. Wherein, the material of the low temperature isolation layer 12 may be a low dielectric constant material, for example, SiO ₂ (silicon dioxide), SiNx (silicon nitride) and the like.

S13: A low-temperature gate dielectric layer and a gate layer are sequentially arranged on the silicon wafer.

A low temperature gate dielectric layer material is deposited on the silicon wafer 11, and a low temperature gate dielectric layer 13 is obtained by a low temperature process, wherein the low temperature gate dielectric layer material can be a gate oxide material, such as silicon dioxide, silicon nitride, high dielectric constant material, etc.

A gate material is deposited on the side of the low-temperature gate dielectric layer 13 away from the silicon wafer 11, and the gate material is patterned to obtain a gate layer 14, wherein the gate material is a metal, such as Mo (molybdenum), Al (aluminum) , Cu (copper), W (tungsten) and so on.

S14: Disposing source and drain layers in the silicon wafer.

When forming the source-drain layer 15 on the silicon wafer 11, according to the difference of the low-temperature CMOS process, the low-temperature NMOS process and the low-temperature PMOS process, the required ions are selected and implanted into the silicon wafer 11 to form the source-drain layer 15. For example, it can be Select P-type ions, N-type ions, or a mixture of P-type ions and N-type ions. The source and drain layers 15 are formed on the side of the silicon wafer 11 close to the low temperature gate dielectric layer 13 through an ion doping process of implanting one or two ions, and the source and drain layers 15 are connected to the low temperature gate dielectric layer 13 .

S15: A low-temperature passivation layer is provided on the low-temperature gate dielectric layer and the gate layer.

A low-temperature passivation layer material is deposited on the low-temperature gate dielectric layer 13 and the gate layer 14, and a low-temperature process is used for curing to obtain a low-temperature passivation layer 16. The low-temperature passivation layer material may be silicon nitride and/or silicon dioxide , the low temperature passivation layer 16 can protect the gate layer 14, prevent the gate layer 14 from being oxidized, and can protect the device from external humidity and other factors at the same time.

S16: A metal layer is provided on the low-temperature passivation layer, the gate layer and the source and drain layers, and the metal layer connects the gate layer and the source and drain layers.

After the low-temperature passivation layer 16 is obtained, a metal material is deposited on the low-temperature passivation layer 16 , the gate electrode layer 14 and the source and drain layers 15 , and the metal material is patterned into a metal layer 17 , which is used as the connection line and Test pads.

The present application provides a method for manufacturing a thin film transistor, which includes preparing a silicon wafer; disposing a low-temperature isolation layer on the silicon wafer; disposing a low-temperature gate dielectric layer and a gate layer on the silicon wafer in sequence; disposing a source in the silicon wafer drain layer; a low temperature passivation layer is arranged on the low temperature gate dielectric layer and the gate layer; a metal layer is arranged on the low temperature passivation layer, the gate layer and the source and drain layers, and the metal layer connects the gate layer and the source and drain Floor. By arranging a low-temperature isolation layer, a low-temperature gate dielectric layer, a gate layer, a source-drain layer, a low-temperature passivation layer and a metal layer on the silicon wafer in a low-temperature state, the manufacturing cost can be reduced and the process of manufacturing high-resolution displays can be improved. success rate of thin-film transistors.

On the basis of the above-mentioned embodiments, the present application proposes another three embodiments of thin film transistors. The method disclosed in this embodiment is described according to three processes: low temperature CMOS process, low temperature PMOS process and low temperature NMOS process. In the example, the same part as the above will not be repeated here.

Please refer to FIG. 3 and FIG. 4 together. FIG. 3 is a schematic flowchart of another embodiment of a method for manufacturing a thin film transistor of the present application, and FIG. 4 is a schematic structural diagram of another embodiment of a thin film transistor of the present application. In the low temperature CMOS process, the manufacturing method of the thin film transistor 200 may specifically include the following steps:

S21: Prepare a P-type silicon wafer.

In this embodiment, the silicon wafer used is the P-type silicon wafer 21, and the P-type silicon wafer 21 is used as the substrate.

S22: Disposing a first silicon dioxide layer on the P-type silicon wafer.

A silicon dioxide film is grown on the P-type silicon wafer 21 as a first silicon dioxide layer, and the first silicon dioxide layer is used as a sacrificial oxide layer to protect the surface. The first silicon dioxide layer here can be formed by LPCVD (Low pressure chemical vapor deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), etc., for example, in this embodiment Using the method of LPCVD at 425° C., the thickness of the first silicon dioxide layer is 50 nm.

S23: Disposing a photoresist on the first silicon dioxide layer and performing patterning treatment, implanting first N-type ions to form an N well between the P-type silicon wafer and the first silicon dioxide layer, and removing the photoresist.

A layer of photoresist (PR) is applied on the side of the first silicon dioxide layer away from the P-type silicon wafer 21, patterned with a mask, and N-type ions are implanted to make the P-type silicon wafer 21 close to the first An N-well 22 (N-well) is formed on one side of the silicon dioxide layer. The N-type ions implanted into the N well 22 may be phosphorus ions or arsenic ions, and phosphorus ions are used for doping in this embodiment. Since the substrate is a P-type silicon wafer 21, the P-type silicon wafer 21 is a natural P-well, and after removing the photoresist, a P-type silicon wafer 21 having an N-well 22 and a P-well is obtained.

S24: Disposing a photoresist on the first silicon dioxide layer and performing patterning treatment, implanting first P-type ions to form a P field between the P-type silicon wafer and the first silicon dioxide layer, removing the photoresist and first silicon dioxide layer.

A photoresist is arranged on the first silicon dioxide layer and patterned, and first P-type ions are implanted to form a P field 23 between the P-type silicon wafer 21 and the first silicon dioxide layer, that is, a photolithography process is used. The range of P-type ion implantation is defined so that leakage between different devices can be prevented. Among them, at least one P field 23 is arranged adjacent to the N well 22 . After the P field 23 is obtained, the photoresist and the first silicon dioxide layer, which is a sacrificial oxide layer, are stripped.

S25 : depositing silicon dioxide on the P-type silicon wafer, patterning the silicon dioxide layer to obtain a second silicon dioxide layer, and patterning the second silicon dioxide layer to obtain a low-temperature isolation layer.

Silicon dioxide is deposited on the side of the P-type silicon wafer 21 close to the N well 22, wherein the deposition method may be low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or sputtering and other processes. In this embodiment, the thickness of the second silicon dioxide layer is greater than or equal to 500 nm.

The second silicon dioxide layer is patterned to form a low temperature isolation layer 24 to expose the device area, and the low temperature isolation layer 24 acts as a field oxide on the P-type silicon wafer 21 to isolate the devices from each other. In this embodiment, the low temperature isolation layer 24 is disposed adjacent to the P field 23 .

S26: A low-temperature gate dielectric layer and a gate layer are sequentially arranged on the P-type silicon wafer.

S261 : depositing a gate dielectric on the P-type silicon wafer, and patterning the gate dielectric to form a low temperature gate dielectric layer.

S262 : depositing gate metal on the low temperature gate dielectric layer to form a gate layer.

In this embodiment, step S26 may include steps S261 to S262, which will be described together below:

Silicon dioxide is deposited on the P-type silicon wafer 21 using a low temperature process to obtain a low temperature gate dielectric layer 25, wherein the deposition method may be low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or atomic Layer deposition (ALD, Atomic Layer Deposition) or sputtering and so on. In this embodiment, the thickness of the low-temperature gate dielectric layer 25 is 70 nm, the LPCVD method is adopted, and the heating temperature is 425°C.

The gate material metal molybdenum is deposited on the side of the low-temperature gate dielectric layer 25 away from the P-type silicon wafer 21 . The deposition method may be sputtering or evaporation, and the gate layer 26 is obtained by patterning the metal molybdenum. In this embodiment, the thickness of the gate layer 26 is 200 nm. The gate layer 26 may be disposed between two adjacent low temperature isolation layers 24 .

S27: Disposing source and drain layers in the P-type silicon wafer.

S271 : implanting second P-type ions into the N well for doping treatment to obtain a first source and drain layer.

S272 : implanting N-type ions into the P-type silicon wafer to perform doping treatment to obtain a second source and drain layer.

In this embodiment, step S27 may include steps S271-S272, which will be described together below:

When the source and drain layers 27 are formed on the P-type silicon wafer 21, the source and drain layers 27 need to be respectively provided for the N well 22 and the P well, that is, the sources of the N well 22 and the P well are respectively formed through two ion doping processes. Drain layer 27 . Among them, the ion doping can be realized by means of ion implanter or ion bombardment.

Specifically, the second P-type ions are implanted into the N well 22 for doping treatment. First, by setting a photoresist, the photoresist is patterned and then the source and drain (S/D) regions of the PMOS device and the NMOS device are exposed. The body contact region is then doped with photoresist as a mask to block the P-type ion doping. After the P-type ion doping is completed, the photoresist is removed to obtain a first source-drain layer 271 , wherein the first source-drain layer 271 is disposed in the N-well 22 and disposed in the N-well 22 and the low-temperature gate dielectric layer 25 In between, the first source and drain layers 271 are also distributed on both sides of the gate layer 26 .

Set the photoresist again, implant N-type ions into the P-type silicon wafer 21 for doping treatment, define the source-drain (S/D) region of the NMOS device and the body contact region of the PMOS device, and obtain the second source-drain region. Layer 272, wherein the second source and drain layers 272 are formed in the P-type silicon wafer 21 and disposed between the P-type silicon wafer 21 and the low temperature gate dielectric layer 25, and the second source and drain layers 272 are also distributed on the gate Both sides of layer 26 .

S28: A low-temperature passivation layer is provided on the low-temperature gate dielectric layer and the gate layer.

S281 : sequentially depositing silicon nitride and silicon oxide on the low-temperature isolation layer, the gate layer and the low-temperature gate dielectric layer, and performing rapid thermal annealing on the silicon nitride and silicon oxide to obtain a low-temperature passivation layer, wherein the heating temperature is less than or equal to 600°C.

S282 : patterning the low temperature passivation layer to obtain contact holes to expose the gate electrode layer, the first source and drain layers and the second source and drain layers.

In this embodiment, step S28 may include steps S281 to S282, which will be described together below:

On the low-temperature isolation layer 24, the low-temperature gate dielectric layer 25 and the gate layer 26, silicon nitride and silicon oxide are sequentially deposited as the low-temperature passivation layer material. It is oxidized during the process and protects the device from external moisture and other influences.

After the low temperature passivation layer material is deposited, the P-type silicon wafer 21 is heated to activate the low temperature passivation layer material, and the activation process may be rapid thermal annealing at a temperature not exceeding 600° C., or annealing through a heating stage.

After the low temperature passivation layer 28 is obtained, patterning is performed on the low temperature passivation layer 28 to form contact holes and islands on both sides of the contact holes, and the gate layer 26 and the first source and drain layers 271 are exposed in the contact holes. and the second source and drain layers 272 .

S29 : disposing a metal layer on the low temperature passivation layer, the gate layer and the source and drain layers, and the metal layer connects the gate layer and the source and drain layers.

S291: depositing metal on the low-temperature passivation layer and the contact hole, and patterning the metal.

S292: Perform synthesis gas annealing treatment on the metal layer.

In this embodiment, step S29 may include steps S291 to S292, which will be described together below:

A metal layer material is deposited in the low temperature passivation layer 28 and the contact holes, and the metal material is patterned to form a metal layer 29. The metal layer 29 is disposed on the low temperature passivation layer 28, the gate layer 26 and the source and drain layers 27, and is connected with The low-temperature gate dielectric layers 25 in the two islands are connected, and the metal layer material is patterned into connecting lines and test pads. The metal layer material may be a mixture of silicon and aluminum, for example, the metal layer material is a mixture of aluminum and silicon, silicon (Si) accounts for 1% in the metal layer material, and the thickness of the metal layer 29 is 700 nm. Patterning the metal layer 29 by annealing with a forming gas can improve the contact between aluminum and silicon.

On the basis of the above embodiments, please refer to FIG. 5 and FIG. 6 together. FIG. 5 is a schematic flowchart of another embodiment of a method for manufacturing a thin film transistor of the present application, and FIG. 6 is another implementation of a thin film transistor of the present application. Example structure diagram. In the low temperature PMOS process, the manufacturing method of the thin film transistor 300 may specifically include the following steps:

S31: Prepare an N-type silicon wafer.

In the low temperature PMOS process, the silicon wafer 31 is an N-type silicon wafer 31, so it is not necessary to form an N well and a P field.

S32: A low temperature isolation layer is arranged on the silicon wafer.

A low temperature isolation layer 32 is provided on the N-type silicon wafer 31 to define active devices.

S33: Disposing a bulk doping region on the silicon wafer, wherein the bulk doping region is disposed on the side of the silicon wafer facing the low temperature isolation layer.

In the low temperature PMOS process, N-type doping is performed on the body contact region, which is similar to the source-drain (S/D) doping of the NMOS in the low temperature CMOS process in the above embodiment. In this embodiment, the N-type silicon wafer 31 is patterned to obtain the first body doped region 33 , wherein the first body doped region 33 is disposed on the side of the N-type silicon wafer 31 facing the low temperature isolation layer 32 .

S34: thermally annealing the bulk doped region, wherein the heating temperature is 600°C.

After the bulk doped region 33 is formed, the N-type silicon wafer 31 is subjected to thermal annealing treatment, wherein the temperature of the thermal annealing treatment is greater than 600°C.

S35: A low-temperature gate dielectric layer and a gate layer are sequentially arranged on the silicon wafer.

S351: Disposing a low temperature gate dielectric layer on the silicon wafer and the low temperature isolation layer.

S352 : depositing gate metal on the low-temperature gate dielectric layer, and performing dry etching processing on the gate metal to form a gate layer by patterning.

In this embodiment, step S35 may include steps S351-S352, which will be described together below:

A low-temperature gate dielectric layer 34 is arranged on the N-type silicon wafer 31 and the low-temperature isolation layer 32. Similar to the above-mentioned low-temperature CMOS process, gate metal is deposited on the low-temperature gate dielectric layer 34. The resist pattern is transferred onto the metal layer 38 , and then dry etching is performed to pattern the gate layer 35 .

S36: Disposing source and drain layers in the silicon wafer.

The N-type silicon wafer 31 is implanted with third P-type ions for doping treatment, which is similar to the source-drain (S/D) doping process of the PMOS device in the above-mentioned low-temperature CMOS process, exposing the source-drain (S/D) region Using a P-type ion implanter or ion bombardment, a third source-drain layer 36 is obtained, wherein the third source-drain layer 36 is formed in the N-type silicon wafer 31 and disposed on the low-temperature gate dielectric layer 34 and the N-type silicon wafer between 31.

S37: A low-temperature passivation layer is provided on the low-temperature gate dielectric layer and the gate layer.

Silicon nitride and silicon oxide are sequentially deposited on the gate layer 35 and the low temperature gate dielectric layer 34 to obtain a low temperature passivation layer 37 .

S38 : disposing a metal layer on the low-temperature passivation layer, the gate layer and the source and drain layers, and the metal layer connects the gate layer and the source and drain layers.

Similar to the above-mentioned low temperature CMOS process, a metal layer material is provided on the low temperature passivation layer 37 , the gate layer 35 and the source and drain layers 36 , and the metal layer 38 is obtained after curing.

On the basis of the above-mentioned embodiments, please refer to FIG. 7 and FIG. 8 together. FIG. 7 is a schematic flowchart of another embodiment of a method for manufacturing a thin film transistor of the present application, and FIG. 8 is another implementation of a thin film transistor of the present application. Example structure diagram. In the low temperature NMOS process, the manufacturing method of the thin film transistor 400 may specifically include the following steps:

S41: Prepare a P-type silicon wafer.

In the low temperature NMOS process, the silicon wafer 41 is a P-type silicon wafer 41 .

S42: A low temperature isolation layer is arranged on the silicon wafer.

S43: Disposing a bulk doping region on the silicon wafer, wherein the bulk doping region is disposed on the side of the silicon wafer facing the low temperature isolation layer.

Different from the low temperature PMOS process, the body region of the low temperature NMOS is doped with a P-type dopant, that is, a fourth P-type ion is implanted on the P-type silicon wafer 41 to perform bulk doping treatment to obtain the second body doping region 43 , wherein The second body doped region 43 is disposed on the side of the P-type silicon wafer 41 facing the low temperature isolation layer 42 .

S44: thermally annealing the bulk doped region, wherein the heating temperature is greater than 600°C.

S45: A low-temperature gate dielectric layer and a gate layer are sequentially arranged on the silicon wafer.

S451 : disposing a low temperature gate dielectric layer on the silicon wafer and the low temperature isolation layer.

S452 : depositing gate metal on the low-temperature gate dielectric layer, and performing dry etching processing on the gate metal to form a gate layer by patterning.

S46: Disposing source and drain layers in the silicon wafer.

Different from the low temperature PMOS process, the source and drain layers 46 are N-type doped, that is, the P-type silicon wafer 41 is patterned to obtain the fourth source and drain layers 46, wherein the fourth source and drain layers 46 are formed in the P-type In the silicon wafer 41 , and disposed between the low temperature gate dielectric layer 44 and the P-type silicon wafer 41 .

S47: A low-temperature passivation layer is provided on the low-temperature gate dielectric layer and the gate layer.

Silicon nitride and silicon oxide are sequentially deposited on the gate layer 45 and the low-temperature gate dielectric layer 44 , and thermal annealing is performed on the silicon nitride and the silicon oxide to activate the N-type dopant to obtain a low-temperature passivation layer 47 .

S48: A metal layer is provided on the low-temperature passivation layer, the gate layer and the source and drain layers, and the metal layer connects the gate layer and the source and drain layers.

Similar to the above-mentioned low temperature CMOS process, a metal material is provided on the low temperature passivation layer 47 , the gate layer 45 and the source and drain layers 46 , and the metal layer 48 is obtained after curing.

The present application provides a low temperature metal oxide semiconductor process for high resolution displays, a commercial TFT backplane can handle FPD with PPI<1000, an expensive silicon chip process can handle small size FPDS with PPI>1000, no A cost-effective FPD industry compatible process for manufacturing ultra-high PPI displays. The present application reduces the manufacturing cost of the silicon-based display panel, shortens the production cost and processing time, and fills the gap between the IC process and the TFT panel technology.

The technical solutions disclosed in this application can realize low-temperature, low-cost, and industrial-compatible silicon MOSFET fabrication processes, ie, low-temperature CMOS process, low-temperature PMOS process, and low-temperature NMOS process. Through these three low-temperature processes, thin-film transistors can be produced at low cost and in large areas, and then high-resolution virtual reality/augmented reality devices including micro OLED projectors can be fabricated, making silicon-based liquid crystal displays possible.

The present application provides a method for manufacturing a thin film transistor, which includes preparing a silicon wafer; disposing a low-temperature isolation layer on the silicon wafer; disposing a low-temperature gate dielectric layer and a gate layer on the silicon wafer in sequence; disposing a source in the silicon wafer drain layer; a low temperature passivation layer is arranged on the low temperature gate dielectric layer and the gate layer; a metal layer is arranged on the low temperature passivation layer, the gate layer and the source and drain layers, and the metal layer connects the gate layer and the source and drain Floor. By arranging a low-temperature isolation layer, a low-temperature gate dielectric layer, a gate layer, a source-drain layer, a low-temperature passivation layer and a metal layer on the silicon wafer in a low-temperature state, the manufacturing cost can be reduced and the process of manufacturing high-resolution displays can be improved. success rate of thin-film transistors.

Corresponding to the above method, the present application proposes a thin film transistor. Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of an embodiment of a thin film transistor of the present application. The thin film transistor 100 disclosed in the present application includes a silicon wafer 11 , a low temperature isolation layer 12 , a low temperature gate dielectric layer 13 , a gate layer 14 , a source and drain layer 15 , a low temperature passivation layer 16 and a metal layer 17 .

Specifically, the low temperature isolation layer 12 is formed on one side of the silicon wafer 11; the low temperature gate dielectric layer 13 is formed on the side of the silicon wafer 11 close to the low temperature isolation layer 12; the gate layer 14 is formed on the low temperature gate dielectric layer 13 the side away from the silicon wafer 11; the source and drain layers 15 are formed in the silicon wafer 11; the low temperature passivation layer 16 is formed on the low temperature gate dielectric layer 13 and the gate layer 14; the metal layer 17 is formed on the low temperature On the passivation layer 16 , the gate layer 14 and the source and drain layers 15 , the gate layer 14 and the source and drain layers 15 are connected.

The present application provides a thin film transistor 100, which can reduce manufacturing costs and improve the success rate of manufacturing thin film transistors in high-resolution displays.

Corresponding to the above-mentioned thin film transistor 100 , the present application proposes a display panel 500 . Please refer to FIG. 9 , which is a schematic structural diagram of an embodiment of a display panel of the present application. The display panel 500 disclosed in the present application includes a thin film transistor 51 . The specific implementation of the thin film transistor 51 is similar to the above, and will not be repeated here.

The present application provides a display panel 500, which can reduce the manufacturing cost and improve the success rate of manufacturing thin film transistors in high-resolution displays.

The above is only the preferred embodiment of the present invention, and does not limit the present invention in any form. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, implements the above implementation according to the technical essence of the present invention. Any simple modifications, equivalent changes and modifications made in the examples still fall within the scope of the technical solutions of the present invention.

Claims (10)

1. A method for manufacturing a thin film transistor, wherein the method comprises: prepare silicon wafers; A low temperature isolation layer is arranged on the silicon wafer; A low-temperature gate dielectric layer and a gate layer are sequentially arranged on the silicon wafer; Disposing source and drain layers in the silicon wafer; A low-temperature passivation layer is provided on the low-temperature gate dielectric layer and the gate layer; A metal layer is provided on the low-temperature passivation layer, the gate layer and the source and drain layers, and the metal layer connects the gate layer and the source and drain layers. 2 . The method according to claim 1 , wherein the silicon wafer is a P-type silicon wafer, and before the step of disposing a low temperature isolation layer on the silicon wafer, the method comprises: 3 . disposing a first silicon dioxide layer on the P-type silicon wafer; Disposing photoresist on the first silicon dioxide layer and performing patterning treatment, implanting first N-type ions to form an N-well between the P-type silicon wafer and the first silicon dioxide layer, removing the photoresist; Disposing the photoresist on the first silicon dioxide layer and performing patterning treatment, and implanting first P-type ions to form a P field between the P-type silicon wafer and the first silicon dioxide layer , removing the photoresist and the first silicon dioxide layer; The step of disposing a low temperature isolation layer on the silicon wafer includes: Deposition silicon dioxide on the P-type silicon wafer, patterning the silicon dioxide layer to obtain a second silicon dioxide layer, and patterning the second silicon dioxide layer to obtain the low temperature isolation Floor. 3. The method according to claim 2, wherein the step of sequentially disposing a low-temperature gate dielectric layer and a gate layer on the silicon wafer comprises: depositing a gate dielectric on the P-type silicon wafer, and patterning the gate dielectric to form the low temperature gate dielectric layer; depositing gate metal on the low temperature gate dielectric layer to form the gate layer; The step of disposing the source and drain layers in the silicon wafer includes: implanting second P-type ions into the N well for doping treatment to obtain a first source and drain layer; N-type ions are implanted into the P-type silicon wafer for doping treatment to obtain a second source and drain layer. 4. The method according to claim 3, wherein the step of disposing a low-temperature passivation layer on the low-temperature gate dielectric layer and the gate layer comprises: Silicon nitride and silicon oxide are sequentially deposited on the low temperature isolation layer, the gate layer and the low temperature gate dielectric layer, and the silicon nitride and the silicon oxide are subjected to rapid thermal annealing to obtain the low temperature Passivation layer, wherein the heating temperature is less than or equal to 600°C; patterning the low temperature passivation layer to obtain contact holes to expose the gate electrode layer, the first source and drain layers and the second source and drain layers; A metal layer is provided on the low temperature passivation layer, the gate layer and the source and drain layers, and the step of connecting the metal layer with the gate layer and the source and drain layers includes: depositing metal on the low temperature passivation layer and the contact hole, and patterning the metal; A forming gas annealing process is performed on the metal layer. 5. The method according to claim 1, wherein before the step of sequentially disposing a low-temperature gate dielectric layer and a gate layer on the silicon wafer, it comprises: Disposing a body doping region on the silicon wafer, wherein the body doping region is disposed on the side of the silicon wafer facing the low temperature isolation layer; thermally annealing the bulk doped region, wherein the heating temperature is greater than 600°C; The step of sequentially disposing a low-temperature gate dielectric layer and a gate layer on the silicon wafer includes: disposing the low temperature gate dielectric layer on the silicon wafer and the low temperature isolation layer; depositing gate metal on the low temperature gate dielectric layer, and performing dry etching on the gate metal to form the gate layer by patterning; The step of disposing a low-temperature passivation layer on the low-temperature gate dielectric layer and the gate layer includes: Silicon nitride and silicon oxide are sequentially deposited on the gate layer and the low-temperature gate dielectric layer to obtain the low-temperature passivation layer. 6 . The method according to claim 5 , wherein the silicon wafer is an N-type silicon wafer, and a body doped region is provided on the silicon wafer, wherein the body doped region is arranged on the silicon wafer. 7 . The step toward the side of the low temperature isolation layer includes: performing a patterning process on the N-type silicon wafer to obtain a first body doping region, wherein the first body doping region is disposed on the side of the N-type silicon wafer facing the low temperature isolation layer; The step of disposing the low temperature gate dielectric layer on the silicon wafer and the low temperature isolation layer includes: Disposing the low temperature gate dielectric layer on the N-type silicon wafer and the low temperature isolation layer; The step of disposing the source and drain layers in the silicon wafer includes: The N-type silicon wafer is implanted with third P-type ions for doping treatment to obtain a third source-drain layer, wherein the third source-drain layer is formed in the N-type silicon wafer. 7 . The method according to claim 5 , wherein the silicon wafer is a P-type silicon wafer, and a body doped region is provided on the silicon wafer, wherein the body doped region is provided on the silicon wafer. 8 . The step toward the side of the low temperature isolation layer includes: A fourth P-type ion is implanted on the P-type silicon wafer to perform bulk doping treatment to obtain a second bulk doping region, wherein the second bulk doping region is disposed on the P-type silicon wafer and faces the low temperature isolation one side of the layer; The step of disposing the source and drain layers in the silicon wafer includes: N-type ions are implanted into the P-type silicon wafer to perform doping treatment to obtain a fourth source and drain layer, wherein the fourth source and drain layer is formed in the silicon wafer. 8. The method according to claim 7, wherein the step of disposing a low temperature passivation layer on the low temperature gate dielectric layer and the gate layer comprises: Silicon nitride and silicon oxide are sequentially deposited on the gate layer and the low-temperature gate dielectric layer, and thermal annealing is performed on the silicon nitride and the silicon oxide to obtain the low-temperature passivation layer. 9. A thin film transistor, wherein the thin film transistor comprises: a silicon wafer and a low temperature isolation layer formed on one side of the silicon wafer; a low temperature gate dielectric layer, formed on the side of the silicon wafer close to the low temperature isolation layer; a gate layer, formed on the side of the low-temperature gate dielectric layer away from the silicon wafer; source and drain layers, formed in the silicon wafer; a low-temperature passivation layer, formed on the low-temperature gate dielectric layer and the gate layer; A metal layer is formed on the low temperature passivation layer, the gate layer and the source and drain layers, and connects the gate layer and the source and drain layers. 10. A display panel, wherein the display panel comprises the thin film transistor of claim 9.

Images