CN110738594B

CN110738594B - FPGA-based onboard electronic instrument picture generation method

Info

Publication number: CN110738594B
Application number: CN201911194261.0A
Authority: CN
Inventors: 王昱煜; 苗莉; 陶栋琦; 苗蔚; 丁露
Original assignee: Suzhou Changfeng Aviation Electronics Co Ltd
Current assignee: Suzhou Changfeng Aviation Electronics Co Ltd
Priority date: 2019-11-28
Filing date: 2019-11-28
Publication date: 2022-09-20
Anticipated expiration: 2039-11-28
Also published as: CN110738594A

Abstract

The invention discloses an onboard electronic instrument picture generating method based on FPGA, which takes FPGA as a core processor, utilizes rich hardware logic resources and RAM storage resources, designs 10 layers in an FPGA chip, can independently set a bmp bitmap as an image of the current layer for each layer, realizes the rotation and translation operations of the image of the current layer according to the requirement of a drawing instruction, and finally superposes the 10 layers in sequence, thereby realizing the onboard electronic instrument picture. The invention fully utilizes the advantages of FPGA parallel computation, can improve the generation efficiency of graphic pictures, improves the integration level of the system, and is beneficial to realizing the requirements of miniaturization and low power consumption of the system.

Description

FPGA-based onboard electronic instrument image generation method

Technical Field

The invention relates to a method for generating an image of an airborne electronic instrument based on an FPGA (field programmable gate array), belonging to the technical field of image display of the airborne electronic instrument.

Background

In modern airborne integrated display systems, electronic liquid crystal instruments are increasingly widely used. For this application scenario, although the conventional CPU + GPU architecture display can generate high-resolution and high-quality graphics images, it has the problems of large power consumption, high cost, complex system, and the like.

Especially, for some small-sized electronic instruments, the requirements on low cost, small volume, low power consumption and the like are strict, and the requirements of design indexes are difficult to meet in the aspects of adopting the traditional CPU + GPU architecture.

Disclosure of Invention

The invention aims to solve the defects of the prior art, and provides a method for generating an onboard electronic instrument picture based on an FPGA (field programmable gate array) aiming at the problems of high power consumption, high cost and complex system of a traditional CPU + GPU (graphics processing unit) architecture display.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

the FPGA-based onboard electronic instrument picture generation method comprises the following steps:

the design of an FPGA framework is carried out,

designing ten layers and an image superposition unit in the FPGA by using on-chip logic resources and RAM resources of the FPGA, wherein the ID numbers of the ten layers are sequentially 0-9 in a front-back sequence, and each layer comprises an instruction buffer area, an instruction acquisition unit, an image storage ROM, an image rotation unit, an image translation unit and two groups of image cache RAMs;

the drawing instruction is analyzed, and the drawing instruction is analyzed,

analyzing a mapping instruction input at the front end by using logic resources in the FPGA chip, distinguishing the analyzed instruction according to the rotation and translation functions, and caching the instruction into instruction buffer areas of all layers;

the picture of each layer is generated,

the instruction acquisition unit is used for performing instruction acquisition operation from an instruction buffer area of a current layer to acquire a rotation angle and a translation coordinate of an image of the current layer, transmitting the rotation angle parameter to a subsequent image rotation unit and transmitting the translation coordinate to a subsequent image translation unit;

the image storage ROM is used for storing specific images of the current layer, the images are stored in the format of a bmp bitmap converted file, and corresponding image pictures are output from the image storage ROM by taking a video time sequence generated by the post-stage image superposition unit as a reference;

the image rotation unit receives a rotation instruction of the front end and rotates the image output from the image storage ROM by a specific angle according to the instruction requirement;

the image translation unit receives a translation instruction at the front end and translates the image which is output by the image rotation unit and rotated according to a specific angle into corresponding coordinates according to the instruction requirement;

the image cache RAM is used for timing sequence adjustment and image temporary storage, the RAM for executing reading operation outputs the last frame of image picture temporarily stored in the RAM according to the timing sequence of the later-stage image superposition unit; the RAM for executing the writing operation temporarily stores the processed current frame image into the RAM;

the image layers are superposed with each other,

the image superposition unit outputs a set of uniform time sequence to the image cache RAM of each layer, the pictures of each layer are uniformly output from the image cache RAM according to the time sequence,

and image pictures output by each layer are collected to an image superposition unit, and the image superposition unit superposes 10 layers in total of 0-9 in sequence in a transparent superposition mode to output a final complete image picture.

The invention has the following beneficial effects:

1. the high-quality dynamic electronic instrument picture can be output through the FPGA.

2. The electronic instrument picture with small resolution can reach 512 multiplied by 512@60Hz and 256 gray levels.

3. The output picture has high real-time performance. From the reception of the command to the final output of the picture, the data is delayed by one field sync period.

Drawings

FIG. 1 is a schematic diagram of a schematic framework of the method for generating an image of an on-board electronic instrument based on an FPGA.

Detailed Description

The invention provides an onboard electronic instrument image generation method based on an FPGA. The technical solution of the present invention is described in detail below with reference to the accompanying drawings so that it can be more easily understood and appreciated.

The method for generating the airborne electronic instrument picture based on the FPGA is mainly used for small-size airborne electronic instruments, static image mapping is achieved by using storage resources on an FPGA chip, rotation, translation and superposition operations of static images are achieved by using logic resources on the FPGA chip, and common small-size airborne electronic instrument picture display is achieved by receiving corresponding airborne picture drawing instructions.

Fig. 1 is a schematic diagram of the principle framework of the method.

Firstly, taking a K7 series FPGA of Xilinx company as core hardware, carrying out FPGA frame design, designing ten layers and an image superposition unit in the FPGA by utilizing on-chip logic resources and RAM resources, wherein the ten layers correspond to respective ID numbers and are sequentially 0-9 in sequence from front to back, each layer comprises an instruction buffer area, an instruction acquisition unit, an image storage ROM, an image rotation unit, an image translation unit and two groups of image cache RAMs, and the image superposition unit is used for providing time sequence attributes for each layer and carrying out transparent superposition display on output images of each layer.

And (5) analyzing the drawing instruction.

And analyzing the mapping instruction input at the front end by using logic resources in the FPGA chip, distinguishing the analyzed instruction according to the rotation and translation functions, and caching the instruction into an instruction buffer area of each layer at the later stage. The instruction buffer is implemented by a set of FPGA on-chip dual-port RAMs.

And generating pictures of each layer.

And (3) designing 10 layers in total by utilizing on-chip logic resources and RAM resources in the FPGA, wherein the ID numbers corresponding to the layers are 0-9 in sequence. Each image layer comprises an instruction acquisition unit, an image storage ROM, an image rotation unit, an image translation unit and two groups of image cache RAMs.

the image storage ROM is used for storing specific images of the current layer, and the images are stored in the format of a multi-mif file after bmp bitmap conversion. The corresponding image picture is output from the ROM with reference to the video timing generated by the latter-stage image superimposing unit.

The image rotation unit receives a rotation command from the front end and rotates the image outputted from the image storage ROM by a specified angle according to the command.

The image translation unit receives a translation instruction at the front end, and translates the image which is output from the image rotation unit and rotated according to a specific angle according to the instruction requirement by corresponding coordinates.

The image cache RAM is used for timing adjustment and image temporary storage. And the current layer image of which the front end is processed by the image rotation unit and the image translation unit writes the cache into an image cache RAM.

The image cache RAM has A, B groups, and works in ping-pong operation mode, i.e. group A executes write-read-write- … operation in turn, and group B executes read-write-read- … operation in turn. The RAM for executing the reading operation outputs the last frame of image picture temporarily stored in the RAM according to the time sequence of the later-stage image superposition unit; the RAM for executing the writing operation temporarily stores the processed current frame image into the RAM.

And (6) overlapping the layers.

The image superposition unit outputs a set of uniform time sequence to the image cache RAM of each layer, and the images of each layer are uniformly output from the image cache RAM according to the time sequence. And image pictures output by each layer are collected to an image superposition unit, and the image superposition unit superposes 10 layers in total of 0-9 in sequence in a transparent superposition mode to output a final complete image picture.

Through the description, the method for generating the images of the airborne electronic instrument based on the FPGA makes full use of the advantages of FPGA parallel computation, can improve the generation efficiency of the images, improves the integration level of the system, and is favorable for realizing the requirements of miniaturization and low power consumption of the system.

The technical solutions of the present invention are fully described above, it should be noted that the specific embodiments of the present invention are not limited by the above description, and all technical solutions formed by equivalent or equivalent changes in structure, method, or function according to the spirit of the present invention by those skilled in the art are within the scope of the present invention.

Claims

1. The method for generating the onboard electronic instrument picture based on the FPGA is characterized by comprising the following steps of:

the design of an FPGA framework is carried out,

designing ten layers and an image superposition unit by using on-chip logic resources and RAM resources in the FPGA, wherein the ID numbers of the ten layers are sequentially 0-9 according to the front and back, and each layer comprises an instruction buffer area, an instruction acquisition unit, an image storage ROM, an image rotation unit, an image translation unit and two groups of image cache RAMs;

the drawing instruction is analyzed, and the drawing instruction is analyzed,

the picture of each layer is generated,

the image translation unit receives a translation instruction at the front end and translates the image which is output from the image rotation unit and rotated according to a specific angle into corresponding coordinates according to the instruction requirement;

the image layers are superposed with each other,

and image pictures output by each layer are collected to the image superposition unit, and the image superposition unit superposes 10 layers in total from 0 to 9 in a transparent superposition mode to output the final complete image picture.