CN110719076B - semiconductor amplifier - Google Patents
semiconductor amplifier Download PDFInfo
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- CN110719076B CN110719076B CN201910620156.2A CN201910620156A CN110719076B CN 110719076 B CN110719076 B CN 110719076B CN 201910620156 A CN201910620156 A CN 201910620156A CN 110719076 B CN110719076 B CN 110719076B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000003990 capacitor Substances 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 49
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Amplifiers (AREA)
- Microwave Amplifiers (AREA)
Abstract
A semiconductor amplifier. The semiconductor amplifier (1) includes transistors (21 a) and (21 b) which are loaded side by side on a bottom plate (2) in a space in a package (6); a matching circuit (22 a) mounted between the transistors (21 a, 21 b) on the base plate (2); a matching circuit (22 b) mounted on the opposite side of the transistor (21 b) from the transistor (21 a) on the bottom plate (2); an input Terminal (TIN) mounted on one side of the wiring substrate (3); an output terminal (TOUT) mounted on the other side of the wiring substrate (3); grid bias terminal (T) 1G ) Sum (T) 2G ) And drain bias terminal (T) 1D ) Sum (T) 2D ) An input terminal (T) of the wiring substrate (3) is mounted at this position IN ) And output terminal (T) OUT ) And the transistor (21 a), the matching circuit (22 a), the transistor (21 b) and the matching circuit (22 b) are linearly disposed at the input terminal (T IN ) And output terminal (T) OUT ) Between them.
Description
Technical Field
The present invention relates to a semiconductor amplifier.
Background
As an apparatus for amplifying a high-frequency signal, an apparatus in which a plurality of metallized surfaces are formed on an insulating substrate, one transistor chip is placed on one metallized surface, and an input matching circuit is placed on another grounded metallized surface on the insulating substrate is known (japanese unexamined patent publication No. h 5-243871). In this device, an input terminal is mounted on one side of an insulating substrate, and an output terminal is mounted on the other side of the insulating substrate.
Further, as a configuration of a high-frequency amplifier in which two transistors are connected in multiple stages, a configuration in which two transistors and a matching circuit are placed on a circuit board in a package is known (japanese unexamined patent publication No. 2016-19068). In this amplifier, a terminal for inputting an input signal to the gate of the first stage transistor via the matching circuit, a terminal for supplying a bias to the gate of the first stage transistor via the matching circuit, and a terminal for supplying a bias to the gate of the second stage transistor via the matching circuit are mounted on a first side of the circuit board in this order, and a terminal for supplying a bias to the drain of the first stage transistor via the matching circuit, a terminal for supplying a bias to the drain of the second stage transistor via the matching circuit, and a terminal for outputting an output signal from the drain of the second stage transistor via the matching circuit are mounted on a second side opposite to the first side of the circuit board in this order.
In the high-frequency amplifier disclosed in japanese unexamined patent publication No.2016-19068, bias interference occurs because terminals for supplying bias to two transistors are adjacent to each other. Therefore, there are cases in which the output signal cannot be stably generated. Therefore, there is a need for a semiconductor amplifier that generates a stable output signal by preventing bias disturbance in a multi-stage transistor.
Disclosure of Invention
A semiconductor amplifier according to an aspect of the present invention includes: a package body including a metal base plate; an insulating circuit board placed on the bottom plate and including a first opening; an insulating sidewall portion placed on a peripheral portion on the circuit board and including a second opening that is larger than and surrounds the first opening, and a cover portion placed on the sidewall portion and sealing a space formed by the first opening and the second opening, the first and second transistors being loaded side by side on a bottom plate in the space; a first matching circuit which is loaded between the first transistor and the second transistor on the bottom plate in the space, the first matching circuit being connected between the drain of the first transistor and the gate of the second transistor; a second matching circuit mounted near the second transistor in the space on the bottom plate, the second matching circuit being located on an opposite side of the second transistor from the first transistor, the second matching circuit being connected to a drain of the second transistor; an input terminal mounted at the center of one side of the circuit board and connected to the gate of the first transistor; an output terminal mounted at the center of one side opposite to the other side of the circuit board and connected to the drain of the second transistor via a second matching circuit; first and second gate bias terminals mounted at a position of one of an input terminal or an output terminal sandwiching a circuit board therebetween, the first and second gate bias terminals being connected to a gate of the first transistor and a gate of the second transistor, respectively; and first and second drain bias terminals mounted at a position of the other one of the input terminal and the output terminal sandwiching the circuit board therebetween, the first and second drain bias terminals being connected to the drain of the first transistor and the drain of the second transistor, respectively, and the first transistor, the first matching circuit, the second transistor, and the second matching circuit being placed linearly between the input terminal and the output terminal.
Drawings
Fig. 1 is a perspective view of a semiconductor amplifier according to an embodiment.
Fig. 2 is a rear view of a chassis and a circuit board constituting a package of the semiconductor amplifier of fig. 1.
Fig. 3 is a plan view of a base plate and a circuit board constituting a package of the semiconductor amplifier of fig. 1.
Fig. 4 is a plan view of a side wall portion of a package constituting the semiconductor amplifier of fig. 1.
Fig. 5 is a plan view illustrating a state in which a cover part is removed from the semiconductor amplifier of fig. 1.
Fig. 6 is a plan view illustrating a loading state of circuit elements in the semiconductor amplifier of fig. 1.
Fig. 7 is a circuit diagram illustrating a circuit configuration of the semiconductor amplifier of fig. 1.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Note that in the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted.
[ configuration of semiconductor Amplifier ]
Fig. 1 is a perspective view of a semiconductor amplifier according to an embodiment, fig. 2 is a rear view of a chassis and a circuit board constituting a package of the semiconductor amplifier, fig. 3 is a plan view of the chassis and the circuit board constituting the package, fig. 4 is a plan view of a side wall portion constituting the package, and fig. 5 is a plan view illustrating a state in which a cover portion is removed from the semiconductor amplifier. The semiconductor amplifier 1 according to the embodiment is an amplifier for a frequency band of an X-band such as 8.5 to 10.1GHz, and is incorporated in a device such as a radar.
As illustrated in fig. 1, the semiconductor amplifier 1 is configured such that a circuit element is accommodated in a package 6 having a four-layer structure of a base plate 2 made of metal (e.g., copper), a wiring substrate 3, a side wall portion 4, and a lid portion 5. As illustrated in fig. 2 and 3, the wiring substrate 3 is a rectangular flat plate member made of an insulating material such as alumina, and includes a substantially rectangular opening 7 in the center thereof. The wiring substrate 3 is bonded to the base plate 2 in a state in which the opening 7 is covered by the base plate 2. The side wall portion 4 is made of a rectangular annular insulating material such as alumina and includes an opening 8 larger than the opening 7 illustrated in fig. 4, which is bonded to a peripheral portion of the surface 10 on the opposite side of the wiring substrate 3 of the base plate 2 to surround the entire opening 7 in the opening 8 (fig. 5). A seal ring made of metal is mounted on the side of the side wall portion 4 opposite to the wiring substrate 3. The cover portion 5 is a rectangular flat plate member made of an insulating material (for example, alumina) and is fixed to the seal ring while covering the opening 8. With this structure, that is, a structure in which the wiring substrate 3, the side wall portion 4, and the lid portion 5 are placed on the base plate 2 in this order, the space on the base plate 2 formed by the opening 7 and the opening 8 is sealed.
The size of the package 6 is not limited to a specific size, and for example, the horizontal size thereof is 8.7mm×8.3mm, the thickness of the bottom plate 2 is about 0.5mm, and the thickness of the combination of the wiring substrate 3 and the side wall portion 4 is about 0.8mm.
Further, on the bottom surface of the package 6, i.e., on the back surface 11 of the wiring substrate 3, a conductive input terminal T extending perpendicularly to the first side 3a IN Mounted at the centre of the side 3a. In addition, two gate bias terminals T 1G And T 2G With the input terminal T sandwiched therebetween IN Mounted in both ends of the first side 3a of the back surface 11. Also, on the back surface 11, a conductive output terminal T extending vertically to the second side 3b OUT Is mounted at and connected withAt the centre of the opposite side 3b of the first side 3a. Further, two drain bias terminals T 1D And T 2D With the output terminal T sandwiched therebetween OUT Mounted in both ends of the second side 3b of the back surface 11. Input terminal T IN Is a terminal for receiving an input signal from the outside, and an output terminal T OUT Is a terminal for outputting an amplified signal to the outside, two gate bias terminals T 1G And T 2G Are terminals for supplying gate bias to two transistors in the package 6, and two drain bias terminals T 1D And T 2D Is a terminal for supplying drain bias to these transistors.
Further, in the bottom plate 2, a ground terminal T extending perpendicular to the sides 3c and 3d GND Formed in a central portion of each of the third side 3c and the fourth side 3d connecting both sides 3a and 3b of the wiring substrate 3. In addition, in the bottom plate 2, two protruding portions 9 protruding vertically on the side 3a form an input terminal T on the first side 3a IN And two gate bias terminals T 1G And T 2G Each of which is between. In addition, in the bottom plate 2, two protruding portions 9 protruding perpendicularly from the side 3b are also formed on the output terminal T on the second side 3b OUT And two drain bias terminals T 1D And T 2D Each of which is between. Ground terminal T GND Is a terminal for connecting the base plate 2 to the ground, and the protruding portion 9 is a connection member for electrically connecting the base plate 2 with the wiring portion on the wiring substrate 3.
Here, the configuration of the wiring substrate 3 will be described in more detail.
The opening 7 formed in the wiring substrate 3 includes a convex cutout portion 7a protruding toward the center portion of the third side 3c and a convex cutout portion 7b protruding toward the center portion of the fourth side 3 d. Further, in the surface 10 of the wiring substrate 3 on the side opposite to the base plate 2, a conductive wiring portion L is formed between the cutout portion 7a and the first side 3a 2G And a conductive wiring portion L is formed between the cutout portion 7a and the second side 3b 2D . Similarly, in the surface 10, the conductive wiring portion L 1G Formed between the cutout portion 7b and the first side 3a, and a conductive wiring portion L 1D Formed atBetween the cut-out 7b and the second side 3b. Wiring part L 2G 、L 2D 、L 1G And L 1D The gate bias terminals T are respectively connected to the metal via the metal embedded in the hollow 12 formed on the side surface of the wiring substrate 3 2G Drain bias terminal T 2D Gate bias terminal T 1G And a drain bias terminal T 1D And (5) electric connection. For example, when the circuit element is soldered to the wiring substrate 3, a solder fillet is formed in the hollow portion 12, and each wiring portion L 2G 、L 2D 、L 1G And L 1D Is connected to the gate bias terminal T 2G Drain bias terminal T 2D Gate bias terminal T 1G And a drain bias terminal T 1D 。
Further, in the surface 10, a linear conductive wiring portion L extending perpendicularly to the side 3a from the vicinity of the opening 7 to the front face of the side 3a is formed between the opening 7 and the center portion of the first side 3a IN . Further, in the surface 10, a linear conductive wiring portion L extending perpendicularly to the side 3b from the vicinity of the opening 7 to the front face of the side 3b is formed between the opening 7 and the center portion of the second side 3b OUT . These wiring portions L IN And L OUT Are electrically connected to the input terminals T via the via holes 13 penetrating the wiring substrate 3, respectively IN And an output terminal T OUT 。
Further, in the surface 10, between the opening 7 and the first side 3a, two wiring portions L are formed from the opening 7 to the side 3a GND . Also, in the surface 10, between the opening 7 and the second side 3b, two wiring portions L are formed from the opening 7 to the side 3b GND . Four wiring parts L GND Formed at the wiring part L 2G And a wiring part L IN Between and wiring part L 1G And a wiring part L IN Between and wiring part L 2D And a wiring part L OUT Between, and wiring part L 1D And a wiring part L OUT Between them. Wiring part L GND The base plate 2 is electrically connected via a metal embedded in a hollow portion 14 formed on the side surface of the wiring substrate 3 and the protruding portion 9, and the base plate 2 is electrically connected by a metal embedded in a hollow portion 15 formed on the inner wall of the opening 7 of the wiring substrate 3. Thus, the wiring portion L GND And (5) grounding. For example, when the circuit element is soldered to the wiring substrate 3, solder fillets are formed in the hollow portions 14 and 15, and the wiring portion L is connected GND And a base plate 2.
As described above, the seal ring is placed on the upper surface of the side wall portion 4. The seal ring is electrically connected to the base plate 2 via metal embedded through the hollow portion 16 formed on the outer side surface of the side wall portion 4 and the hollow portion 14 of the wiring substrate 3 and the protruding portion 9 (fig. 5). At the same time, the seal ring is inserted into the inner side surface of the side wall 4 and the wiring portion L GND The metal in the hollow 17 formed above is electrically connected to the base plate 2 (fig. 5). Therefore, the seal ring of the side wall portion 4 is grounded. For example, when the circuit element is soldered to the wiring substrate 3, solder fillets are formed in the hollow portions 16 and 17, and the seal ring and the base plate 2 are connected.
In the package 6 of the above-described structure, each circuit element is loaded in the space formed by the opening 7 and the opening 8. The loading form and circuit configuration of the circuit elements in the semiconductor amplifier 1 will be described below with reference to fig. 6 and 7. Fig. 6 is a plan view illustrating a loading state of circuit elements in the semiconductor amplifier 1, and fig. 7 is a circuit diagram illustrating a circuit configuration of the semiconductor amplifier 1. In the package 6 of the semiconductor amplifier 1, three bias resistance elements R11, R12, and R2; nine capacitors C1, C3, C21, C22, C41, C42, C61, C71 and C72; two-stage transistors 21a and 21b; and two matching circuits 22a and 22b are loaded. Among these, the transistor 21a in the front stage, the matching circuit 22a, the transistor 21b in the rear stage, and the matching circuit 22b are placed to be at the input terminal T on the bottom plate 2 in the package 6 IN And an output terminal T OUT Which are arranged linearly in this order.
The two stages of the transistors 21a and 21b are, for example, field effect transistors such as High Electron Mobility Transistors (HEMTs) mainly composed of GaN-based materials, and are arranged side by side on the bottom plate 2 inside the opening 7. The size of the transistor 21b is larger than that of the transistor 21a, and the size ratio of the transistor 21a and the transistor 21b is, for example, 1:5. the transistor 21a in the preceding stage is placed at the wiring portion L on the wiring substrate 3 at the edge of the opening 7 IN And its gate 23a passes throughThe bonding wire is electrically connected to the wiring portion L IN . The transistor 21b in the subsequent stage faces the wiring portion L OUT The side is placed apart from the transistor 21a, and in the center portion of the opening 7, a matching circuit 22a is sandwiched between the transistor 21b and the transistor 21 a.
Capacitors C1, C3, C21, C41, C61 and C71 are wiring portions L mounted on the back surface and wiring substrate 3 GND A die capacitor in a direct contact state. Capacitors C22, C42, and C72 are die capacitors loaded in a state where the back surface is in direct contact with the bottom plate 2 in the opening 7.
The resistance elements R11 and R12 are placed on the base plate 2 adjacent to the transistor 21a on the side 3d side of the wiring substrate 3, and are connected in series on the resistor chip. The resistance elements R11 and R12 are connected in series on a resistor chip having a plurality of electrodes on the surface to constitute a series circuit. The terminal of the series circuit on the side of the resistance element R11 is connected to the wiring portion L via the surface of the capacitor C22 placed on the bottom plate 2 by a bonding wire 1G . The terminal of the series circuit between the two resistance elements R11 and R12 is connected to the gate 23a of the transistor 21a by a bonding wire. Further, a terminal of the series circuit on the resistive element R12 side is connected to the surface of the capacitor C3 on the wiring substrate 3. Further, wiring part L 1G Is connected to the surface of the capacitor C21 on the wiring substrate 3 by a bonding wire. Wiring part L IN Is connected to the surface of the capacitor C1 on the wiring substrate 3 by a bonding wire. Furthermore, the coupling capacitor is connected to an input terminal T outside the package 6 IN 。
With such a configuration, the gate 23a of the transistor 21a can be biased from the gate bias terminal T via the resistance element R11 1G Is supplied with a gate bias and is also supplied from the input terminal T via a coupling capacitor IN Is supplied with an input signal. The gate 23a is grounded via the resistor R12 and the capacitor C3. Further, the gate bias terminal T 1G Is bypassed by capacitor C21 and capacitor C22 at high frequencies.
In the transistor 21b of the subsequent stage, the gate 23b is connected to the wiring portion L through the surface of the capacitor C42 through the resistive element R2 by a bonding wire 2G . Further, wiring part L 2G Is connected to the surface of the capacitor C41 on the wiring substrate 3 by a bonding wire. With this connection, the gate bias can be conducted from the gate bias terminal T via the resistive element R2 2G Is supplied to the gate electrode 23b. Also, the gate bias terminal T 2G Is bypassed by capacitors C41 and C42 at high frequencies.
In the transistor 21a of the preceding stage, the source is connected to the substrate 2 via a via hole (not shown). The drain 24a of the transistor 21a is connected to the wiring portion L via the surface electrode of the matching circuit 22a on the bottom plate 2 and the surface of the capacitor C72 by a bonding wire 1D . Further, wiring portion L 1D Is connected to the surface of the capacitor C71 on the wiring substrate 3 by a bonding wire. With this connection, the terminal T can be biased from the drain 1D A drain bias is supplied to drain 24a. Further, the drain bias terminal T 1D Is bypassed by capacitor C71 and capacitor C72 at high frequencies.
The matching circuit 22a is loaded between the two-stage transistors 21a and 21b on the bottom plate 2, and the capacitor C5 as a die capacitor is loaded on the matching circuit 25a as a die capacitor such that the back surface of the capacitor C5 is in contact with the surface of the matching circuit 25 a. The matching circuit 22a has a pair of circuit elements symmetrical to a virtual line L0, the virtual line L0 being connected to an input terminal T corresponding to the size of the transistor 21b IN And an output terminal T OUT And a matching circuit 25a and a capacitor C5 are included in each circuit element. With this bifurcated structure, the output of the transistor 21a in the front stage is electrically equivalently output to each finger electrode of the transistor 21b widely placed in the rear stage in the direction perpendicular to the virtual line L0. The surfaces of the two capacitors C5 are directly connected to the drain 24a of the transistor 21a in the preceding stage through bonding wires. The gate 23b of the transistor 21b in the subsequent stage is connected to the surfaces of the two matching circuits 25a through a plurality of bonding wires.
In this configuration of the matching circuit 22a, the T-type LCL circuit is constituted by an inductance component included in a bonding wire between the drain 24a of the transistor 21a in the preceding stage and the capacitor C5, the matching circuit 25a, and an inductance component included in a bonding wire between the matching circuit 25a and the gate 23b of the transistor 21b in the succeeding stage. Thus, it is possible toThe impedance seen from the drain 24a is made closer to the output impedance by impedance conversion, and effective signal amplification can be performed. Further, the capacitors C71 and C72 are directly connected to the drain 24a of the transistor 21a in the preceding stage, but the drain 24a is connected to the drain bias terminal T 1D Is isolated at high frequencies by the inductive component of the bond wire connecting capacitor C72 and capacitor C5.
In the transistor 21b in the subsequent stage, the source is connected to the substrate 2 via a via hole (not shown). Further, the drain 24b of the transistor 21b is connected to the wiring portion L via the surface electrode of the matching circuit 22b on the bottom plate 2 by a bonding wire 2D . In addition, wiring part L 2D Is connected to the surface of the capacitor C61 on the wiring substrate 3 by a bonding wire. Further, the drain 24b of the transistor 21b is also connected to the wiring portion L through a bonding wire via the surface electrode of the matching circuit 22b OUT . Furthermore, the coupling capacitor is connected to an output terminal T outside the package 6 OUT . By this connection, the terminal T can be biased from the drain 2D A drain bias is supplied to drain 24 b. Further, the drain bias terminal T 2D Is bypassed by capacitor C61 at high frequencies. Further, an output signal generated by the transistor 21b is output from the drain 24b to the output terminal T via the matching circuit 22b OUT 。
The matching circuit 22b is a matching circuit mounted on the output terminal T OUT Die capacitors on the side adjacent to the later stage transistors 21b on the bottom plate 2. The matching circuit 22a includes a pair of circuit elements 26x and 26y connected to an input terminal T corresponding to the size of the transistor 21b IN And an output terminal T OUT Is symmetrical to the virtual line L0 of (c). The pair of circuit elements 26x and 26y are connected to the drain 24b of the transistor 21b of the subsequent stage by a plurality of bonding wires (such as four bonding wires) along the virtual line L0, respectively, and the lengths of these bonding wires are set to increase as they are away from the virtual line L0. Further, the two circuit elements 26x and 26y are connected to the wiring portion L through a plurality of bonding wires (such as two bonding wires) having connection points in the vicinity of the virtual line L0 on the surface electrodes of the circuit elements 26x and 26y 2D And the lengths of the bonding wires are set to have the same length. By using this kind ofBifurcated configuration capable of reducing each finger electrode of the transistor 21b in the subsequent stage widely placed in the direction perpendicular to the virtual line L0 to the output terminal T OUT Is a distance difference between the two.
In this configuration of the matching circuit 22b, the T-type LCL circuit is composed of an inductance component included in the wiring between the drain 24b of the subsequent stage transistor 21b and the matching circuit 22b, and a wiring portion L included in the matching circuit 22b OUT The inductance component in the bond wires between. Therefore, the impedance seen from the drain 24b can be made closer to the output impedance by impedance conversion, and effective signal output can be performed. Further, the capacitor C61 is directly connected to the drain 24b of the transistor 21b in the subsequent stage, but the drain 24b and the drain bias terminal T are connected 2D Through the connection wiring part L 2D And the bond wires of the matching circuit 22b are isolated at high frequencies.
In the semiconductor amplifier 1 of the present embodiment, the transistor 21a, the matching circuit 22a, the transistor 21b, and the matching circuit 22b are loaded in this order to input the terminal T in the center portion of the side 3a on the base plate 2 mounted in the space of the package 6 IN Output terminal T in the center of side 3b OUT Is arranged linearly. In addition, two gate bias terminals T for supplying bias to the gates 23a and 23b of the two stages of the transistors 21a and 21b 1G And T 2G Is mounted at the end of the package 6, sandwiching the input terminal T at this position IN And two drain bias terminals T for supplying bias to the drains 24a and 24b of the two stages of the transistors 21a and 21b 1D And T 2D Is mounted at the end of the package 6, sandwiching the output terminal T at this position OUT . In such a configuration, the power supply terminal T IN The input signal is amplified by two-stage transistors 21a and 21b to generate an output signal, and the output signal is outputted from an output terminal T OUT And outputting. In this case, the two-stage transistors 21a and 21b are connected to the input terminal T together with the two matching circuits 22a and 22b IN And an output terminal T OUT Is arranged linearly with the input terminal T sandwiched therebetween IN Or output terminal T OUT Is a combination of two of (2)The terminals supply bias to the two-stage transistors 21a and 21b, and thereby prevent bias interference between the two stages of the transistors 21a and 21b. As a result, a stable level of the output signal can be generated while preventing bias disturbance in the multi-stage transistor.
Further, in the semiconductor amplifier 1, the terminal T is input via a via hole penetrating the wiring substrate 3 IN And an output terminal T OUT Wiring portions L on the wiring substrate 3 respectively connected to the gate electrode 23a of the transistor 21a and the matching circuit 22b in the preceding stage IN And a wiring part L OUT And (5) connection. In this configuration, the input terminal T IN And an output terminal T OUT Can be connected to the transistor 21a and the matching circuit 22b on the base plate 2 in the package 6 by short-distance wiring. As a result, degradation of the output signal can be prevented.
Further, the gate bias terminal T 1G Gate bias terminal T 2G Drain bias terminal T 1D And a drain bias terminal T 2D A wiring portion L formed on the substrate 3 via a metal embedded in a hollow portion of a side surface of the wiring substrate 3 1G 、L 2G 、L 1D And L 2D And (5) connection. In this case, two gate bias terminals T 1G And T 2G Two drain bias terminals T 1D And T 2D Can be connected to the two transistors 21a and 21b by short-distance wiring. As a result, the level of the output signal can be further stabilized.
Further, wiring part L GND A bottom plate 2 connected to a side surface of the wiring substrate 3 and an inner wall where the opening 7 is formed, is formed on the wiring substrate 3, and a wiring portion L GND Connected to the input terminal T IN Or output terminal T OUT And gate bias terminal T 1G Gate bias terminal T 2G Drain bias terminal T 1D And a drain bias terminal T 2D A bottom plate 2 between each of them. In this case, the wiring portion L on the wiring substrate 3 can be ensured GND Electrical connection with the base plate 2, and degradation of the output signal can be further prevented.
Further, in the present embodimentIs connected to a gate bias terminal T for supplying bias 1G Gate bias terminal T 2G Drain bias terminal T 1D And a drain bias terminal T 2D The bypass capacitors C21, C41, C71, and C61 of the package 6 are mounted on the wiring substrate 3 in the package body 6, and the bias terminals are connected to the bypass capacitors C21, C41, C71, and C61 via wires. This connection configuration is common to each bias terminal. In other words, the capacitors C21, C41, C71 and C61 are not mounted on the bottom plate 2 directly connected to the ground, but are mounted on the wiring portion L of the wiring substrate 3 GND And (3) upper part. Because of the wiring part L GND Is connected to the base plate 2 via the side surface of the wiring substrate 3, there is a minute inductance component from the capacitors C21, C41, C71, and C61 to the loading position of the base plate 2. Therefore, even if an inductance component inevitably occurs, the component is equal at each bias terminal, and thus the condition of the resonance frequency caused by such an inductance component outside the operating band of the semiconductor amplifier 1 can be commonized. If a condition for avoiding the influence of a high-frequency signal is found for a certain bias terminal, the condition can be applied to other bias terminals and the implementation design of the semiconductor chip and the passive element is simplified.
Further, additional capacitors C22, C42 and C72 are connected in parallel with bypass capacitors C21, C41 and C71 except for a drain bias terminal T 2D External bias terminal T 1G 、T 2G And T 1D . The capacitors C22, C42 and C72 are directly loaded on the base plate 2 so that the influence of the bonding wires is reduced. Further, since the capacitors C22, C42, and C72 are loaded in the cutout portions 7a of the opening 7, the loading possibility on the base plate 2 is enlarged. Further, the presence of the cutout 7a enhances the bias terminal T 1G And bias terminal T 1D Between and offset terminal T 2G And bias terminal T 2D Isolation effects between. Since the transistors 21a and 21b are loaded at the center of the package 6, the wiring from each bias terminal extends to the center of the package 6. As a result, since the distance between the wiring portions is narrowed at the central portion of the package 6, a notch is formed between the bias terminals, and the capacitor directly loaded on the base plate 2 is placed there, andand thus the bias wiring can be electrically separated. As a result, offset interference between the transistors 21a and 21b can be prevented, and a stable level of the output signal can be generated.
Further, in the matching circuit 22b, a pair of circuit elements 26x and 26y are connected to the wiring portion L via a plurality of bonding wires of the same length 2D . Therefore, the output characteristic of the transistor 21b having a large chip size and a large gate width can be stabilized, and the bias supplied to the drain 24b of the transistor 21b can also be stabilized. As a result, a stable output signal can be generated.
Further, the drain 24b of the transistor 21b and the pair of circuit elements 26x and 26y are connected via a plurality of bonding wires, and the lengths of the plurality of bonding wires are set to increase as they are away from the virtual line L0. With such a configuration, the transistor 21b and the output terminal T can be connected OUT The effective mutual inductance component is equalized among the plurality of bonding wires, and a stable output signal can be generated.
While the principles of the invention have been illustrated and described in the above exemplary embodiments, it will be understood by those skilled in the art that the invention may be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. Accordingly, all modifications and variations coming within the spirit and scope of the claims are claimed.
For example, in the semiconductor amplifier 1 of the above embodiment, the gate bias terminal T 1G And T 2G Can be mounted with the output terminal T sandwiched therebetween OUT Or the drain bias terminal T 1D And T 2D Can be mounted with the input terminal T sandwiched therebetween IN Is located at the position of (2).
Claims (10)
1. A semiconductor amplifier, comprising:
a package, the package comprising:
a metal base plate;
an insulating circuit board placed on the base plate and including a first opening;
an insulating side wall portion placed on a peripheral portion on the circuit board and including a second opening that is larger than and surrounds the first opening, and
a cover portion which is placed on the side wall portion and seals a space formed by the first opening and the second opening,
a first transistor and a second transistor, the first transistor and the second transistor being loaded side by side on the bottom plate in the space;
a first matching circuit which is loaded between the first transistor and the second transistor on the bottom plate in the space, the first matching circuit being connected between a drain of the first transistor and a gate of the second transistor;
a second matching circuit loaded near the second transistor in the space on the bottom plate, the second matching circuit being located on an opposite side of the second transistor with respect to the first transistor, the second matching circuit being connected to a drain of the second transistor;
an input terminal mounted at a center of one side of the circuit board and connected to a gate of the first transistor;
an output terminal mounted at a center of the other side opposite to the one side of the circuit board and connected to a drain of the second transistor via the second matching circuit;
a first gate bias terminal and a second gate bias terminal, the first gate bias terminal and the second gate bias terminal being connected to a gate of the first transistor and a gate of the second transistor, respectively, in such a manner that one of the input terminal or the output terminal of the circuit board is sandwiched between the first gate bias terminal and the second gate bias terminal; and
a first drain bias terminal and a second drain bias terminal, the first drain bias terminal and the second drain bias terminal being positioned in such a manner as to sandwich the other one of the input terminal and the output terminal of the circuit board therebetween, the first drain bias terminal and the second drain bias terminal being connected to a drain of the first transistor and a drain of the second transistor, respectively,
wherein,,
the first transistor, the first matching circuit, the second transistor, and the second matching circuit are linearly disposed between the input terminal and the output terminal.
2. The semiconductor amplifier of claim 1, wherein,
the input terminal and the output terminal are connected to an input wiring and an output wiring on the circuit board via a via hole penetrating the circuit board, the input wiring and the output wiring being connected to a gate of the first transistor and the second matching circuit.
3. The semiconductor amplifier according to claim 1 or 2, wherein,
the first gate bias terminal, the second gate bias terminal, the first drain bias terminal, and the second drain bias terminal are connected to a wiring portion formed on the circuit board via a metal embedded on a side surface of the circuit board.
4. A semiconductor amplifier according to any one of claims 1 to 3, wherein,
forming a ground wiring on the circuit board, the ground wiring being connected to the chassis on a side surface of the circuit board and an inner wall of the circuit board forming the first opening, and
the ground wiring is connected to the bottom plate between the input terminal or the output terminal and the first gate bias terminal, the second gate bias terminal, the first drain bias terminal, and the second drain bias terminal.
5. A semiconductor amplifier according to any one of claims 1 to 4, wherein,
the circuit board includes a cutout portion that forms the first opening on both sides connecting the one side and the other side.
6. The semiconductor amplifier of claim 4, wherein,
forming on the circuit board:
two gate wirings sandwiching one wiring of an input wiring connected to the input terminal and an output wiring connected to the output terminal, the two gate wirings being connected to the first gate bias terminal and the second gate bias terminal, and
two drain wirings sandwiching the other wiring among the input wiring connected to the input terminal and the output wiring connected to the output terminal, the two drain wirings being connected to the first drain bias terminal and the second drain bias terminal,
in the space, sandwiching the ground wiring by the two gate wirings or the two drain wirings, and
loading on the ground wiring:
two capacitors bypassing the two gate wirings connected to the first gate bias terminal and the second gate bias terminal, and
two capacitors connected to the two drain wirings of the first drain bias terminal and the second drain bias terminal are bypassed.
7. The semiconductor amplifier of claim 3, wherein,
the second matching circuit includes a pair of circuit elements connected to the drain of the second transistor and arranged symmetrically with respect to a virtual line connecting the input terminal and the output terminal, and
the wiring portion to be connected to the second drain bias terminal is connected to the virtual line side of each of the pair of circuit elements via a wire having the same length.
8. The semiconductor amplifier of claim 7, wherein,
the drain of the second transistor and the pair of circuit elements are connected via a plurality of wires, and the lengths of the plurality of wires are set to increase as the wires are farther from the virtual line.
9. The semiconductor amplifier according to any one of claims 1 to 8, wherein,
the second matching circuit forms an LCL circuit between the drain of the second transistor and the output terminal.
10. The semiconductor amplifier according to any one of claims 1 to 9, wherein,
the first matching circuit forms an LCL circuit between the drain of the first transistor and the gate of the second transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018-131324 | 2018-07-11 | ||
| JP2018131324A JP7136524B2 (en) | 2018-07-11 | 2018-07-11 | semiconductor amplifier |
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| Publication Number | Publication Date |
|---|---|
| CN110719076A CN110719076A (en) | 2020-01-21 |
| CN110719076B true CN110719076B (en) | 2023-09-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910620156.2A Active CN110719076B (en) | 2018-07-11 | 2019-07-10 | semiconductor amplifier |
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| Country | Link |
|---|---|
| US (2) | US10903795B2 (en) |
| JP (1) | JP7136524B2 (en) |
| CN (1) | CN110719076B (en) |
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| JP6835293B2 (en) * | 2018-04-16 | 2021-02-24 | 三菱電機株式会社 | High frequency power amplifier |
| CN117595794B (en) * | 2024-01-19 | 2024-04-12 | 成都雷电微力科技股份有限公司 | Frequency division suppression structure based on 3D heterogeneous power amplifier chip |
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| CN1329754A (en) * | 1998-12-02 | 2002-01-02 | 艾利森公司 | High frequency power transistor device |
| CN1909363A (en) * | 2005-07-26 | 2007-02-07 | 英飞凌科技股份公司 | Semiconductor power device and RF signal amplifier |
| CN103545281A (en) * | 2012-07-11 | 2014-01-29 | 三菱电机株式会社 | Semiconductor device |
| CN107026165A (en) * | 2016-01-29 | 2017-08-08 | 英飞凌科技股份有限公司 | Circuit including the semiconductor devices containing the first and second transistors and control circuit |
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| JPH05243871A (en) | 1992-02-28 | 1993-09-21 | Nec Yamagata Ltd | High frequency transistor |
| JP2000209038A (en) * | 1998-11-12 | 2000-07-28 | Hitachi Ltd | High frequency power amplifier and radio communication equipment |
| US6329879B1 (en) * | 1998-11-12 | 2001-12-11 | Hitachi, Ltd. | High frequency power amplifier system and wireless communication system |
| TW200518345A (en) * | 2003-08-08 | 2005-06-01 | Renesas Tech Corp | Semiconductor device |
| EP1710048B1 (en) * | 2004-01-28 | 2013-06-12 | Nikon Corporation | Polishing pad surface shape measuring instrument, method of using polishing pad surface shape measuring instrument, method of measuring apex angle of cone of polishing pad, method of measuring depth of groove of polishing pad, cmp polisher, and method of manufacturing semiconductor device |
| WO2006057156A1 (en) * | 2004-11-29 | 2006-06-01 | Autonetworks Technologies, Ltd. | Electric junction box |
| JP2016019068A (en) * | 2014-07-07 | 2016-02-01 | 株式会社東芝 | High frequency amplifier |
| JP6769646B2 (en) * | 2016-11-22 | 2020-10-14 | 住友電工デバイス・イノベーション株式会社 | Semiconductor device |
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2018
- 2018-07-11 JP JP2018131324A patent/JP7136524B2/en active Active
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2019
- 2019-07-10 US US16/507,114 patent/US10903795B2/en active Active
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1329754A (en) * | 1998-12-02 | 2002-01-02 | 艾利森公司 | High frequency power transistor device |
| CN1909363A (en) * | 2005-07-26 | 2007-02-07 | 英飞凌科技股份公司 | Semiconductor power device and RF signal amplifier |
| CN103545281A (en) * | 2012-07-11 | 2014-01-29 | 三菱电机株式会社 | Semiconductor device |
| CN107026165A (en) * | 2016-01-29 | 2017-08-08 | 英飞凌科技股份有限公司 | Circuit including the semiconductor devices containing the first and second transistors and control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| US11588441B2 (en) | 2023-02-21 |
| US20210104977A1 (en) | 2021-04-08 |
| JP2020010242A (en) | 2020-01-16 |
| US10903795B2 (en) | 2021-01-26 |
| US20200021246A1 (en) | 2020-01-16 |
| JP7136524B2 (en) | 2022-09-13 |
| CN110719076A (en) | 2020-01-21 |
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