CN110689910B - Memory configuration structure - Google Patents
Memory configuration structure Download PDFInfo
- Publication number
- CN110689910B CN110689910B CN201810731384.2A CN201810731384A CN110689910B CN 110689910 B CN110689910 B CN 110689910B CN 201810731384 A CN201810731384 A CN 201810731384A CN 110689910 B CN110689910 B CN 110689910B
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- row
- contacts
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- perforations
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- 230000015654 memory Effects 0.000 title claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000005192 partition Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- Semiconductor Memories (AREA)
Abstract
A memory allocation structure comprises a plurality of substrates; a plurality of perforation areas respectively communicated with the center of each substrate; the first contact areas are respectively communicated with each substrate and positioned at one side of each perforation area, and each first contact area is used for being connected with each foot pad of a memory through a signal wire; and a plurality of second contact areas respectively communicated with each substrate and positioned at the other side of each perforation area, wherein each second contact area is used for being connected with each foot pad of the memory by a signal wire and at least comprises PAR pins of the memory, and one substrate is electrically connected with the first or second contact areas of the other substrate through the perforation areas by the first or second contact areas, after each pin of the memory is electrically connected with the first or second contact areas, each substrate is electrically connected in a cross-layer manner by the signal wire corresponding to the first or second contact areas through the guidance of the perforation areas, so that the situation of breaking a reference layer can be effectively avoided when the memory is manufactured, and the memory has better power distribution and enough circuit layout space, thereby maintaining better signal integrity.
Description
Technical Field
The present invention relates to a memory configuration structure, and more particularly, to a memory configuration structure capable of effectively avoiding the occurrence of breakage of a reference layer during the fabrication of a memory, and having a better power distribution and a sufficient circuit layout space, thereby maintaining a better signal integrity.
Background
In general, the existing memory is generally configured to electrically connect each pin to each contact according to the configuration requirement, and each contact is electrically connected with each other by a signal line; thereby completing the setting of the memory.
However, in the existing wiring mode of the memory, the substrate is provided with through holes at each position, and each pin and each contact of the memory are directly and mutually electrically connected through the through holes by using signal lines, so that the situation of poor power distribution is caused besides the situation of relatively limited circuit layout space, and the reference layer is broken during wiring, so that the reference layer of the memory cannot have signal integrity.
Therefore, in order to improve the above-mentioned drawbacks, the present inventors have intensively studied to develop a memory configuration structure to effectively improve the drawbacks of the existing memories.
Disclosure of Invention
The present invention is directed to a memory configuration structure, which can effectively avoid the situation that the reference layer is broken during the memory fabrication, and has better power distribution and enough circuit layout space, so as to maintain better signal integrity.
To achieve the above object, the present invention is a memory configuration structure, comprising: a plurality of substrates; a plurality of perforation areas respectively communicated with the center of each substrate; the first contact areas are respectively communicated with each substrate and positioned at one side of each perforation area, and each first contact area is used for being connected with each foot pad of a memory through a signal wire; and a plurality of second contact areas respectively communicated with the substrates and positioned at the other side of each perforation area, wherein each second contact area is used for being connected with each foot pad of the memory by a signal wire and at least comprises a PAR pin of the memory, and one substrate is electrically connected with the first contact area or the second contact area of the other substrate through the perforation area by the first contact area or the second contact area.
In an embodiment of the present invention, each of the through holes includes a first row of through holes, a second row of through holes disposed at one side of the first row of through holes, and a third row of through holes disposed at one side of the second row of through holes.
In an embodiment of the present invention, each first row of holes has at least eight holes, each second row of holes has at least nine holes, and each third row of holes has at least eight holes.
In an embodiment of the present invention, a partition is respectively disposed between each of the first row of holes, each of the second row of holes and each of the three rows of holes.
In an embodiment of the invention, an insulation portion is disposed at an outer edge of each through hole, and a power connection portion is disposed between each through hole.
In an embodiment of the invention, each first contact point includes a first row of contact points, a second row of contact points disposed at one side of the first row of contact points, and a third row of contact points disposed at one side of the second row of contact points, and each first row of contact points, each second row of contact points, and each third row of contact points has at least nine contact points.
In an embodiment of the invention, each second contact includes a first row of contacts, a second row of contacts disposed on one side of the first row of contacts, and a third row of contacts disposed on one side of the second row of contacts, and each first row of contacts, each second row of contacts, and each third row of contacts has at least nine contacts.
In an embodiment of the invention, each of the first contact areas and each of the second contact areas are electrically connected with one of the contact areas or the second contact area of the other substrate through the through hole area by signal lines through two surfaces of the one substrate.
In one embodiment of the present invention, the signal lines are the same length.
After each pin of the memory is electrically connected with the first contact area and the second contact area, each substrate is electrically connected with each other in a cross-layer manner through the guidance of the through hole area by the signal wire corresponding to the first contact area or the second contact area, so that the situation that the reference layer is broken can be effectively avoided when the memory is manufactured, and the memory has better power distribution and enough circuit layout space, thereby maintaining better signal integrity.
Drawings
Fig. 1 is a basic schematic of the present invention.
FIG. 2 is a schematic view of the use state of the present invention.
Component reference number control:
A substrate 1;
A perforated region 2;
a first row of perforations 21;
perforations 211, 221, 231;
insulation portions 212, 222, 232;
A second row of perforations 22;
A third row of perforations 23;
A partition 24;
a power supply connection unit 25;
A first contact region 3;
a first row of contacts 31;
contacts 311, 321, 331;
a second row of contacts 32;
a third row of contacts 33;
A second contact region 4;
a first row of contacts 41;
Contacts 411, 421, 431;
A second row of contacts 42;
a third row of contacts 43;
A signal line 5.
Detailed Description
Fig. 1 and fig. 2 show a basic schematic view of the present invention and a usage state schematic view of the present invention, respectively. As shown in the figure: the present invention is a memory configuration structure, which at least comprises a plurality of substrates 1, a plurality of through holes 2, a plurality of first contact areas 3 and a plurality of second contact areas 4.
Each substrate 1 is a circuit board, and each substrate 1 is provided so as to be vertically aligned or stacked.
The perforation areas 2 are respectively communicated with the center of the base plates 1.
The first contact areas 3 are respectively connected to the substrate 1 and located at one side of the through hole areas 2, and each first contact area 3 is used for connecting with a signal line (not shown) for each pad of a memory.
The second contact areas 4 are respectively connected to the other side of each through hole area 2 and are respectively arranged on the substrate 1, each second contact area 4 is used for being connected with each pad of the memory by a signal wire and at least comprises a PAR pin (not shown) of the memory, and one substrate is electrically connected with the first contact area 3 or the second contact area 4 of the other substrate 1 through the through hole area 2 by the first contact area 3 or the second contact area 4.
When each pin of the memory is electrically connected with the first contact area 3 and the second contact area 4 of one substrate 1, the signal lines 5 corresponding to the first contact area 3 and the second contact area 4 can be electrically connected with one contact area 3 or the second contact area 4 of the other substrate 1 in a cross-layer manner (not shown) through the guidance of the through hole area 2, so that the situation that the reference layer is broken can be effectively avoided when the memory is manufactured, and the memory has better power distribution and enough circuit layout space, thereby maintaining better signal integrity.
In an embodiment of the present invention, each perforation area 2 includes a first row of perforations 21, a second row of perforations 22 disposed on one side of the first row of perforations 21, and a third row of perforations 23 disposed on one side of the second row of perforations 22, each first row of perforations 21 has at least eight perforations 211, each second row of perforations 22 has at least nine perforations 221, each third row of perforations 23 has at least eight perforations 231, a partition 24 is disposed between each first row of perforations 21, each second row of perforations 22, and each third row of perforations 23, and the outer edge of each perforation has an insulation portion 212, 222, 232, and a power connection portion 25 is disposed between each perforation 211, 221, 231.
In an embodiment of the present invention, each first contact area 3 includes a first row of contacts 31, a second row of contacts 32 disposed on one side of the first row of contacts 31, and a third row of contacts 33 disposed on one side of the second row of contacts 32, and each first row of contacts 31, each second row of contacts 32, and each third row of contacts 33 has at least nine contacts 311, 321, 331.
In an embodiment of the present invention, each second contact area 4 includes a first row of contacts 41, a second row of contacts 42 disposed on one side of the first row of contacts 41, and a third row of contacts 43 disposed on one side of the second row of contacts 42, and each first row of contacts 41, each second row of contacts 42, and each third row of contacts 43 has at least nine contacts 411, 421, 431.
When the memory is electrically connected to the first contact area 3 and the second contact area 4 of one of the substrates 1, the following is illustrated:
when the memory is connected, at least the VDD pin of the memory is connected to the first contact 311 of the first row of contacts 31 in the first contact area 3; the a13 pin of the memory is connected to the first contact 321 of the second row of contacts 32 provided in the first contact area 3; the a17 pin of the memory is connected to the first contact 331 of the third row of contacts 33 provided in the first contact area 3; the PAR pin of the memory is connected to the first contact 411 of the first row of contacts 41 provided in the second contact area 4; the a11 pin of the memory is connected to the first contact 421 of the second row of contacts 42 provided in the second contact area 4; the VSS pin of the memory is connected to the first contact 431 of the third row of contacts 43 provided in the second contact area 4.
Since the through hole region 2 is disposed between the first contact region 3 and the second contact region 4, when the first contact region 3 and the second contact region 4 of the substrate 1 are electrically connected with another substrate 1 (not shown), each signal line 5 is electrically connected with the first contact region 3 and the second contact region 4 of the other substrate 1 through the first row of through holes 21, the second row of through holes 22 and the third row of through holes 23 of the through hole region 2 respectively, so that each signal line 5 is routed and guided through each through hole 211, 221, 231 of the first contact region 3 and each contact 411, 421, 431 of the second contact region 4 as required, each signal line 5 is electrically connected with each power connection portion 25 as required, in this embodiment, each signal line 5 is of the same length, so that each signal line 5 is routed cleanly, the signal lines cannot be broken down, and the layout of the power lines is good, and the power lines can be distributed with good efficiency and good reference.
Besides the first, second and third rows of through holes 21, 22 and 23 being separated by the separating portions 24 to prevent the signal lines 5 from interfering with each other, when the signal lines 5 are inserted into the through holes 211, 221 and 231, the insulating portions 212, 222 and 232 prevent the signal lines 5 from contacting the power connection portions 25 to generate short circuits.
In summary, the memory configuration structure of the present invention can electrically connect each pin of the memory with the first contact area and the second contact area, and then electrically connect each substrate with each signal line corresponding to the first contact area or the second contact area through the guidance of the through hole area in a cross-layer manner, so that the situation that the reference layer is broken can be effectively avoided when the memory is manufactured, and the memory configuration structure has better power distribution and enough circuit layout space, and further can maintain better signal integrity; the invention can be developed more practically and more in line with the requirements of consumers, and the invention meets the requirements of the patent application of the invention, and the patent application is proposed by law.
However, the foregoing description is only of a preferred embodiment of the invention and is not intended to limit the scope of the invention; therefore, all simple and equivalent changes and modifications made in accordance with the claims and the content of the present specification shall fall within the scope of the patent covered by the present invention.
Claims (8)
1. A memory configuration structure, comprising:
a plurality of substrates;
The perforation areas are respectively communicated with the center of each substrate and each perforation area comprises a first row of perforations, a second row of perforations arranged at one side of the first row of perforations and a third row of perforations arranged at one side of the second row of perforations;
the first contact areas are respectively communicated with the substrates and positioned at one side of each perforation area, and each first contact area is used for being connected with each foot pad of a memory through a signal wire; and
The second contact areas are respectively communicated with the substrates and are positioned at the other side of each perforation area, each second contact area is used for being connected with each foot pad of the memory by a signal wire and at least comprises a PAR pin of the memory, and one substrate is electrically connected with the first contact area or the second contact area of the other substrate through the perforation area by the first contact area or the second contact area.
2. The memory arrangement of claim 1, wherein each first row of perforations has at least eight perforations, each second row of perforations has at least nine perforations, and each third row of perforations has at least eight perforations.
3. The memory arrangement of claim 2, wherein each of the first row of perforations, each of the second row of perforations, and each of the third row of perforations has a partition therebetween.
4. The memory arrangement as claimed in claim 2, wherein the outer edge of each of the through holes has an insulating portion, and a power connection portion is provided between each of the through holes.
5. The memory arrangement of claim 1, wherein each first contact includes a first row of contacts, a second row of contacts disposed on a side of the first row of contacts, and a third row of contacts disposed on a side of the second row of contacts, each first row of contacts, each second row of contacts, and each third row of contacts having at least nine contacts.
6. The memory arrangement of claim 1, wherein each second contact includes a first row of contacts, a second row of contacts disposed on one side of the first row of contacts, and a third row of contacts disposed on one side of the second row of contacts, each first row of contacts, each second row of contacts, and each third row of contacts having at least nine contacts.
7. The memory arrangement of claim 1, wherein each of the first contact areas and each of the second contact areas are electrically connected to one of the contact areas or the second contact area of the other substrate via the through hole area by signal lines through two surfaces of one of the substrates.
8. The memory arrangement of claim 7, wherein each signal line is the same length.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810731384.2A CN110689910B (en) | 2018-07-05 | 2018-07-05 | Memory configuration structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810731384.2A CN110689910B (en) | 2018-07-05 | 2018-07-05 | Memory configuration structure |
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| Publication Number | Publication Date |
|---|---|
| CN110689910A CN110689910A (en) | 2020-01-14 |
| CN110689910B true CN110689910B (en) | 2024-10-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810731384.2A Active CN110689910B (en) | 2018-07-05 | 2018-07-05 | Memory configuration structure |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103369817A (en) * | 2012-04-09 | 2013-10-23 | 佳能株式会社 | Printed circuit board |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6664620B2 (en) * | 1999-06-29 | 2003-12-16 | Intel Corporation | Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer |
| JP2005093575A (en) * | 2003-09-16 | 2005-04-07 | Nec Electronics Corp | Semiconductor integrated circuit device and wiring layout method |
| JP5548342B2 (en) * | 2007-10-23 | 2014-07-16 | パナソニック株式会社 | Semiconductor device |
| US8659143B2 (en) * | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
| KR102310511B1 (en) * | 2014-12-19 | 2021-10-08 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
| JP2017045915A (en) * | 2015-08-28 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| KR20170042429A (en) * | 2015-10-08 | 2017-04-19 | 삼성전자주식회사 | Semiconductor package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103369817A (en) * | 2012-04-09 | 2013-10-23 | 佳能株式会社 | Printed circuit board |
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| CN110689910A (en) | 2020-01-14 |
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