CN110634862B

CN110634862B - Semiconductor structure and forming method thereof

Info

Publication number: CN110634862B
Application number: CN201810653795.4A
Authority: CN
Inventors: 于书坤
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2018-06-22
Filing date: 2018-06-22
Publication date: 2023-05-05
Anticipated expiration: 2038-06-22
Also published as: CN110634862A

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a device region, the type of the device region comprises one or two of an NMOS region and a PMOS region, and the device region of the same type is used for forming devices with different threshold voltages; forming a gate structure on a substrate; forming grooves in the substrates at two sides of the grid structure, wherein in the device region of the same type, the minimum distances from the groove side walls corresponding to different threshold voltages to the side walls of the adjacent grid structures are different along the direction perpendicular to the side walls of the grid structures; and forming source-drain doped layers in the grooves. The invention not only can be used for easily adjusting the threshold voltage of each device respectively by adjusting the minimum distance from the side wall of each groove to the side wall of the adjacent grid structure in the device region of the same type, but also can reduce the adverse effect of the process for forming the work function layer on the performance and the yield of the device, and avoid the cross effect of the threshold voltage adjustment of any device on other devices.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

Complementary metal oxide semiconductor (Complementary Metal-Oxide Semiconductor, CMOS) devices are one of the basic semiconductor devices that make up integrated circuits. With the rapid development of integrated circuit manufacturing process, the feature size of CMOS devices is continuously shrinking according to a certain proportion, and the use of a gate dielectric layer of high-k material instead of a gate dielectric layer of conventional oxide material is a trend of integrated circuit development. However, there are many problems to be solved when forming metal gates on high-k gate dielectric layers, one of which is the work function matching problem. Since the work function will directly affect the threshold voltage (Vt) and device performance of the device, the work function must be tuned to be within the proper operating range of the CMOS device.

CMOS devices include P-type metal oxide semiconductor (PMOS) devices and N-type metal oxide semiconductor (NMOS) devices, and in order to meet the requirement of the NMOS devices and PMOS devices for improving threshold voltages at the same time, different metal materials are generally used as Work Function (WF) layer materials of the NMOS devices and the PMOS devices, so that the NMOS devices and the PMOS devices have different threshold voltages, wherein the NMOS devices have N-type Work Function layers and the PMOS devices have P-type Work Function layers.

However, the current process of adjusting the threshold voltage has a relatively large difficulty, and the adjustment of the threshold voltage easily causes the degradation of the device performance and yield.

Disclosure of Invention

The invention solves the problem of providing a semiconductor structure and a forming method thereof, which can reduce the process difficulty of adjusting threshold voltage and improve the performance and yield of devices.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a device region, the type of the device region comprises one or two of an NMOS region and a PMOS region, and the device region of the same type is used for forming devices with different threshold voltages; forming a gate structure on the substrate; forming grooves in substrates at two sides of the grid structure, wherein in the device region of the same type, the minimum distances from the groove side walls corresponding to different threshold voltages to the side walls of the adjacent grid structures are different along the direction perpendicular to the side walls of the grid structure; and forming a source-drain doping layer in the groove.

Correspondingly, the invention also provides a semiconductor structure, which comprises: the substrate comprises a device region, wherein the type of the device region comprises one or two of an NMOS region and a PMOS region, and devices with different threshold voltages are respectively formed in the same type of the device region; a metal gate structure located on the substrate; the source-drain doped layers are positioned in the substrates at two sides of the metal gate structure, and in the device region of the same type, the minimum distances from the side walls of the source-drain doped layers corresponding to different threshold voltages to the side walls of the adjacent metal gate structures are different along the direction perpendicular to the side walls of the metal gate structures.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the invention, when grooves are formed in substrates at two sides of a grid structure in the process of forming devices (NMOS devices or PMOS devices) of the same type with different threshold voltages, the minimum distances from the groove side walls corresponding to the different threshold voltages to the side walls of the adjacent grid structure are different along the direction perpendicular to the side walls of the grid structure, and as the minimum distances from the groove side walls to the side walls of the adjacent grid structure are smaller, the external parasitic resistance (Rex) of the devices is smaller, the threshold voltages of the devices are smaller, therefore, NMOS devices or PMOS devices with different threshold voltages are obtained by adjusting the minimum distances from the side walls of each groove in the device regions of the same type to the side walls of the adjacent grid structure, and when work function layers are formed subsequently, the device regions of the same type can share the same work function layer; therefore, compared with the scheme of adjusting the threshold voltage by adjusting the thickness of the work function layer, the method is easy to respectively adjust the threshold voltage of each device, can simplify the process steps for forming the work function layer, reduce the times of photoetching, etching, ashing and cleaning processes, correspondingly reduce the adverse effect of the process for forming the work function layer on the performance and the yield of the device, and avoid the Cross effect of the threshold voltage adjustment of any device on other devices (Cross Impact); in conclusion, the scheme of the invention is beneficial to reducing the process difficulty of adjusting the threshold voltage, and also can reduce the adverse effect of the adjustment of the threshold voltage on the performance and yield of the device.

In an alternative scheme, the device region comprises an NMOS region and a PMOS region, and threshold voltages of the PMOS device and the NMOS device are conveniently and respectively adjusted by adjusting the minimum distance from the side wall of each groove in the device region of the same type to the side wall of the adjacent grid structure, so that cross influence between the PMOS device and the NMOS device is prevented, the process difficulty of adjusting the threshold voltages is further reduced, and the device performance and the yield are improved.

Drawings

Fig. 1 to 7 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;

fig. 8 to 25 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

Lightly doped drain (Lightly Doped Drain, LDD) implants are the primary process for precisely adjusting the threshold voltage of the device, but as CMOS device feature sizes continue to decrease, semiconductor processes gradually begin to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). After a Fin structure is introduced into a semiconductor structure, the effect of adjusting the threshold voltage of a device by a lightly doped drain injection process is correspondingly deteriorated, so that the NMOS device and the PMOS device have different threshold voltages mainly by a Multi-layer work function layer process (Multi-Work Function Process) at present.

In the multi-layer work function layer process, the doping ion concentration of the source-drain doping layers of the NMOS devices is the same, the doping ion concentration of the source-drain doping layers of the PMOS devices is the same, and the threshold voltages of the NMOS devices and the PMOS devices are respectively adjusted to process requirement values by forming corresponding metal materials (one or two of N-type work function layer materials and P-type work function layer materials) and work function layers with corresponding thicknesses in the areas.

However, the current process of adjusting the threshold voltage has a relatively large difficulty, and the adjustment of the threshold voltage easily causes the degradation of the device performance and yield. The reason why it is difficult to adjust the threshold voltage is now analyzed in conjunction with a method of forming a semiconductor structure.

Referring to fig. 1 to 7, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.

Referring to fig. 1, a substrate 10 is provided, including a first NMOS region 11N, a first PMOS region 11P, a second NMOS region 12N, and a second PMOS region 12P, wherein a device threshold voltage of the first NMOS region 11N is greater than a device threshold voltage of the second NMOS region 12N, and a device threshold voltage of the first PMOS region 11P is greater than a device threshold voltage of the second PMOS region 12P; a high-k gate dielectric Layer 11 is formed on the substrate 10, a Cap Layer 12 is formed on the high-k gate dielectric Layer 11, and a first P-type work function Layer 21 is formed on the Cap Layer 12.

Referring to fig. 2, a first photoresist layer (not shown) is formed on the first P-type work function layer 21 of the second PMOS region 12P; etching to remove the first P-type work function layer 21 of the first NMOS region 11N, the first PMOS region 11P and the second NMOS region 12N by using the first photoresist layer as a mask; and removing the first photoresist layer.

Referring to fig. 3, after the first P-type work function layer 21 of the first NMOS region 11N, the first PMOS region 11P, and the second NMOS region 12N is etched away, a second P-type work function layer 22 is formed on the substrate 10, where the second P-type work function layer 22 covers the remaining first P-type work function layer 21 and the cap layer 12 where the remaining first P-type work function layer 21 is exposed.

Referring to fig. 4, a second photoresist layer (not shown) is formed on the second P-type work function layer 22 of the first PMOS region 11P and the second PMOS region 12P; etching to remove the second P-type work function layer 22 of the first NMOS region 11N and the second NMOS region 12N by using the second photoresist layer as a mask; and removing the second photoresist layer.

Referring to fig. 5, after the second P-type work function layer 22 of the first NMOS region 11N and the second NMOS region 12N is etched away, a third P-type work function layer 23 is formed on the substrate 10, and the third P-type work function layer 23 covers the remaining second P-type work function layer 22 and the cap layer 12 where the remaining second P-type work function layer 22 is exposed.

Referring to fig. 6, a third photoresist layer (not shown) is formed on the third P-type work function layer 23 of the first PMOS region 11P, the second PMOS region 12P and the first NMOS region 11N; etching to remove the third P-type work function layer 23 of the second NMOS region 12N by using the third photoresist layer as a mask; and removing the third photoresist layer.

Referring to fig. 7, after the third P-type work function layer 23 of the second NMOS region 12N is etched and removed, an N-type work function layer 24 is formed on the substrate 10, where the N-type work function layer 24 covers the remaining third P-type work function layer 23 and the cap layer 12 where the remaining third P-type work function layer 23 is exposed.

Taking the example that the first NMOS region 11N is used to form an N-type standard threshold voltage (NSVT) device, the second NMOS region 12N is used to form an N-type low threshold voltage (NLVT) device, the first PMOS region 11P is used to form a P-type standard threshold voltage (PSVT) device, and the second PMOS region 12P is used to form a P-type low threshold voltage (PLVT) device, the second P-type work function layer 22 affects the threshold voltages of the P-type standard threshold voltage device and the P-type low threshold voltage device, the third P-type work function layer 23 affects the threshold voltages of the P-type standard threshold voltage device, the P-type low threshold voltage device and the N-type standard threshold voltage device, the N-type work function layer 24 affects the threshold voltages of the four devices, and the work function layer adjustment affects other devices in a cross manner, so that it is difficult to individually adjust the threshold voltage of any device through the work function layer.

In addition, in the process of the multi-layer work function layer, three photolithography processes and three etching processes are required, so that photoresist of a carbon-based (C-based) material not only has a problem of photoresist residue (PR Residual), but also C ions can diffuse into the work function layer through the contact surface between the photoresist layer and the work function layer, and multiple etching and ashing processes can damage the work function layer and the cap layer 12, thereby adversely affecting the performance and yield of the device.

In order to solve the technical problem, when grooves are formed in the substrates at two sides of the grid structure, the minimum distances from the groove side walls to the adjacent grid structure side walls corresponding to different threshold voltages are different along the direction perpendicular to the grid structure side walls, and as the minimum distances from the groove side walls to the adjacent grid structure side walls are smaller, the external parasitic resistance of the device is smaller, the threshold voltage of the device is smaller, so that NMOS devices or PMOS devices with different threshold voltages can be obtained by adjusting the minimum distances from the groove side walls to the adjacent grid structure side walls in the device regions of the same type, and the device regions of the same type can share the same work function layer when the work function layer is formed subsequently; therefore, compared with the scheme of adjusting the threshold voltage by adjusting the thickness of the work function layer, the method is easy to respectively adjust the threshold voltage of each device, can simplify the process steps for forming the work function layer, reduce the times of photoetching, etching, ashing and cleaning processes, correspondingly reduce the adverse effect of the process for forming the work function layer on the performance and the yield of the device, and avoid the cross effect of the threshold voltage adjustment of any device on other devices; in conclusion, the scheme of the invention is beneficial to reducing the process difficulty of adjusting the threshold voltage, and also can reduce the adverse effect of the adjustment of the threshold voltage on the performance and yield of the device.

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 8 through 10 in combination, fig. 8 is a perspective view (only four fins are illustrated), fig. 9 is a schematic cross-sectional view of the different device regions of fig. 8 along a direction perpendicular to the fin extension direction (as shown in the Y1Y2 direction of fig. 8), fig. 10 is a schematic cross-sectional view of the different device regions of fig. 8 along the fin extension direction (as shown in the X1X2 direction of fig. 8), a substrate 100 is provided, the substrate 100 includes a device region (not labeled), the device region includes one or both of an NMOS region 110N and a PMOS region 110P, and the device region of the same type is used to form devices of different threshold voltages.

In this embodiment, the substrate 100 is used to form a finfet, so the substrate 100 includes a substrate 110 and a plurality of discrete fins 120 on the substrate 110. In other embodiments, the substrate may also be used to form a planar transistor, with the substrate then being the substrate accordingly.

In this embodiment, the substrate 110 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.

In this embodiment, the fin 120 and the substrate 110 are integrally formed. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin. Therefore, in this embodiment, the material of the fin 120 is the same as the material of the substrate 110, and the material of the fin 120 is silicon. In other embodiments, the material of the fin portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin portion may be different from the material of the substrate.

The device region types include one or both of an NMOS region 110N and a PMOS region 110P, the NMOS region 110N being used to form NMOS devices of different threshold voltages, and the PMOS region 110P being used to form PMOS devices of different threshold voltages. In this embodiment, the device region types include an NMOS region 110N and a PMOS region 110P.

It should be noted that the device regions of the same type may be any of a high threshold voltage region, a standard threshold voltage region, a low threshold voltage region, and an ultra-low threshold voltage region. That is, the PMOS region 110P may be any of a P-type high threshold voltage region, a P-type standard threshold voltage region, a P-type low threshold voltage region, and a P-type ultra-low threshold voltage region, and the NMOS region 110N may be any of an N-type high threshold voltage region, an N-type standard threshold voltage region, an N-type low threshold voltage region, and an N-type ultra-low threshold voltage region.

In this embodiment, the device regions of the same type include a first device region (not labeled) and a second device region (not labeled), the device threshold voltage of the first device region being less than the device threshold voltage of the second device region. Specifically, as shown in fig. 8, the first device region in the NMOS region 110N is a first NMOS region 111N, the second device region in the NMOS region 110N is a second NMOS region 112N, the first device region in the PMOS region 110P is a first PMOS region 111P, the second device region in the PMOS region 110P is a second PMOS region 112P, the device threshold voltage of the first NMOS region 111N is smaller than the device threshold voltage of the second NMOS region 112N, and the device threshold voltage of the first PMOS region 111P is smaller than the device threshold voltage of the second PMOS region 112P.

In this embodiment, the first PMOS region 111P is a P-type low threshold voltage region, the second PMOS region 112P is a P-type standard threshold voltage region, the first NMOS region 111N is an N-type low threshold voltage region, and the second NMOS region 112N is an N-type standard threshold voltage region.

It should be further noted that, for convenience of illustration, fig. 9 and 10 only illustrate schematic cross-sectional views of the NMOS region 110N and the PMOS region 110P, that is, fig. 9 and 10 may be used to characterize either one of the first PMOS region 111P and the second PMOS region 112P, and either one of the first NMOS region 111N and the second NMOS region 112N.

Further, with continued reference to fig. 8-10, the forming method further includes: an isolation structure 101 is formed on the substrate 100.

The isolation structure 101 is used to isolate adjacent devices. In this embodiment, the material of the isolation structure 101 is silicon oxide. In other embodiments, the material of the isolation structure may be silicon nitride or other insulating materials such as silicon oxynitride.

In this embodiment, the isolation structure 101 is formed on the substrate 110 exposed by the fin 120, the isolation structure 101 covers a portion of the sidewall of the fin 120, and the top of the isolation structure 101 is lower than the top of the fin 120.

Referring to fig. 11 and 12 in combination, fig. 11 is a schematic cross-sectional view based on fig. 9, and fig. 12 is a schematic cross-sectional view based on fig. 10, a gate structure 130 is formed on the substrate 100 (shown in fig. 8).

In this embodiment, the Gate structure 130 is a Dummy Gate structure (Dummy Gate), and the Gate structure 130 is used to occupy a space for a subsequently formed Metal Gate structure (Metal Gate).

The gate structure 130 may be a stacked structure, including a dummy gate oxide layer and a dummy gate layer on the dummy gate oxide layer; the gate structure 130 may also be a single layer structure including a dummy gate layer. The material of the dummy gate layer may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide or amorphous carbon, and the material of the dummy gate oxide layer may be silicon oxide or silicon oxynitride. In this embodiment, the gate structure 130 is a single-layer structure, and the material of the dummy gate layer is polysilicon.

Specifically, the gate structure 130 spans across the fin 120 and covers a portion of the top and a portion of the sidewalls of the fin 120.

In this embodiment, the gate structure 130 is formed by using a mask etching method, so a gate mask layer 200 is formed on top of the gate structure 130, and the gate mask layer 200 is used as an etching mask for forming the gate structure 130. The material of the gate mask layer 200 is silicon nitride, and the gate mask layer 200 is further used to protect the top of the gate structure 130 during the subsequent process.

It should be noted that after forming the gate structure 130, the method further includes: a sidewall 140 is formed on the sidewall of the gate structure 130, and the sidewall 140 further covers the sidewall of the gate mask layer 200.

The material of the side wall 140 may be one or more of silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride, and the side wall 140 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 140 is a single-layer structure, and the material of the side wall 140 is silicon nitride.

It should be noted that, unless otherwise specified, the drawings provided in the subsequent process are schematic cross-sectional views along the fin extension direction (as shown in the X1X2 direction in fig. 8).

Referring to fig. 13 to 20 in combination, grooves (not labeled) are formed in the substrate at both sides of the gate structure 130, and in the same type of device region (not labeled), the minimum distances (not labeled) from the groove sidewalls corresponding to different threshold voltages to the adjacent gate structure 130 sidewalls are different along the direction perpendicular to the gate structure 130 sidewalls; source-drain doped layers (not shown) are formed in the grooves.

In the device region of the same type, the smaller the minimum distance from the sidewall of the groove to the sidewall of the adjacent gate structure 130 is, the smaller the minimum distance from the source-drain doped layer to the sidewall of the gate structure 130 is, the smaller the external parasitic resistance (Rex) of the device is, and the smaller the threshold voltage of the device is correspondingly, so that the adjustment of the threshold voltage of each device can be realized by adjusting the minimum distance from each sidewall of the groove to the sidewall of the adjacent gate structure 130 in the device region of the same type, and when the work function layer is formed subsequently, the device region of the same type can share the same work function layer; compared with the scheme of adjusting the threshold voltage by adjusting the thickness of the work function layer, the method is easy to respectively adjust the threshold voltage of each device, can simplify the process steps of forming the work function layer, reduce the times of photoetching, etching, ashing and cleaning processes, correspondingly reduce the adverse effect of the process of forming the work function layer on the performance and the yield of the device, and avoid the cross effect of threshold voltage adjustment of any device on other devices.

In this embodiment, the device region includes an NMOS region 110N and a PMOS region 110P, and accordingly, by adjusting the minimum distance between the sidewalls of each recess and the sidewalls of the adjacent gate structure 130, it is also convenient to adjust the threshold voltages of the PMOS device and the NMOS device, respectively, so as to prevent the cross-over effect between the PMOS device and the NMOS device.

In this embodiment, the groove (not labeled) located in the first device region (not labeled) is a first groove (not labeled), and the groove located in the second device region (not labeled) is a second groove (not labeled). In the same type of the device regions, the device threshold voltage of the first device region is less than the device threshold voltage of the second device region, so the minimum distance (not labeled) of the first recess sidewall to the adjacent gate structure 130 sidewall is less than the minimum distance (not labeled) of the second recess sidewall to the adjacent gate structure 130 sidewall.

Specifically, the first groove formed in the PMOS region 110P is a first P-region groove 151 (as shown in fig. 14), the second groove formed in the PMOS region 110P is a second P-region groove 152 (as shown in fig. 15), and the minimum distance D1 (as shown in fig. 14) between the sidewall of the first P-region groove 151 and the sidewall of the adjacent gate structure 130 is smaller than the minimum distance D2 (as shown in fig. 15) between the sidewall of the second P-region groove 152 and the sidewall of the adjacent gate structure 130.

Similarly, the first groove formed in the NMOS region 110N is a first N-region groove 153 (as shown in fig. 18), the second groove formed in the NMOS region 110N is a second N-region groove 154 (as shown in fig. 19), and the minimum distance D5 (as shown in fig. 18) between the sidewall of the first N-region groove 153 and the sidewall of the adjacent gate structure 130 is smaller than the minimum distance D6 (as shown in fig. 19) between the sidewall of the second N-region groove 154 and the sidewall of the adjacent gate structure 130.

In a semiconductor process, the source-drain doped layer of the NMOS region 110N is typically formed after the source-drain doped layer of the PMOS region 110P is formed, and thus, in order to reduce process variations, the recess of the NMOS region 110N is formed after the recess of the PMOS region 110P is formed. In other embodiments, the recess of the PMOS region may also be formed after the recess of the NMOS region is formed.

In this embodiment, the first P-region groove 151, the second P-region groove 152, the first N-region groove 153, and the second N-region groove 154 are sequentially formed as an example.

Referring to fig. 13 to 15 in combination, fig. 13 to 15 are schematic cross-sectional views of the first PMOS region and the second PMOS region along the fin extension direction, and a first P-region recess 151 (shown in fig. 14) is formed in the substrate 100 (shown in fig. 8) at both sides of the first PMOS region 111P gate structure 130; a second P-region groove 152 is formed in the substrate 100 on both sides of the gate structure 130 of the second PMOS region 112 (as shown in fig. 15).

In this embodiment, the first P-region groove 151 and the second P-region groove 152 are U-shaped. The sidewalls of the first and second P-

region grooves

151 and 152, which are U-shaped, are perpendicular to the surface of the substrate 110, thereby advantageously reducing the effect of the process of forming the first and second P-

region grooves

151 and 152 on the device channel region. In other embodiments, the shape of the first P-region groove may be bowl-shaped or Sigma-shaped, and the shape of the second P-region groove may be bowl-shaped or Sigma-shaped.

Specifically, the step of forming the first P-region groove 151 and the second P-region groove 152 includes:

as shown in fig. 13, a first mask layer 210 is formed on the substrate 100 (shown in fig. 8), wherein the first mask layer 210 covers the top and the sidewalls of the fin 120 of the first PMOS region 111P and the second PMOS region 112P, and also covers the top and the sidewalls of the fin 120 of the first NMOS region 111N (shown in fig. 8) and the second NMOS region 112N (shown in fig. 8).

The process of forming the first mask layer 210 may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the first mask layer 210 is formed by using an atomic layer deposition process, so that the first mask layer 210 conformally covers the top and the sidewall of the fin 120, the top and the sidewall of the gate structure 130, and the isolation structure 101 where the gate structure 130 is exposed.

In this embodiment, the first mask layer 210 is a PMOS Silicon Recess (PSR) mask layer, and the first mask layer 210 is used as an etching mask for a subsequent etching process, so as to increase the distances between the first P-region Recess 151 (as shown in fig. 14), the second P-region Recess 152 (as shown in fig. 15), and the gate structure 130; in addition, the first mask layer 210 located on the fin 120 sidewall may also play a role in protecting the fin 120 sidewall, so as to avoid performing an epitaxial growth process on the fin 120 sidewall.

It should be noted that, the material of the first mask layer 210 is a material with a common process and a relatively high process compatibility, and the first mask layer 210 needs to be removed later, so that the material of the first mask layer 210 is also a material easy to remove, and the process of removing the first mask layer 210 has a small influence on other film structures. Accordingly, the material of the first mask layer 210 may be silicon nitride, silicon oxide, boron nitride or silicon oxynitride. In this embodiment, the material of the first mask layer 210 is silicon nitride.

As shown in fig. 14, the first mask layer 210 on the fin portions 120 at two sides of the first PMOS region 111P gate structure 130 is etched to expose the fin portions 120 at two sides of the first PMOS region 111P gate structure 130, and a part of the thickness material of the exposed fin portions 120 is also etched, so that the first P-region recess 151 is formed in the etched first PMOS region 111P fin portions 120.

In this embodiment, before etching the first mask layer 210, the method further includes: forming a first filling layer 310 on the substrate 100 (as shown in fig. 8), the first filling layer 310 covering the first mask layer 210; forming a first photoresist layer (not shown) on the first filling layer 310, wherein the first photoresist layer exposes the first filling layer 310 on two sides of the gate structure 130 of the first PMOS region 111P; the first filling layer 310 is etched using the first photoresist layer as a mask.

The material of the first filling layer 310 is a Bottom Anti-reflection coating (Bottom Anti-ReflectCoating, BARC) material, and the first filling layer 310 is used for improving the appearance quality of the first photoresist layer; the first photoresist layer can protect the first mask layer 210 of the second PMOS region 112P, the first NMOS region 111N, and the second NMOS region 112N, and the first photoresist layer can also cover the regions of the first PMOS region 111P that are not desired to be etched.

Specifically, after the first filling layer 310 is etched, the first photoresist layer is used as a mask to etch and remove the first mask layer 210 on top of the fin portions 120 on both sides of the gate structure 130 of the first PMOS region 111P; in the dry etching process, the first mask layer 210 on the isolation structure 101 at two sides of the gate structure 130 of the first PMOS region 111 is also etched and removed; after the tops of the fin portions 120 at two sides of the P gate structure 130 of the first PMOS region 111 are exposed, etching is continued to form a portion of the exposed fin portion 120 to form the first P-region recess 151.

It should be noted that, the minimum distance D1 between the sidewall of the first P region groove 151 and the sidewall of the adjacent gate structure 130 should not be too large, otherwise, the distance between the source-drain doped layer of the first PMOS region 111P and the gate structure 130 is too large, which is easy to adversely affect the performance of the device. For this reason, in this embodiment, in order to reduce the process risk and reduce the influence on the device channel, the minimum distance D1 between the sidewall of the first P-region groove 151 and the sidewall of the adjacent gate structure 130 is

To the point of

Wherein when the site isThe minimum distance D1 is +.>

The sidewalls of the first P-region recess 151 are then characterized as being flush with the sidewalls of the adjacent gate structure 130. />

By reasonably setting the minimum distance D1 from the sidewall of the first P region groove 151 to the sidewall of the adjacent gate structure 130, on the basis of realizable process, it is beneficial to ensure that the subsequent PMOS region 110P (as shown in fig. 8) can share the same work function layer while ensuring that the threshold voltage of the device in the first PMOS region 111P can meet the process requirement, and the threshold voltages of other devices in the PMOS region 110P can also meet the process requirement.

In other embodiments, when the first P-region groove is bowl-shaped or Sigma-shaped, in order to reduce the process risk and reduce the influence on the device channel, the minimum distance between the sidewall of the first P-region groove and the sidewall of the adjacent gate structure is

To->

And when the minimum distance is a negative value, the side wall of the first P region groove is characterized to be positioned below the adjacent gate structure, namely the projection of the first P region groove on the substrate is overlapped with the projection part of the adjacent gate structure on the substrate.

In this embodiment, the first P-region groove 151 is U-shaped, so the first P-region groove 151 is formed by a dry etching process in which the carrier gas includes Ar and O ₂ 、N ₂ He and H ₂ One or more of the dry etching process, wherein the etching gas comprises HBr and Cl ₂ 、HCl、SO ₂ 、CF ₄ 、CHF ₃ 、CH ₂ F2、CH ₃ F. And CH (CH) ₄ One or more of the following.

Specifically, by adjusting the etching time of the dry etching process, the minimum distance D1 from the sidewall of the first P-region groove 151 to the sidewall of the adjacent gate structure 130 meets the process requirement.

In this embodiment, after the first P-region groove 151 is formed, a wet photoresist removing or ashing process is used to remove the first filling layer 310 and the first photoresist layer.

As shown in fig. 15, after the first P-region recess 151 (as shown in fig. 14) is formed, the first mask layer 210 on the fin portions 120 on both sides of the gate structure 130 of the second PMOS region 112P is etched to expose the fin portions 120 on both sides of the gate structure 130 of the second PMOS region 112P, and a portion of the thickness material of the exposed fin portions 120 is also etched, so that the second P-region recess 152 is formed in the etched fin portions 120 of the second PMOS region 112P.

In this embodiment, before etching the first mask layer 210 on the fin 120 at two sides of the gate structure 130 of the second PMOS region 112P, the method further includes: forming a second filling layer 320 on the substrate 100 (as shown in fig. 8), wherein the second filling layer 320 fills the first P-region groove 151 and also covers the first mask layer 210, the gate structure 130 and the isolation structure 101; forming a second photoresist layer (not shown) on the second filling layer 320, wherein the second photoresist layer exposes the second filling layer 320 on both sides of the gate structure 130 of the second PMOS region 112P; and etching the second filling layer 320 by using the second photoresist layer as a mask.

For a specific description of the second filling layer 320 and the second photoresist layer, reference may be made to the foregoing related description of the first filling layer 310 (as shown in fig. 14) and the first photoresist layer (not shown), and the detailed description thereof will be omitted.

Specifically, after etching the second filling layer 320, the second photoresist layer is used as a mask to etch and remove the first mask layer 210 on top of the fin portions 120 on both sides of the gate structure 130 of the second PMOS region 112P; in the dry etching process, the first mask layer 210 on the isolation structure 101 at two sides of the gate structure 130 of the second PMOS region 112P is also etched and removed; after the tops of the fin portions 120 at two sides of the gate structure 130 of the second PMOS region 112P are exposed, etching is continued to form a portion of the thickness material of the exposed fin portion 120, so as to form the second P-region groove 152.

In this embodiment, the minimum distance D2 between the sidewall of the second P-region groove 152 and the sidewall of the adjacent gate structure 130 is

To->

In other embodiments, when the second P-region groove is bowl-shaped or Sigma-shaped, the minimum distance between the sidewall of the second P-region groove and the sidewall of the adjacent gate structure is +.>

To->

In this embodiment, since the device threshold voltage of the first PMOS region 111P is smaller than the device threshold voltage of the second PMOS region 112P, the minimum distance D2 from the sidewall of the second P-region groove 152 to the sidewall of the adjacent gate structure 130 is greater than the minimum distance D1 from the sidewall of the first P-region groove 151 to the sidewall of the adjacent gate structure 130 (as shown in fig. 14), i.e., the sidewall of the second P-region groove 152 is farther away from the adjacent gate structure 130 than the sidewall of the first P-region groove 151.

In this embodiment, the minimum distance D2 between the sidewall of the second P region groove 152 and the sidewall of the adjacent gate structure 130 is reasonably adjusted according to the actual process condition, so that the device threshold voltage of the second PMOS region 112P meets the process requirement on the basis of realizable process, and the subsequent PMOS region 110P (as shown in fig. 8) can share the same work function layer, and the threshold voltages of other devices in the PMOS region 110P can also meet the process requirement.

In this embodiment, the second P-region groove 152 is formed by a dry etching process. For a specific description of the dry etching process, reference may be made to the corresponding description in the formation of the first P-region groove 151, which is not repeated herein.

In this embodiment, the etching time used to form the grooves (not labeled) corresponding to different threshold voltages is different. Specifically, in the process of forming the second P-region groove 152, the etching time of the dry etching process is increased, so that the minimum distance D2 from the sidewall of the second P-region groove 152 to the sidewall of the adjacent gate structure 130 is greater than the minimum distance D1 from the sidewall of the first P-region groove 151 to the sidewall of the adjacent gate structure 130. Accordingly, the etching time of the dry etching process for forming the second P-region grooves 152 is longer than the etching time of the dry etching process for forming the first P-region grooves 151.

In this embodiment, after the second P-region groove 152 is formed, a wet photoresist removing or ashing process is used to remove the second filling layer 320 and the second photoresist layer.

For a specific description of the second P-region groove 152, reference may be made to the corresponding description of the first P-region groove 151 (as shown in fig. 14) described above, and the description will not be repeated here.

After forming the first P-region groove 151 (as shown in fig. 14) and the second P-region groove 152 (as shown in fig. 15), the method further includes: and cleaning the first P region groove 151 and the second P region groove 152. The cleaning process is used to remove impurities on the surfaces of the first P-region groove 151 and the second P-region groove 152, and remove a natural oxide layer (not shown) on the surface of the fin 120, so as to provide a good process foundation for the subsequent epitaxial process.

The cleaning solution used in the cleaning treatment may be a combination of aqueous ammonia, a mixed solution of hydrogen peroxide and water (SC 1 solution) and diluted hydrofluoric acid (DHF), or may be a combination of ozone water, SC1 solution and DHF.

In this embodiment, the second P-region groove 152 is formed after the first P-region groove 151 is formed. In other embodiments, the first P-region recess may also be formed after the second P-region recess is formed.

In addition, in this embodiment, the first P-region groove 151 and the second P-region groove 152 are formed in a sequential manner, respectively. In other embodiments, the first P-region groove and the second P-region groove may also be formed in the same etching process.

Specifically, the step of forming the first P-region groove and the second P-region groove includes: performing first etching treatment on the substrates at two sides of the grid structure of the first PMOS region, and forming initial grooves in the substrates at two sides of the grid structure of the first PMOS region; and carrying out second etching treatment on the substrate at two sides of the grid structure of the second PMOS region and the initial groove, forming a second groove in the substrate at two sides of the grid structure of the second PMOS region, wherein the initial groove after the second etching treatment is the first groove. The second etching treatment has the same etching amount on the substrate at two sides of the grid structure of the second PMOS region and the initial groove, so that the initial groove provides the allowance of the minimum distance difference by means of first etching treatment, and the distance from the first groove to the side wall of the adjacent grid structure is smaller than the distance from the second groove to the side wall of the adjacent grid structure through the same etching process, so that the purpose of adjusting the threshold voltage of the device is achieved.

Or, before performing a first etching treatment on the first mask layer of the first PMOS region, removing a part of thickness material of the first mask layer along a direction perpendicular to the side wall of the gate structure, where the thickness removal amount of the first mask layer in the first etching treatment is a difference value between a minimum distance from the side wall of the groove of the second P region to the side wall of the adjacent gate structure and a minimum distance from the side wall of the groove of the first P region to the side wall of the adjacent gate structure; and after the first etching treatment, performing second etching treatment on the substrates at two sides of the grid structures of the first PMOS region and the second PMOS region, forming the first groove in the substrate at two sides of the grid structure of the first PMOS region, and forming the second groove in the substrate at two sides of the grid structure of the second PMOS region. The first mask layer is further used as an etching mask for forming the first groove and the second groove, so that the distance from the first groove to the side wall of the adjacent gate structure is smaller than the distance from the second groove to the side wall of the adjacent gate structure by reducing the thickness of the first mask layer of the first PMOS region.

Referring to fig. 16, fig. 16 is a schematic cross-sectional view of fig. 15, in which source and drain doped layers (not shown) of the PMOS region 110P (shown in fig. 8) are formed in the first P region recess 151 (shown in fig. 14) and the second P region recess 152 (shown in fig. 15).

In this embodiment, the source-drain doped layer formed in the PMOS region 110P is the P-type source-drain doped layer 160, and since the minimum distance D2 (as shown in fig. 15) from the sidewall of the second P-region trench 152 to the sidewall of the adjacent gate structure 130 is greater than the minimum distance D1 (as shown in fig. 14) from the sidewall of the first P-region trench 151 to the sidewall of the adjacent gate structure 130, the minimum distance D3 from the P-type source-drain doped layer 160 of the first PMOS region 111P to the sidewall of the adjacent gate structure 130 is smaller than the minimum distance D4 from the P-type source-drain doped layer 160 of the second PMOS region 112P to the sidewall of the adjacent gate structure 130, so that the threshold voltage of the device formed in the first PMOS region 111P is smaller.

Specifically, the step of forming the P-type source-drain doped layer 160 includes: a first epitaxial layer (not shown) is formed in the first P-region groove 151 and the second P-region groove 152 by a selective epitaxial process, and P-type ions are self-doped in situ during the process of forming the first epitaxial layer, so as to form the P-type source/drain doped layer 160.

Due to the high cost of the selective epitaxy process, the number of times of the epitaxy process can be reduced by forming the P-type source/drain doped layer 160 after forming the first P-region groove 151 and the second P-region groove 152, thereby being beneficial to reducing the process cost.

The material of the first epitaxial layer may be SiGe, geSn or GeSb, and the first epitaxial layer provides a compressive stress to the device channel region of the PMOS region 110P, so as to improve the carrier mobility of the PMOS region 110P.

In this embodiment, the P-type ion is a B ion. The Atomic Mass (Atomic Mass) of B is small and can act as a spacer in the first epitaxial layer, thereby being beneficial to preventing the B doping from influencing the compressive stress effect of the first epitaxial layer. In other embodiments, the P-type ions may also be Ga ions or In ions.

In this embodiment, the material of the first epitaxial layer is SiGe, so the material of the P-type source/drain doped layer 160 is SiGe doped with B ions, i.e., the material of the P-type source/drain doped layer 160 is SiGeB.

It should be noted that, in the P-type source-drain doped layer 160, the higher the doping concentration of P-type ions, the more obvious the corresponding compressive stress providing effect is; however, in the semiconductor process, the subsequent process further includes forming a metal silicide (silicide) layer on the P-type source/drain doped layer 160, and forming a contact plug (CT) electrically connected to the metal silicide layer on the metal silicide layer, where the doping concentration of P-type ions is too high, which may cause a problem of too high contact resistance. Therefore, in order to reduce the contact resistance while ensuring the compressive stress effect of the P-type source-drain doped layer 160, the step of forming the P-type source-drain doped layer 160 includes: a bottom P-type source-drain doped layer 161 is formed in the first and second P-

region grooves

151 and 152, and a top P-type source-drain doped layer 162 is formed on the bottom P-type source-drain doped layer 161.

In this embodiment, in order to effectively reduce the contact resistance, the P-type ions are not doped in the top P-type source/drain doped layer 162, and the material of the top P-type source/drain doped layer 162 is the same as the material of the first epitaxial layer. In other embodiments, the P-type ions may also be doped in the top P-type source-drain doped layer, and the concentration of the doping ions in the top P-type source-drain doped layer is smaller.

In this embodiment, due to the nature of the selective epitaxy process, the top of the P-type source/drain doped layer 160 is higher than the top of the first P-region groove 151 and the second P-region groove 152. In other embodiments, the P-type source-drain doped layer may be flush with the tops of the first P-region recess and the second P-region recess.

It should be noted that, in order to protect the surface of the P-type source-drain doped layer 160, after forming the P-type source-drain doped layer 160, the method further includes: the surface of the P-type source/drain doped layer 160 is subjected to an oxidation treatment, and a first oxide layer (not shown) is formed on the surface of the P-type source/drain doped layer 160, where the oxidation treatment may be dry oxygen oxidation, wet oxygen oxidation or water vapor oxidation. In other embodiments, the first oxide layer may not be formed.

In addition, in order to facilitate the formation of the subsequent film layer, after the P-type source/drain doped layer 160 is formed, the first mask layer 210 is removed, so that a larger space position is provided for the subsequent formation of the second mask layer, and the second mask layer can cover the P-type source/drain doped layer 160, thereby avoiding the damage to the surface of the P-type source/drain doped layer 160 caused by the subsequent process. In other embodiments, the first mask layer may not be removed.

Referring to fig. 17 to 19 in combination, fig. 17 to 19 are schematic cross-sectional views of the first NMOS region and the second NMOS region along the fin extension direction, and a first N-region groove 153 (shown in fig. 18) is formed in the substrate 100 (shown in fig. 8) at both sides of the N-gate structure 130 of the first NMOS region 111; a second N-region recess 154 is formed in the substrate 100 on both sides of the second NMOS region 112N gate structure 130 (as shown in fig. 19).

In this embodiment, the first N-region groove 153 and the second N-region groove 154 are U-shaped. In other embodiments, the shape of the first N-region groove may be bowl-shaped or Sigma-shaped, and the shape of the second N-region groove may be bowl-shaped or Sigma-shaped.

Specifically, the step of forming the first N-region groove 153 and the second N-region groove 154 includes:

As shown in fig. 17, a second mask layer 230 is formed on the substrate 100 (shown in fig. 8), wherein the second mask layer 230 covers the top and the sidewalls of the fin 120 of the first NMOS region 111N and the second NMOS region 112N, and also covers the top and the sidewalls of the fin 120 of the first PMOS region 111P (shown in fig. 16) and the second PMOS region 112P (shown in fig. 16).

Specifically, the second mask layer 230 conformally covers the top and sidewalls of the fin 120 exposed by the gate structure 130, the P-type source-drain doped layer 160, the top and sidewalls of the gate structure 130, and the isolation structure 101 exposed by the gate structure 130.

The material of the second mask layer 230 may be silicon nitride, silicon oxide, boron nitride or silicon oxynitride. In this embodiment, the material of the second mask layer 230 is silicon nitride.

In this embodiment, the second mask layer 230 is an NMOS Silicon Recess (NSR) mask layer, and the second mask layer 230 is used as an etching mask for a subsequent etching process, so as to increase the distance between the first N-region groove 153 (as shown in fig. 18) and the second N-region groove 154 (as shown in fig. 19) and the gate structure 130; in addition, the second mask layer 230 located on the side wall of the fin 120 may also play a role in protecting the side wall of the fin 120, so as to avoid performing an epitaxial growth process on the side wall of the fin 120.

As shown in fig. 18, the second mask layer 230 on the fin portions 120 at two sides of the gate structure 130 of the first NMOS region 111N is etched to expose the fin portions 120 at two sides of the gate structure 130 of the first NMOS region 111N, and a part of the thickness material of the exposed fin portions 120 is also etched, so that the first N-region recess 153 is formed in the etched fin portions 120 of the first NMOS region 111N.

It should be noted that, before etching the second mask layer 230, the method further includes: forming a third filling layer 330 on the substrate 100 (as shown in fig. 8), the third filling layer 330 covering the second mask layer 230; forming a third photoresist layer (not shown) on the third filling layer 330, wherein the third photoresist layer exposes the third filling layer 330 on two sides of the gate structure 130 of the first NMOS region 111N; the third filling layer 330 is etched by using the third photoresist layer as a mask, so as to expose a portion of the second mask layer 230.

For a specific description of the third filling layer 330 and the third photoresist layer, reference may be made to the foregoing related description of the first filling layer 310 (as shown in fig. 14) and the first photoresist layer (not shown), and the detailed description thereof will be omitted.

Specifically, after the third filling layer 330 is etched, the third photoresist layer is used as a mask to etch and remove the third mask layer 230 on top of the fin portions 120 on both sides of the gate structure 130 of the first NMOS region 111N; in the dry etching process, the third mask layer 230 on the isolation structure 101 at two sides of the gate structure 130 of the first NMOS region 111 is also etched and removed; after the tops of the fin portions 120 at two sides of the gate structure 130 of the first NMOS region 111N are exposed, etching is continued to form a portion of the exposed fin portion 120 to form the first N-region recess 153.

In this embodiment, the minimum distance D5 between the sidewall of the first N-region groove 153 and the sidewall of the adjacent gate structure 130 is

To->

In other embodiments, when the first N-region groove is bowl-shaped or Sigma-shaped, the minimum distance between the sidewall of the first N-region groove and the sidewall of the adjacent gate structure is +.>

To->

By reasonably setting the minimum distance D5 from the sidewall of the first N region groove 153 to the sidewall of the adjacent gate structure 130, it is beneficial to ensure that the NMOS region 110N (as shown in fig. 8) can share the same work function layer while ensuring that the threshold voltage of the device in the first NMOS region 111N can meet the process requirement, and the threshold voltages of other devices in the NMOS region 110N can also meet the process requirement.

In this embodiment, the first N-region groove 153 is formed by a dry etching process. For a specific description of the dry etching process, reference may be made to the corresponding description in the formation of the first P-region groove 151 (as shown in fig. 14), which is not repeated herein.

Specifically, by adjusting the etching time of the dry etching process, the minimum distance D5 from the sidewall of the first N-region groove 153 to the sidewall of the adjacent gate structure 130 meets the process requirement.

In this embodiment, after the first N-region groove 153 is formed, a wet photoresist removing or ashing process is used to remove the third filling layer 330 and the third photoresist layer.

For a detailed description of the process steps of forming the first N-region groove 153, reference may be made to the foregoing corresponding description of the first P-region groove 151, which is not repeated herein.

As shown in fig. 19, after the first N-region groove 153 (as shown in fig. 18) is formed, the second mask layer 230 on the fin portions 120 on both sides of the gate structure 130 of the second NMOS region 112N is etched to expose the fin portions 120 on both sides of the gate structure 130 of the second NMOS region 112N, and a part of the thickness material of the exposed fin portions 120 is also etched, so that the second N-region groove 154 is formed in the etched fin portions 120 of the second NMOS region 112N.

It should be noted that before etching the second mask layer 230 on the fin portion 120 at two sides of the gate structure 130 of the second NMOS region 112N, the method further includes: forming a fourth filling layer 340 on the substrate 100 (as shown in fig. 8), wherein the fourth filling layer 340 fills the first N-region groove 153 and also covers the second mask layer 230, the gate structure 130 and the isolation structure 101; forming a fourth photoresist layer (not shown) on the fourth filling layer 340, wherein the fourth photoresist layer exposes the fourth filling layer 340 at two sides of the gate structure 130 of the second NMOS region 112N; the fourth filling layer 340 is etched with the fourth photoresist layer as a mask, exposing a portion of the second mask layer 230.

For a specific description of the fourth filling layer 340 and the fourth photoresist layer, reference may be made to the foregoing related description of the first filling layer 310 (as shown in fig. 14) and the first photoresist layer (not shown), and the detailed description thereof will be omitted.

Specifically, after etching the fourth filling layer 340, the second mask layer 230 on top of the fin portions 120 on both sides of the gate structure 130 of the second NMOS region 112N is etched and removed by using the fourth photoresist layer as a mask; in the dry etching process, the second mask layer 230 on the isolation structure 101 at two sides of the gate structure 130 of the second NMOS region 112N is also etched and removed; after the tops of the fin portions 120 at two sides of the gate structure 130 of the second NMOS region 112N are exposed, etching is continued to form a portion of the exposed fin portion 120 to form the second N-region recess 154.

In this embodiment, the second N-region groove 154 is formed from the sidewall to the adjacent gateThe minimum distance D6 of the side wall of the pole structure 130 is

To->

In other embodiments, when the second N-region groove is bowl-shaped or Sigma-shaped, the minimum distance between the sidewall of the second N-region groove and the sidewall of the adjacent gate structure is +.>

To->

In this embodiment, since the device threshold voltage of the first NMOS region 111N is smaller than the device threshold voltage of the second NMOS region 112N, the minimum distance D6 from the sidewall of the second N-region recess 154 to the sidewall of the adjacent gate structure 130 is greater than the minimum distance D5 from the sidewall of the first N-region recess 153 (as shown in fig. 18) to the sidewall of the adjacent gate structure 130 (as shown in fig. 18), i.e., the sidewall of the second N-region recess 154 is farther away from the adjacent gate structure 130 than the sidewall of the first N-region recess 153.

The minimum distance D6 between the sidewall of the second N region groove 154 and the sidewall of the adjacent gate structure 130 is reasonably adjusted according to the actual process condition, so that the device threshold voltage of the second NMOS region 112N meets the process requirement on the basis of the process realization, the NMOS region 110N (as shown in fig. 8) can share the same work function layer, and the threshold voltages of other devices in the NMOS region 110N can also meet the process requirement.

In this embodiment, the second N-region groove 154 is formed by a dry etching process. For a specific description of the dry etching process, reference may be made to the corresponding description in the formation of the first P-region groove 151 (as shown in fig. 14), which is not repeated herein.

In this embodiment, the etching time used to form the grooves (not labeled) corresponding to different threshold voltages is different. Specifically, in the process of forming the second N-region groove 154, the etching time of the dry etching process is increased, so that the minimum distance D6 from the sidewall of the second N-region groove 154 to the sidewall of the adjacent gate structure 130 is greater than the minimum distance D5 from the sidewall of the first N-region groove 153 to the sidewall of the adjacent gate structure 130. Accordingly, the etching time of the dry etching process for forming the second N-region grooves 154 is longer than the etching time of the dry etching process for forming the first N-region grooves 153.

In this embodiment, after the second N-region groove 154 is formed, a wet photoresist removing or ashing process is used to remove the fourth filling layer 340 and the fourth photoresist layer.

For a detailed description of the process steps of forming the second N-region groove 154, reference may be made to the corresponding description of the first P-region groove 151 (shown in fig. 14) described above, and thus, a detailed description thereof will not be repeated.

After forming the first N-region groove 153 and the second N-region groove 154, the method further includes: the first N-region groove 153 and the second N-region groove 154 are subjected to a cleaning process. The cleaning process is used to remove impurities on the surfaces of the first N-region groove 153 and the second N-region groove 154, and also to remove a native oxide layer (not shown) on the surface of the fin 120, thereby providing a good process base for the subsequent epitaxial process.

In this embodiment, the second N-region groove 154 is formed after the first N-region groove 153 is formed. In other embodiments, the first N-region groove may also be formed after the second N-region groove is formed.

In addition, in this embodiment, the first N-region groove 153 and the second N-region groove 154 are formed in a sequential manner, respectively. In other embodiments, the first N-region groove and the second N-region groove may also be formed in the same etching process. Specifically, for a specific description of the process steps of forming the first N-region groove and the second N-region groove, reference may be made to the foregoing corresponding descriptions in the first P-region groove and the second P-region groove, which are not repeated herein.

Referring to fig. 20, fig. 20 is a schematic cross-sectional view of fig. 19, in which source and drain doped layers (not shown) of the NMOS region 110N (shown in fig. 8) are formed in the first N-region recess 153 (shown in fig. 18) and the second N-region recess 154 (shown in fig. 19).

In this embodiment, the source-drain doped layer formed in the NMOS region 110N is an N-type source-drain doped layer 180, and since the minimum distance D6 (as shown in fig. 19) from the sidewall of the second N-region groove 154 to the sidewall of the adjacent gate structure 130 is greater than the minimum distance D5 (as shown in fig. 18) from the sidewall of the first N-region groove 153 to the sidewall of the adjacent gate structure 130, the minimum distance D7 from the N-type source-drain doped layer 180 of the first NMOS region 111N to the sidewall of the adjacent gate structure 130 is smaller than the minimum distance D8 from the N-type source-drain doped layer 180 of the second NMOS region 112N to the sidewall of the adjacent gate structure 130, so that the threshold voltage of the device formed in the first NMOS region 111N is smaller.

Specifically, the step of forming the N-type source-drain doped layer 180 includes: a second epitaxial layer (not shown) is formed in the first N-region groove 153 and the second N-region groove 154 by a selective epitaxial process, and N-type ions are self-doped in situ during the process of forming the second epitaxial layer, so as to form the N-type source/drain doped layer 180.

By forming the N-type source-drain doped layer 180 after forming the first N-region groove 153 and the second N-region groove 154, the number of epitaxial processes can be reduced, thereby being beneficial to reducing the process cost.

The second epitaxial layer is made of Si or SiC, and provides a tensile stress effect for the device channel region of the NMOS region 110N, so as to improve carrier mobility of the NMOS region 110N.

In this embodiment, the N-type ions are P ions. In other embodiments, the N-type ions may also be As ions or Sb ions.

In this embodiment, the material of the second epitaxial layer is Si, so the material of the N-type source-drain doped layer 180 is Si doped with P ions, i.e., the material of the N-type source-drain doped layer 180 is SiP.

The top of the N-type source-drain doped layer 180 is higher than the top of the first N-region recess 153 and the second N-region recess 154 due to the nature of the selective epitaxy process. In other embodiments, the top of the N-type source-drain doped layer may be flush with the tops of the first N-region groove and the second N-region groove.

It should be noted that, in order to protect the surface of the N-type source-drain doped layer 180, after forming the N-type source-drain doped layer 180, the method further includes: and oxidizing the surface of the N-type source-drain doped layer 180, and forming a second oxide layer (not shown) on the surface of the N-type source-drain doped layer 180, wherein the oxidation treatment can be dry oxygen oxidation, wet oxygen oxidation or water vapor oxidation. In other embodiments, the second oxide layer may not be formed.

It should be further noted that, in order to facilitate the formation of the subsequent film layer, after the N-type source/drain doped layer 180 is formed, the second mask layer 230 is removed, so that a larger space position is provided for the subsequent film layer such as the high-k gate dielectric layer and the work function layer, which is beneficial to improving the formation quality of the subsequent film layer. In other embodiments, the second mask layer may also be retained.

Referring to fig. 21 and 22 in combination, fig. 21 is a schematic cross-sectional view of a PMOS region and an NMOS region along a direction perpendicular to an extension direction of the fin, fig. 22 is a schematic cross-sectional view of the PMOS region and the NMOS region along the extension direction of the fin, an interlayer dielectric layer 102 is formed on a substrate 100 (shown in fig. 8) exposed by the gate structure 130 (shown in fig. 22), the interlayer dielectric layer 102 covers the P-type source-drain doped layer 160 and the N-type source-drain doped layer 180, and the interlayer dielectric layer 102 exposes a top of the gate structure 130.

The interlayer dielectric layer 102 is used to achieve electrical isolation between adjacent devices, and the interlayer dielectric layer 102 is also used to define the dimensions and locations of subsequently formed metal gate structures.

The interlayer dielectric layer 102 is made of an insulating material. In this embodiment, the material of the interlayer dielectric layer 102 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be another dielectric material such as silicon nitride or silicon oxynitride.

In this embodiment, before the interlayer dielectric layer 102 is formed, the gate mask layer 200 is formed on top of the gate structure 130 (as shown in fig. 16 and 20), so that during the process of forming the interlayer dielectric layer 102, the gate mask layer 200 is also removed, i.e. the top of the interlayer dielectric layer 102 is flush with the top of the gate structure 130.

It should be noted that, for convenience of illustration, fig. 21 and fig. 22 illustrate schematic cross-sectional views of the NMOS region 110N and the PMOS region 110P, that is, fig. 21 and fig. 22 may be used to characterize any one of the NMOS region 111P and the second PMOS region 112P, and any one of the PMOS region 111N and the second NMOS region 112N.

Referring to fig. 23, fig. 23 is a schematic cross-sectional view of fig. 22, the gate structure 130 is removed (as shown in fig. 22), and a gate opening 105 is formed in the interlayer dielectric layer 102.

The gate opening 105 is used to provide a spatial location for the formation of a subsequent metal gate structure. In this embodiment, the gate opening 105 spans across the fin 120 and exposes a portion of the top and a portion of the sidewall of the fin 120.

Referring to fig. 24 and 25 in combination, fig. 24 is a schematic cross-sectional view based on fig. 23, and fig. 25 is an enlarged view of a dashed box a and a dashed box B in fig. 24, and a high-k gate dielectric layer 510 is formed on the bottom and sidewalls of the gate opening 105 (shown in fig. 23); forming a work function layer (not labeled) on the high-k gate dielectric layer 510; a gate electrode layer 550 is formed within the gate opening 105 where the work function layer is formed, and the high-k gate dielectric layer 510, work function layer and gate electrode layer 550 are used to form a metal gate structure 500 (as shown in fig. 25).

The material of the high-k gate dielectric layer 510 is a high-k gate dielectric material, where the high-k gate dielectric material refers to a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer 510 is HfO ₂ . In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zrO ₂ Or Al ₂ O ₃ 。

In this embodiment, the work function layer of the PMOS region 110P is a P-type work function layer 530, and the P-type work function layer 530 is used to adjust the threshold voltages of the PMOS devices. In particular, the P-type work function layer 530 is used to adjust the threshold voltages of P-type low threshold voltage devices and P-type standard threshold voltage devices.

Correspondingly, the P-type work function layer 530 is made of P-type work function material. The P-type work function layer 530 has a material work function in the range of 5.1ev to 5.5ev, for example, 5.2ev, 5.3ev, or 5.4ev; the P-type work function layer 530 is made of one or more of TiN, taN, taSiN, tiSiN, taAlN and TiAlN. In this embodiment, the P-type work function layer 530 is made of TiN.

Specifically, the step of forming the P-type work function layer 530 includes: forming a P-type work function material layer on the high-k gate dielectric layer 510 of the PMOS region 110P and the NMOS region 110N; forming a fifth photoresist layer (not shown) on the P-type work function material layer of the PMOS region 110P, the fifth photoresist layer exposing the P-type work function material layer of the NMOS region 110N; etching to remove the P-type work function material layer of the NMOS region 110N by using the fifth photoresist layer as a mask, and reserving the P-type work function material layer of the PMOS region 110P as the P-type work function layer 530; and removing the fifth photoresist layer by adopting a wet photoresist removing or ashing process.

The thickness of the P-type work function layer 530, the minimum distance D1 (shown in fig. 14) from the sidewall of the first P-region recess 151 (shown in fig. 14) to the sidewall of the adjacent gate structure 130, and the minimum distance D2 (shown in fig. 15) from the sidewall of the second P-region recess 152 (shown in fig. 15) to the sidewall of the adjacent gate structure 130 are matched with each other, so that the threshold voltage of each PMOS device is ensured to meet the process requirements on the basis of the process being achievable. In this embodiment, the thickness of the P-type work function layer 530 is

To->

In this embodiment, the work function layer of the NMOS region 110N is an N-type work function layer 540, and the N-type work function layer 540 is used to adjust the threshold voltage of the NMOS device. In particular, the N-type work function layer 540 is used to adjust the threshold voltages of N-type standard threshold voltage devices and N-type low threshold voltage devices.

Accordingly, the material of the N-type work function layer 540 is an N-type work function material. The material work function of the N-type work function layer 540 ranges from 3.9ev to 4.5ev, for example, 4ev, 4.1ev, or 4.3ev; the material of the N-type work function layer 540 is one or more of TiAl, mo, moN, alN and TiAlC. In this embodiment, the material of the N-type work function layer 540 is TiAl.

The thickness of the N-type work function layer 540, the minimum distance D5 (shown in fig. 18) from the sidewall of the first N-region groove 153 (shown in fig. 18) to the sidewall of the adjacent gate structure 130, and the minimum distance D6 (shown in fig. 19) from the sidewall of the second N-region groove 154 (shown in fig. 19) to the sidewall of the adjacent gate structure 130 are matched with each other, so that the threshold voltage of each NMOS device is ensured to meet the process requirement on the basis of the process being achievable. In this embodiment, the N-type work function layer 540 has a thickness of

To->

Specifically, the step of forming the N-type work function layer 540 includes: the N-type work function layer 540 is formed on the high-k gate dielectric layer 510 of the NMOS region 110N, the N-type work function layer 540 also covering the P-type work function layer 530.

In this embodiment, in order to reduce the process steps and save the mask, after the N-type work function layer 540 is formed, the N-type work function layer 540 located in the PMOS region 110P is remained, i.e. the N-type work function layer 540 also covers the P-type work function layer 530.

Accordingly, the step of forming the gate electrode layer 550 includes: the gate electrode layer 550 is formed on the N-type work function layer 540, and the gate electrode layer 550 is filled in the gate opening 105. In this embodiment, the material of the gate electrode layer 550 is W. In other embodiments, the material of the gate electrode layer may also be a conductive material such as Al, cu, ag, au, pt, ni or Ti.

It should be noted that, before forming the P-type work function layer 530 and the N-type work function layer 540, the method further includes: a cap layer 520 is formed on the high-k gate dielectric layer 510.

The cap layer 520 may serve to protect the high-k gate dielectric layer 510 from damage caused by subsequent processes to the high-k gate dielectric layer 510, and the cap layer 520 may also be beneficial to blocking diffusion of easily-diffused ions in the gate electrode layer 550 into the high-k gate dielectric layer 510. In this embodiment, the capping layer is made of TiN. In other embodiments, the capping layer material may also be TiSiN.

Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 24 and 25 in combination, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown, fig. 24 is a schematic sectional view of a PMOS region and an NMOS region along a fin extension direction (as shown in an X1X2 direction in fig. 8), and fig. 25 is an enlarged view of a dashed line box a and a dashed line box B in fig. 24.

With continued reference to fig. 24 and 25, and with reference to fig. 16 and 20, the semiconductor structure includes: a substrate 100 (shown in fig. 8), the substrate 100 including a device region (not shown), the type of the device region including one or both of an NMOS region 110N (shown in fig. 24) and a PMOS region 110P (shown in fig. 24), the same type of the device region having devices formed with different threshold voltages, respectively; a metal gate structure 500 on the substrate 100; source and drain doped layers (not shown) are located in the substrate 100 at two sides of the metal gate structure 500, and in the same type of device region, the minimum distances (not shown) from the sidewalls of the source and drain doped layers corresponding to different threshold voltages to the sidewalls of the adjacent metal gate structure 500 are different along the direction perpendicular to the sidewalls of the metal gate structure 500.

In this embodiment, the semiconductor structure is a finfet, so the base 100 includes a substrate 110 and a plurality of discrete fins 120 on the substrate 110. In other embodiments, the semiconductor structure may also be a planar transistor, and the base is a substrate, respectively.

The device region types include one or both of an NMOS region 110N and a PMOS region 110P, the NMOS region 110N being formed with NMOS devices of different threshold voltages, the PMOS region 110P being formed with PMOS devices of different threshold voltages. In this embodiment, the device region types include an NMOS region 110N and a PMOS region 110P.

In this embodiment, the device regions of the same type include a first device region (not labeled) and a second device region (not labeled), the device threshold voltage of the first device region being less than the device threshold voltage of the second device region.

Specifically, the first device region in the NMOS region 110N is a first NMOS region 111N (as shown in fig. 20), the second device region in the NMOS region 110N is a second NMOS region 112N (as shown in fig. 20), the first device region in the PMOS region 110P is a first PMOS region 111P (as shown in fig. 16), the second device region in the PMOS region 110P is a second PMOS region 112P (as shown in fig. 16), the device threshold voltage of the first NMOS region 111N is smaller than the device threshold voltage of the second NMOS region 112N, and the device threshold voltage of the first PMOS region 111P is smaller than the device threshold voltage of the second PMOS region 112P.

It should be further noted that, for convenience of illustration, fig. 24 and 25 illustrate schematic cross-sectional views of the NMOS region 110N and the PMOS region 110P, that is, fig. 24 and 25 may be used to characterize either one of the first PMOS region 111P and the second PMOS region 112P, and either one of the first NMOS region 111N and the second NMOS region 112N.

Further, with continued reference to fig. 24, the semiconductor structure further includes: and the isolation structure 101 is positioned on the substrate 110 exposed by the fin 120, the isolation structure 101 covers part of the side wall of the fin 120, and the top of the isolation structure 101 is lower than the top of the fin 120.

The semiconductor structure further includes: the sidewall 140 (as shown in fig. 24) is located on the sidewall of the metal gate structure 500. The side wall 140 is used for defining the forming positions of the PMOS region 110P source drain doped layer and the NMOS region 110N source drain doped layer.

The source-drain doped layers are located in the fin portions 120 at two sides of the metal gate structure 500, wherein minimum distances from the sidewalls of the source-drain doped layers to the sidewalls of the adjacent metal gate structure 500 corresponding to different threshold voltages are different along the direction perpendicular to the sidewalls of the metal gate structure 500 in the same type of device region (not labeled).

In the device region (not labeled) of the same type, the smaller the minimum distance from the sidewall of the source-drain doped layer to the sidewall of the adjacent metal gate structure 500 is, the smaller the external parasitic resistance of the device is, and the smaller the threshold voltage of the device is correspondingly, so that the adjustment of the threshold voltage of each device can be realized by adjusting the minimum distance from the sidewall of each source-drain doped layer in the device region of the same type to the sidewall of the adjacent metal gate structure 500.

In the semiconductor process, in the device region of the same type, the minimum distance from the side wall of each source/drain doped layer to the side wall of the adjacent metal gate structure 500 is generally equal, and the threshold voltage of each device meets the process requirement by adjusting the thickness of the work function layer of each region. In this embodiment, by adjusting the minimum distance between the sidewalls of the source/drain doped layers in the device regions of the same type and the sidewalls of the adjacent metal gate structure 500, it is easy to adjust the threshold voltages of devices respectively, and the device regions of the same type can share the same work function layer, so that the process steps for forming the work function layer are simplified correspondingly, the times of photolithography, etching, ashing and cleaning processes are reduced, thereby reducing the adverse effect of the process for forming the work function layer on the device performance, and avoiding the cross effect of threshold voltage adjustment of any device on other devices.

In this embodiment, the device region includes an NMOS region 110N and a PMOS region 110P, and accordingly, by adjusting the distance, it is also convenient to adjust threshold voltages of the PMOS device and the NMOS device respectively, so as to prevent cross influence between the PMOS device and the NMOS device.

In this embodiment, since the device threshold voltage of the first device region is smaller than the device threshold voltage of the second device region, the minimum distance between the source-drain doped layer of the first device region and the sidewall of the adjacent metal gate structure 500 is smaller than the minimum distance between the source-drain doped layer of the second device region and the sidewall of the adjacent metal gate structure 500.

Specifically, the source-drain doped layer 160 in the PMOS region 110P is a P-type source-drain doped layer 160, and the minimum distance D3 (shown in fig. 16) between the P-type source-drain doped layer 160 in the first PMOS region 111P and the sidewall of the adjacent gate structure 130 is smaller than the minimum distance D4 (shown in fig. 16) between the P-type source-drain doped layer 160 in the second PMOS region 112P and the sidewall of the adjacent gate structure 130, so that the threshold voltage of the device formed in the first PMOS region 111P is smaller.

In this embodiment, the P-type source/drain doped layer 160 is U-shaped. The process of forming the P-type source-drain doped layer 160 generally includes an etching process, which is advantageous to reduce the effect of the etching process on the device channel region, since the sidewalls of the P-type source-drain doped layer 160 are perpendicular to the surface of the substrate 110. In other embodiments, the P-type source-drain doped layer may also have a bowl shape or Sigma shape.

The minimum distance between the P-type source/drain doped layer 160 and the sidewall of the adjacent metal gate structure 500 should not be too large, otherwise, the distance between the P-type source/drain doped layer 160 and the metal gate structure 500 may be too large, which may easily adversely affect the performance and yield of the device. For this reason, in this embodiment, in order to reduce the process risk and reduce the influence on the device channel, the minimum distance between the P-type source/drain doped layer 160 and the sidewall of the adjacent metal gate structure 500 is

To->

Wherein when the minimum distance is +.>

The sidewalls of the P-type source drain doped layer 160 are then characterized as being flush with the sidewalls of the adjacent metal gate structure 500.

Therefore, in the present embodiment, the minimum distance D3 between the P-type source/drain doped layer 160 of the first PMOS region 111P and the sidewall of the adjacent metal gate structure 500 is

To->

The minimum distance D4 between the P-type source/drain doped layer 160 of the second PMOS region 112P and the sidewall of the adjacent metal gate structure 500 is +.>

To->

And by reasonably setting the minimum distance D3 between the P-type source-drain doped layer 160 of the first PMOS region 111P and the sidewall of the adjacent metal gate structure 500 and the minimum distance D4 between the P-type source-drain doped layer 160 of the second PMOS region 112P and the sidewall of the adjacent metal gate structure 500, on the basis of realizing the process, the threshold voltages of the devices in the first PMOS region 111P and the second PMOS region 112P can meet the process requirements, and at the same time, the PMOS region 110P (as shown in fig. 8) can share the same work function layer, and the threshold voltages of other devices in the PMOS region 110P can also meet the process requirements.

In other embodiments, when the P-type source-drain doped layer is bowl-shaped or Sigma-shaped, in order to reduce the process risk and reduce the influence on the device channel, the minimum distance between the sidewall of the P-type source-drain doped layer and the sidewall of the adjacent metal gate structure is

To->

And when the minimum distance is a negative value, the side wall of the P-type source-drain doped layer is characterized to be positioned below the adjacent metal gate structure, namely, the projection of the P-type source-drain doped layer on the substrate is overlapped with the projection of the adjacent metal gate structure on the substrate.

The P-type source/drain doped layer 160 includes a first epitaxial layer (not shown) doped with P-type ions.

In this embodiment, the P-type ion is a B ion. In other embodiments, the P-type ions may also be Ga ions or In ions.

The material of the first epitaxial layer is SiGe, geSn or GeSb, and the first epitaxial layer provides a compressive stress effect for the device channel region of the PMOS region 110P, so as to improve the carrier mobility of the PMOS region 110P. In this embodiment, the material of the first epitaxial layer is SiGe, so the material of the P-type source/drain doped layer 160 is SiGe doped with B ions, i.e., the material of the P-type source/drain doped layer 160 is SiGeB.

It should be noted that, in the P-type source-drain doped layer 160, the higher the doping concentration of P-type ions, the more obvious the P-type source-drain doped layer 160 correspondingly plays a role of providing pressure stress; however, in the semiconductor process, the semiconductor structure generally further includes a metal silicide layer on the P-type source/drain doped layer 160, and a contact plug on the metal silicide layer and electrically connected to the metal silicide layer, where the doping concentration of P-type ions is too high, which may cause a problem of too high contact resistance.

Therefore, in order to reduce the contact resistance while ensuring the compressive stress effect of the P-type source-drain doped layer 160, the P-type source-drain doped layer 160 includes: a bottom P-type source-drain doped layer 161 (as shown in fig. 16) and a top P-type source-drain doped layer 162 (as shown in fig. 16) on the bottom P-type source-drain doped layer 161.

In this embodiment, the top of the P-type source/drain doped layer 160 is higher than the top of the fin 120. In other embodiments, the top of the P-type source-drain doped layer may be flush with the top of the fin.

Specifically, the source-drain doped layer located in the NMOS region 110N is an N-type source-drain doped layer 180, and the minimum distance D8 (shown in fig. 20) between the N-type source-drain doped layer 180 of the first NMOS region 111N (shown in fig. 20) and the sidewall of the adjacent metal gate structure 500 is smaller than the minimum distance D8 (shown in fig. 20) between the N-type source-drain doped layer 180 of the second NMOS region 112N (shown in fig. 20) and the sidewall of the adjacent metal gate structure 500, so that the threshold voltage of the device formed in the first NMOS region 111N is smaller.

In this embodiment, the N-type source-drain doped layer 180 is U-shaped. In other embodiments, the N-type source-drain doped layer may also have a bowl shape or Sigma shape.

In this embodiment, in order to reduce adverse effects on device performance and yield and reduce effects on device channels, the minimum distance between the N-type source/drain doped layer 180 and the sidewall of the adjacent metal gate structure 500 is

To->

Wherein when the minimum distance is +.>

The sidewalls of the N-type source-drain doped layer 180 are then characterized as being flush with the sidewalls of the adjacent metal gate structure 500.

Therefore, in this embodiment, the minimum distance D7 between the N-type source/drain doped layer 180 of the first NMOS region 111N and the sidewall of the adjacent metal gate structure 500 is

To->

The minimum distance D8 between the N-type source/drain doped layer 180 of the second NMOS region 112N and the sidewall of the adjacent metal gate structure 500 is +.>

To->

And by reasonably setting the minimum distance D7 between the N-type source-drain doped layer 180 of the first NMOS region 111N and the sidewall of the adjacent metal gate structure 500 and the minimum distance D8 between the N-type source-drain doped layer 180 of the second NMOS region 112N and the sidewall of the adjacent metal gate structure 500, on the basis that the process can be realized, the threshold voltages of the devices in the first NMOS region 111N and the second NMOS region 112N can be ensured to meet the process requirements, and simultaneously, the NMOS region 110N (as shown in fig. 8) can be ensured to share the same work function layer, and the threshold voltages of other devices in the NMOS region 110N can also meet the process requirements.

In other embodiments, when the N-type source-drain doped layer is bowl-shaped or Sigma-shaped, in order to reduce the process risk and reduce the influence on the device channel, the minimum distance between the sidewall of the N-type source-drain doped layer and the sidewall of the adjacent metal gate structure is

To->

For a specific description of the N-type source-drain doped layer 180, reference may be made to the foregoing corresponding description of the P-type source-drain doped layer 160, which is not repeated herein.

The N-type source/drain doped layer 180 includes a second epitaxial layer (not shown) doped with N-type ions.

In this embodiment, the N-type ions are P ions. In other embodiments, the N-type ions may also be Ga ions or In ions.

The second epitaxial layer is made of Si or SiC, and provides a compressive stress effect for the device channel region of the NMOS region 110N, so as to improve carrier mobility of the NMOS region 110N. In this embodiment, the material of the second epitaxial layer is Si, so the material of the N-type source-drain doped layer 180 is Si doped with P ions, i.e., the material of the N-type source-drain doped layer 180 is SiP.

The metal gate structure 500 spans across the fin 120 and covers a portion of the top and a portion of the sidewalls of the fin 120. Specifically, the metal gate structure 500 includes a high-k gate dielectric layer 510 (shown in fig. 25) on the substrate 100, a work function layer (not labeled) on the high-k gate dielectric layer 510, and a gate electrode layer 550 (shown in fig. 24 or 25) on the work function layer.

In this embodiment, the work function layer of the PMOS region 110P is a P-type work function layer 530, and the P-type work function layer 530 is used to adjust the threshold voltage of the PMOS device. In particular, the P-type work function layer 530 is used to adjust the threshold voltages of P-type low threshold voltage devices and P-type standard threshold voltage devices.

The P-type work function layer 530, the minimum distance D3 between the P-type source-drain doped layer 160 of the first PMOS region 111P and the sidewall of the adjacent metal gate structure 500, and the minimum distance D4 between the P-type source-drain doped layer 160 of the second PMOS region 112P and the sidewall of the adjacent metal gate structure 500, so that the threshold voltage of each PMOS device is ensured to meet the process requirement on the basis of being realized by the process. In this embodiment, the thickness of the P-type work function layer 530 is

To->

The thickness of the N-type work function layer 540, the minimum distance D7 between the N-type source/drain doped layer 180 of the first NMOS region 111N and the sidewall of the adjacent metal gate structure 500, and the minimum distance D8 between the N-type source/drain doped layer 180 of the second NMOS region 112N and the sidewall of the adjacent metal gate structure 500 are matched with each other, so that the threshold voltage of each NMOS device is ensured to meet the process requirements on the basis of the process being realizable. In this embodiment, the N-type work function layer 540 has a thickness of

To->

In the process of forming the semiconductor structure, in order to reduce the process steps and save the mask, the N-type work function layer 540 located in the PMOS region 110P is remained when the N-type work function layer 540 is formed, so that the N-type work function layer 540 also covers the P-type work function layer 530.

Thus, the metal gate structure 500 of the PMOS region 110P includes a high-k gate dielectric layer 510 on the substrate 100, a P-type work function layer 530 on the high-k gate dielectric layer 510, an N-type work function layer 540 on the P-type work function layer 530, and a gate electrode layer 550 on the N-type work function layer 540; the metal gate structure 500 of the NMOS region 110N includes a high-k gate dielectric layer 510 on the substrate 100, an N-type work function layer 540 on the high-k gate dielectric layer 510, and a gate electrode layer 550 on the N-type work function layer 540.

In this embodiment, the material of the gate electrode layer 550 is W. In other embodiments, the material of the gate electrode layer may also be a conductive material such as Al, cu, ag, au, pt, ni or Ti.

It should also be noted that the semiconductor structure further includes: the cap layer 520 is located between the high-k gate dielectric layer 510 and the P-type work function layer 530 of the PMOS region 110P and between the high-k gate dielectric layer 510 and the N-type work function layer 540 of the NMOS region 110N.

The cap layer 520 may serve to protect the high-k gate dielectric layer 510 from damage to the high-k gate dielectric layer 510, and the cap layer 520 may also be beneficial to block diffusion of easily-diffused ions in the gate electrode layer 550 into the high-k gate dielectric layer 510. In this embodiment, the capping layer is made of TiN. In other embodiments, the capping layer material may also be TiSiN.

It should be noted that the semiconductor structure further includes: and the side wall 140 is positioned on the side wall of the metal gate structure 500. The side walls 140 are used for defining the forming positions of the P-type source-drain doped layer 160 and the N-type source-drain doped layer 180.

In this embodiment, the semiconductor structure further includes: and the interlayer dielectric layer 102 is positioned on the substrate 110 exposed by the metal gate structure 500, and the interlayer dielectric layer 102 covers the side wall of the metal gate structure 500. The interlayer dielectric layer 102 is used to achieve electrical isolation between adjacent devices, and the interlayer dielectric layer 102 is also used to define the size and location of the metal gate structure 500.

In this embodiment, the top of the interlayer dielectric layer 102 is flush with the top of the metal gate structure 500. Accordingly, the gate electrode layer 550 is located within the interlayer dielectric layer 102, and the high-k gate dielectric layer 510 is located between the interlayer dielectric layer 102 and the gate electrode layer 550, and the substrate 100 and the gate electrode layer 550.

The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a device region, the type of the device region comprises one or two of an NMOS region and a PMOS region, and the device region of the same type is used for forming devices with different threshold voltages;

Forming a gate structure on the substrate;

forming grooves in substrates at two sides of the grid structure, wherein in the device region of the same type, along the direction perpendicular to the side walls of the grid structure, the opening sizes of the grooves corresponding to different threshold voltages are different, so that the minimum distances from the side walls of the grooves corresponding to different threshold voltages to the side walls of the adjacent grid structures are different;

and forming a source-drain doping layer in the groove.

2. The method of forming a semiconductor structure of claim 1, wherein in the step of forming a gate structure on the substrate, the gate structure is a dummy gate structure;

the forming method further includes: forming an interlayer dielectric layer on the substrate exposed by the pseudo gate structure, wherein the interlayer dielectric layer covers the source-drain doping layer, and the interlayer dielectric layer is exposed out of the top of the pseudo gate structure; removing the pseudo gate structure and forming a gate opening in the interlayer dielectric layer; forming a high-k gate dielectric layer on the bottom and the side wall of the gate opening; forming a work function layer on the high-k gate dielectric layer; and forming a gate electrode layer in the gate opening formed with the work function layer, wherein the high-k gate dielectric layer, the work function layer and the gate electrode layer are used for forming a metal gate structure.

3. The method of forming a semiconductor structure of claim 2, wherein the device region comprises a PMOS region, the work function layer of the PMOS region being a P-type work function layer having a thickness of

To->

The device region comprises an NMOS region, wherein the work function layer of the NMOS region is an N-type work function layer, and the N-type work function layer is a silicon nitride layerThe thickness of the layers is->

To the point of

4. The method of forming a semiconductor structure of claim 1, wherein in the step of forming grooves in the substrate on both sides of the gate structure, the grooves are U-shaped, bowl-shaped or Sigma-shaped.

5. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming grooves in the substrate on both sides of the gate structure, the grooves are U-shaped, and the minimum distance between the groove sidewalls and the adjacent gate structure sidewalls is

To->

Or,

the shape of the groove is bowl-shaped or Sigma-shaped, and the minimum distance from the side wall of the groove to the side wall of the adjacent grid structure is-

To->

6. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the device regions of the same type comprise a first device region and a second device region, the first device region having a device threshold voltage that is less than a device threshold voltage of the second device region;

In the step of forming grooves in the substrate at two sides of the gate structure, the groove formed in the first device region is a first groove, the groove formed in the second device region is a second groove, and the minimum distance from the side wall of the first groove to the side wall of the adjacent gate structure is smaller than the minimum distance from the side wall of the second groove to the side wall of the adjacent gate structure.

7. The method of forming a semiconductor structure of claim 6, wherein the step of forming the first recess and the second recess comprises: performing first etching treatment on the substrates at two sides of the grid structure of the first device region, and forming the first groove in the substrates at two sides of the grid structure of the first device region; performing second etching treatment on the substrates at two sides of the grid structure of the second device region, and forming the second grooves in the substrates at two sides of the grid structure of the second device region;

or,

the step of forming the first and second grooves includes: performing first etching treatment on the substrates at two sides of the grid structure of the first device region, and forming initial grooves in the substrates at two sides of the grid structure of the first device region; and carrying out second etching treatment on the substrate at two sides of the grid structure of the second device region and the initial groove, forming a second groove in the substrate at two sides of the grid structure of the second device region, wherein the initial groove after the second etching treatment is the first groove.

8. The method of forming a semiconductor structure of claim 6, wherein in the step of providing a substrate, the device regions are of a type including an NMOS region and a PMOS region, a first device region of the NMOS region being a first NMOS region, a second device region of the NMOS region being a second NMOS region, a first device region of the PMOS region being a first PMOS region, and a second device region of the PMOS region being a second PMOS region;

the first PMOS region is a P-type standard threshold voltage region, and the second PMOS region is a P-type low threshold voltage region;

the first NMOS region is an N-type standard threshold voltage region, and the second NMOS region is an N-type low threshold voltage region.

9. The method of forming a semiconductor structure of claim 1, wherein the process of forming the recess comprises a dry etching process, the carrier gas of the dry etching process comprising Ar, O ₂ 、N ₂ He and H ₂ One or more of the dry etching process, wherein the etching gas comprises HBr, cl2, HCl and SO ₂ 、CF ₄ 、CHF ₃ 、CH ₂ F ₂ 、CH ₃ F. And CH (CH) ₄ One or more of the following.

10. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a base, the base is a substrate; alternatively, the base includes a substrate and a plurality of discrete fins on the substrate.

11. A semiconductor structure, comprising:

the substrate comprises a device region, wherein the type of the device region comprises one or two of an NMOS region and a PMOS region, and devices with different threshold voltages are respectively formed in the same type of the device region;

a metal gate structure located on the substrate;

the source-drain doped layers are positioned in the substrates at two sides of the metal gate structure, and in the device region of the same type, the widths of the source-drain doped layers corresponding to different threshold voltages are different along the direction perpendicular to the side walls of the metal gate structure, so that the minimum distances from the side walls of the source-drain doped layers corresponding to different threshold voltages to the side walls of the adjacent metal gate structures are different.

12. The semiconductor structure of claim 11, wherein the metal gate structure comprises a high-k gate dielectric layer on the substrate, a work function layer on the high-k gate dielectric layer, and a gate electrode layer on the work function layer.

13. The semiconductor structure of claim 12, wherein the device region comprises a PMOS region, the work function layer of the PMOS region being a P-type work function layer having a thickness of

To->

The device region comprises an NMOS region, wherein the work function layer of the NMOS region is an N-type work function layer, and the thickness of the N-type work function layer is +. >

To->

14. The semiconductor structure of claim 11, wherein the source-drain doped layer has a shape of a U, bowl, or Sigma.

15. The semiconductor structure of claim 11, wherein the source-drain doped layer has a U-shape and a minimum distance from a sidewall of the source-drain doped layer to a sidewall of an adjacent metal gate structure is

To the point of

Or the source-drain doped layer is bowl-shaped or Sigma-shaped, and the minimum distance from the side wall of the source-drain doped layer to the side wall of the adjacent metal gate structure is-

To->

16. The semiconductor structure of claim 11, wherein the device regions of the same type comprise a first device region and a second device region, the first device region having a device threshold voltage that is less than a device threshold voltage of the second device region;

and the minimum distance from the side wall of the source and drain doping layer of the first device region to the side wall of the adjacent metal gate structure is smaller than the minimum distance from the side wall of the source and drain doping layer of the second device region to the side wall of the adjacent metal gate structure.

17. The semiconductor structure of claim 16, wherein the device regions are of a type comprising an NMOS region and a PMOS region, a first device region of the NMOS region being a first NMOS region,

The second device region in the NMOS region is a second NMOS region, the first device region in the PMOS region is a first PMOS region, and the second device region in the PMOS region is a second PMOS region;

18. The semiconductor structure of claim 11, wherein the base is a substrate; alternatively, the base includes a substrate and a plurality of discrete fins on the substrate.