CN110620094A - Packaging structure and packaging process of power semiconductor device - Google Patents
Packaging structure and packaging process of power semiconductor device Download PDFInfo
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- CN110620094A CN110620094A CN201910969687.2A CN201910969687A CN110620094A CN 110620094 A CN110620094 A CN 110620094A CN 201910969687 A CN201910969687 A CN 201910969687A CN 110620094 A CN110620094 A CN 110620094A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 28
- 238000012858 packaging process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 108
- 230000017525 heat dissipation Effects 0.000 claims abstract description 61
- 239000000919 ceramic Substances 0.000 claims description 54
- 239000000463 material Substances 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 239000005022 packaging material Substances 0.000 claims 1
- 238000009434 installation Methods 0.000 abstract description 21
- 239000000969 carrier Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 description 7
- 238000010292 electrical insulation Methods 0.000 description 5
- 238000009421 internal insulation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000000338 in vitro Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
一种功率半导体器件的封装结构及其封装工艺，属于功率半导体器件封装技术领域，该功率半导体器件的封装结构，包括封装体以及封装体内部由芯片、键合线、电路载体、引脚组成的内部电路和散热基板，芯片与引脚通过键合线连接，内部电路通过电路载体与散热基板实现绝缘隔离，本发明的有益效果是，其中的封装结构实现了功率半导体器件的内部绝缘，省去了应用安装时需要加装绝缘片的环节，提高了作业效率及安装良率，而且提高了功率半导体器件的散热性能，该封装结构的封装工艺简单、具有实现规模化量产的可能，可提供性能较好、安装成本较低的功率半导体器件。
A packaging structure of a power semiconductor device and a packaging process thereof belong to the technical field of packaging of power semiconductor devices. The packaging structure of the power semiconductor device includes a package body and a package inside the package body composed of chips, bonding wires, circuit carriers and pins. The internal circuit and the heat-dissipating substrate, the chip and the pins are connected by bonding wires, and the internal circuit is insulated from the heat-dissipating substrate through the circuit carrier. It eliminates the need to install insulating sheets during application and installation, improves work efficiency and installation yield, and improves the heat dissipation performance of power semiconductor devices. Power semiconductor devices with better performance and lower installation cost.
Description
技术领域technical field
本发明涉及功率半导体器件封装技术领域，尤其涉及一种功率半导体器件的封装结构及其封装工艺。The invention relates to the technical field of power semiconductor device packaging, in particular to a packaging structure of a power semiconductor device and a packaging process thereof.
背景技术Background technique
目前对于大功率半导体器件的封装结构，大致分为两种，一种是封装体背部露散热基板的结构，另一种是全包封的结构，因大功率半导体器件发热量较大的特性，无论哪种封装结构，在其应用时都需要在背部加装散热器进行散热。At present, the packaging structure of high-power semiconductor devices is roughly divided into two types, one is the structure in which the heat dissipation substrate is exposed on the back of the package body, and the other is the fully encapsulated structure. Due to the large heat generation characteristics of high-power semiconductor devices, Regardless of the package structure, it is necessary to install a heat sink on the back to dissipate heat during its application.
如图1为封装体背部露散热基板的封装结构的侧视图，因其芯片2与本身的散热基板6连接，需在散热基板6的散热面与散热器之间加装绝缘片进行电气绝缘，保证其应用的绝缘性能，绝缘片在安装时，其位置及贴近程度也关系到绝缘效果的好坏，导致应用端安装难度加大，且绝缘片本身的导热性能一般在1-3W/mk之间，热量并不能在短时间内快速散出，热传输效果一般。如图2为全包封的封装结构的侧视图，因封装体1本身的绝缘性能，在安装散热器时就无需再加装绝缘片，该封装结构背面的封装体1厚度通常在0.4-0.6mm之间，塑封用的树脂材料导热系数一般为1-2W/mk，散热效果更差。因此，如何既能简化应用端安装工艺，又能提高产品散热性能，是本发明的研究方向。Figure 1 is a side view of the package structure with the heat dissipation substrate exposed on the back of the package body. Because the chip 2 is connected to its own heat dissipation substrate 6, an insulating sheet needs to be installed between the heat dissipation surface of the heat dissipation substrate 6 and the heat sink for electrical insulation. To ensure the insulation performance of its application, when the insulating sheet is installed, its position and closeness are also related to the insulation effect, which makes the installation of the application end more difficult, and the thermal conductivity of the insulating sheet itself is generally within 1-3W/mk. During this time, the heat cannot be dissipated quickly in a short time, and the heat transfer effect is average. Figure 2 is a side view of the fully encapsulated package structure. Due to the insulating performance of the package body 1 itself, there is no need to install an insulating sheet when installing the heat sink. The thickness of the package body 1 on the back of the package structure is usually 0.4-0.6 Between mm, the thermal conductivity of resin materials used for plastic packaging is generally 1-2W/mk, and the heat dissipation effect is worse. Therefore, how to not only simplify the application-side installation process, but also improve the heat dissipation performance of the product is the research direction of the present invention.
发明内容SUMMARY OF THE INVENTION
为了解决上述技术问题，本发明提供了一种功率半导体器件的封装结构，主要解决了现有的封装结构存在应用端安装难度大和散热效果差的问题，目的在于，通过设计一种新型的封装结构，既不需要在其背部安装绝缘片进行电气绝缘，简化了应用端的安装难度，又可以提高产品整体的散热性能。In order to solve the above technical problems, the present invention provides a packaging structure of a power semiconductor device, which mainly solves the problems of difficult installation at the application end and poor heat dissipation effect of the existing packaging structure. The purpose is to design a new packaging structure by designing a new packaging structure , it does not need to install an insulating sheet on the back for electrical insulation, which simplifies the installation difficulty of the application side, and can improve the overall heat dissipation performance of the product.
为实现上述目的，本发明解决其技术问题所采用的技术方案是：所述功率半导体器件的封装结构，包括封装体以及封装体内部由芯片、键合线、电路载体、引脚组成的内部电路和散热基板，所述芯片与引脚通过键合线连接，所述内部电路通过所述电路载体与所述散热基板实现绝缘隔离。In order to achieve the above purpose, the technical solution adopted by the present invention to solve the technical problem is: the package structure of the power semiconductor device includes a package body and an internal circuit composed of chips, bonding wires, circuit carriers and pins inside the package body. and a heat-dissipating substrate, the chip and the pins are connected by bonding wires, and the internal circuit is insulated and isolated from the heat-dissipating substrate through the circuit carrier.
进一步地，所述电路载体设置为双面覆铜陶瓷基板，所述双面覆铜陶瓷基板包括陶瓷基板和所述陶瓷基板两面分别烧结的铜板，所述陶瓷基板的两面铜板分别通过结合材与芯片和散热基板相连。Further, the circuit carrier is configured as a double-sided copper-clad ceramic substrate, and the double-sided copper-clad ceramic substrate includes a ceramic substrate and a copper plate sintered on both sides of the ceramic substrate respectively, and the copper plates on both sides of the ceramic substrate are respectively connected with each other through a bonding material. The chip is connected to the heat dissipation substrate.
进一步地，所述结合材设置为焊锡材料。Further, the bonding material is set as a solder material.
进一步地，所述双面覆铜陶瓷基板背面设置散热基板，所述双面覆铜陶瓷基板通过其中的陶瓷基板与所述散热基板实现绝缘隔离。Further, a heat dissipation substrate is arranged on the back of the double-sided copper-clad ceramic substrate, and the double-sided copper-clad ceramic substrate is insulated from the heat dissipation substrate through the ceramic substrate therein.
进一步地，所述散热基板与引脚设置为一体式框架结构，所述引脚穿出所述封装体外。Further, the heat dissipation substrate and the pins are arranged in an integrated frame structure, and the pins pass out of the package body.
进一步地，所述引脚沿其长度方向设置有将塑封材料聚集的环形塑封槽。Further, the pins are provided with annular molding grooves along the length direction of the pins for collecting molding materials.
进一步地，所述双面覆铜陶瓷基板设置在所述散热基板的中部，且所述双面覆铜陶瓷基板的边缘与所述散热基板的边缘之间在水平方向的距离大于0.8mm。Further, the double-sided copper-clad ceramic substrate is disposed in the middle of the heat dissipation substrate, and the distance in the horizontal direction between the edge of the double-sided copper-clad ceramic substrate and the edge of the heat dissipation substrate is greater than 0.8 mm.
一种所述的功率半导体器件的封装结构的封装工艺，包括以下步骤：A packaging process for the packaging structure of a power semiconductor device, comprising the following steps:
1)通过结合材将所述双面覆铜陶瓷基板的底层焊接在所述散热基板上；1) Welding the bottom layer of the double-sided copper-clad ceramic substrate on the heat dissipation substrate through a bonding material;
2)通过结合材将所述芯片焊接在双面覆铜陶瓷基板上层；2) Welding the chip on the upper layer of the double-sided copper-clad ceramic substrate through the bonding material;
3)将芯片通过键合线与所述引脚进行电气连接；3) the chip is electrically connected to the pin through the bonding wire;
4)将连接好的芯片、双面覆铜陶瓷基板、散热基板、引脚放置在注塑模具内塑封形成封装体，同时使散热基板的背面露出所述封装体，使引脚伸出所述封装体外。4) Place the connected chip, double-sided copper-clad ceramic substrate, heat-dissipating substrate, and pins in an injection mold to form a package, and at the same time expose the back of the heat-dissipating substrate to the package, so that the pins extend out of the package in vitro.
本发明的有益效果是：The beneficial effects of the present invention are:
1、该封装结构设置为封装体背部露散热基板的结构，通过在内部电路里设置电路载体，通过电路载体将内部电路和散热基板进行绝缘隔离，实现了功率半导体器件的内部绝缘，省去了应用安装时需要加装绝缘片的环节，提高了作业效率及安装良率，而且通过将散热基板外露的方式可将热量及时散出，提高了散热性能。1. The package structure is set to a structure in which the heat dissipation substrate is exposed on the back of the package body. By arranging a circuit carrier in the internal circuit, the internal circuit and the heat dissipation substrate are insulated and isolated by the circuit carrier, so as to realize the internal insulation of the power semiconductor device, eliminating the need for It is necessary to add insulating sheets during application installation, which improves the operation efficiency and installation yield, and the heat can be dissipated in time by exposing the heat dissipation substrate, which improves the heat dissipation performance.
2、具体地，其中的电路载体设置为双面覆铜陶瓷基板，双面覆铜陶瓷基板的两面铜板通过结合材分别与芯片和散热基板焊接相连，该双面覆铜陶瓷基板中的陶瓷基板的散热系数导热系数可达到20W/mk，散热性能好，且陶瓷基板本身为绝缘材料，把双面覆铜陶瓷基板应用在功率半导体器件的封装上，不但提高了产品本身的散热性能，提升了功率半导体器件本身导热与绝缘耐压能力，同时避免了功率半导体器件绝缘失效的风险，还实现了产品内部电路与散热基板之间的电气绝缘，进而降低了功率半导体器件应用端的安装难度。2. Specifically, the circuit carrier is set as a double-sided copper-clad ceramic substrate, and the two-sided copper plates of the double-sided copper-clad ceramic substrate are respectively welded and connected to the chip and the heat dissipation substrate through the bonding material. The ceramic substrate in the double-sided copper-clad ceramic substrate The thermal conductivity can reach 20W/mk, the heat dissipation performance is good, and the ceramic substrate itself is an insulating material. The application of the double-sided copper-clad ceramic substrate to the packaging of power semiconductor devices not only improves the heat dissipation performance of the product itself, but also improves the The thermal conductivity and insulation withstand voltage capability of the power semiconductor device itself, while avoiding the risk of insulation failure of the power semiconductor device, also realizes the electrical insulation between the internal circuit of the product and the heat dissipation substrate, thereby reducing the installation difficulty of the power semiconductor device application side.
3、具体地，由于该封装结构整体结构简单，其封装工艺也比较简单，同时也具有实现规模化量产的可能，可提供性能较好、安装成本较低的功率半导体器件。3. Specifically, because the overall structure of the package structure is simple, the packaging process is also relatively simple, and it is also possible to achieve large-scale mass production, which can provide power semiconductor devices with better performance and lower installation costs.
综上，本发明提供了一种新型的封装结构及其封装工艺，该封装结构实现了功率半导体器件的内部绝缘，省去了应用安装时需要加装绝缘片的环节，提高了作业效率及安装良率，而且提高了功率半导体器件的散热性能，该封装结构的封装工艺简单、具有实现规模化量产的可能，可提供性能较好、安装成本较低的功率半导体器件。To sum up, the present invention provides a new type of packaging structure and packaging process, which realizes the internal insulation of the power semiconductor device, saves the need to install an insulating sheet during application and installation, and improves the operation efficiency and installation. The yield rate is improved, and the heat dissipation performance of the power semiconductor device is improved. The packaging structure of the packaging structure has a simple packaging process, has the possibility of realizing large-scale mass production, and can provide a power semiconductor device with better performance and lower installation cost.
附图说明Description of drawings
下面对本发明说明书各幅附图表达的内容及图中的标记作简要说明：Below is a brief description of the content expressed in each of the drawings in the description of the present invention and the marks in the drawings:
图1为现有技术中一种封装结构的结构示意图；1 is a schematic structural diagram of a packaging structure in the prior art;
图2为现有技术中另一种封装结构的结构示意图；2 is a schematic structural diagram of another packaging structure in the prior art;
图3为本发明的封装结构的结构示意图；3 is a schematic structural diagram of the packaging structure of the present invention;
上述图中的标记均为：1.封装体，2.芯片，3.键合线，4.电路载体，41.陶瓷基板，42.铜板，5.引脚，51.环形塑封槽，6.散热基板。The marks in the above figures are: 1. Package body, 2. Chip, 3. Bonding wire, 4. Circuit carrier, 41. Ceramic substrate, 42. Copper plate, 5. Pin, 51. Ring-shaped plastic sealing groove, 6. heat sink.
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对实施例中的技术方案进行清楚、完整地描述，以下实施例用于说明本发明，但不用来限制本发明的范围。In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and the following embodiments are used to illustrate the present invention , but are not intended to limit the scope of the present invention.
在本发明的描述中，需要说明的是，术语“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。In the description of the present invention, it should be noted that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limiting the invention.
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。In the description of the present invention, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection or electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.
本发明具体的实施方案为：如图3所示，为本发明中功率半导体器件的封装结构的侧视图，该封装结构为左右对称结构，该封装结构包括封装体1以及封装体1内部由芯片2、键合线3、电路载体4、引脚5组成的内部电路和散热基板6，芯片2与引脚5通过键合线3连接，内部电路通过电路载体4与散热基板6实现绝缘隔离。该封装结构设置为封装体1背部露散热基板6的结构，通过在内部电路里设置电路载体4，通过电路载体4将内部电路和散热基板6进行绝缘隔离，实现了功率半导体器件的内部绝缘，省去了应用安装时需要加装绝缘片的环节，提高了作业效率及安装良率，而且通过将散热基板6外露的方式可将热量及时散出，提高了散热性能。The specific embodiment of the present invention is as follows: as shown in FIG. 3 , which is a side view of the package structure of the power semiconductor device in the present invention, the package structure is a left-right symmetrical structure, and the package structure includes a package body 1 and a chip inside the package body 1 . 2. Internal circuit composed of bonding wire 3, circuit carrier 4, and pin 5 and heat dissipation substrate 6. Chip 2 and pin 5 are connected by bonding wire 3, and the internal circuit is insulated from heat dissipation substrate 6 through circuit carrier 4. The package structure is set to a structure in which the heat dissipation substrate 6 is exposed on the back of the package body 1. By arranging a circuit carrier 4 in the internal circuit, the internal circuit and the heat dissipation substrate 6 are insulated and isolated by the circuit carrier 4, so as to realize the internal insulation of the power semiconductor device. The process of installing an insulating sheet during application and installation is omitted, the operation efficiency and the installation yield are improved, and the heat can be dissipated in time by exposing the heat dissipation substrate 6, thereby improving the heat dissipation performance.
具体地，该电路载体4设置为双面覆铜陶瓷基板，该双面覆铜陶瓷基板为一体式结构，包括陶瓷基板41和陶瓷基板41两面分别烧结的铜板42，陶瓷基板41的两面铜板42分别通过锡膏、锡片或锡线等焊锡材料组成的结合材与芯片2和散热基板6焊接相连，其中的陶瓷基板41为陶瓷材料，其散热系数可达到20W/mk，与现有技术中的绝缘片和塑封用的树脂材料相比，陶瓷基板41的散热系数高，散热性能好，且陶瓷基板41本身为绝缘材料，实现了产品内部电路与散热基板之间的电气绝缘，进而降低了功率半导体器件应用端的安装难度。把双面覆铜陶瓷基板应用在功率半导体器件的封装上，不但提高了产品本身的散热性能，提升了功率半导体器件本身导热与绝缘耐压能力，同时避免了功率半导体器件绝缘失效的风险，还实现了产品内部电路与散热基板之间的电气绝缘，解决了本领域技术人员一直想解决却未解决的问题。Specifically, the circuit carrier 4 is configured as a double-sided copper-clad ceramic substrate, and the double-sided copper-clad ceramic substrate has an integrated structure, including a ceramic substrate 41 and a copper plate 42 sintered on both sides of the ceramic substrate 41 respectively, and the two-sided copper plate 42 of the ceramic substrate 41 The chip 2 and the heat dissipation substrate 6 are welded and connected to the chip 2 and the heat dissipation substrate 6 through a bonding material composed of solder materials such as solder paste, tin sheet or tin wire. Compared with the resin material used for plastic encapsulation, the ceramic substrate 41 has a high heat dissipation coefficient and good heat dissipation performance, and the ceramic substrate 41 itself is an insulating material, which realizes the electrical insulation between the internal circuit of the product and the heat dissipation substrate, thereby reducing the cost of heat dissipation. The installation difficulty of the power semiconductor device application side. The application of double-sided copper-clad ceramic substrates to the packaging of power semiconductor devices not only improves the heat dissipation performance of the product itself, but also improves the thermal conductivity and insulation withstand voltage capabilities of the power semiconductor device itself, while avoiding the risk of insulation failure of the power semiconductor device. The electrical insulation between the internal circuit of the product and the heat-dissipating substrate is realized, which solves the unsolved problem that those skilled in the art have always wanted to solve.
具体地，双面覆铜陶瓷基板背面设置散热基板6，散热基板6露出封装体1的背部，散热基板6的材料设置为常用的铜材、铝材或合金材料，并在散热基板6的背部加装散热器，可及时将内部电路产生的热量依次通过双面覆铜陶瓷基板中的陶瓷基板41、散热基板6传热，由散热器将热量及时快速散出去，进一步提高了功率半导体器件的散热性能。Specifically, a heat dissipation substrate 6 is arranged on the back of the double-sided copper-clad ceramic substrate, and the heat dissipation substrate 6 is exposed on the back of the package body 1 . The installation of a radiator can timely transfer the heat generated by the internal circuit through the ceramic substrate 41 and the heat dissipation substrate 6 in the double-sided copper-clad ceramic substrate in turn, and the heat can be quickly dissipated by the radiator in time, which further improves the power semiconductor device. Thermal performance.
另外，散热基板6与引脚5设置为一体式框架结构，提高了整体结构的稳定性，降低了安装难度，引脚5穿出封装体1外与其他元器件进行电气连接；引脚5沿其长度方向设置有将塑封材料聚集的环形塑封槽51，在对产品进行塑封时，该环形塑封槽51可将塑封材料实现缩口密封，进一步提高了塑封的质量；双面覆铜陶瓷基板设置在散热基板6的中部，且双面覆铜陶瓷基板的边缘与散热基板6的边缘之间在水平方向的距离大于0.8mm，由于在不同的使用情况下，为了防止芯片2、散热基板6之间的双面覆铜陶瓷基板的表面可能出现的污染物出现爬电现象，使双面覆铜陶瓷基板被电极化，导致绝缘失效的现象，在综合额定电压、污染状况、绝缘材料、表面形状、位置方向、承受电压时间长短等多种使用条件和环境因素下，根据经验值，将双面覆铜陶瓷基板的边缘与散热基板6的边缘之间在水平方向的距离大于0.8mm时，可防止爬电现象的产生，防止了内部绝缘失效。In addition, the heat dissipation substrate 6 and the pins 5 are set as an integral frame structure, which improves the stability of the overall structure and reduces the difficulty of installation. The pins 5 pass out of the package body 1 for electrical connection with other components; Its length direction is provided with an annular plastic sealing groove 51 that gathers the plastic sealing material. When the product is plastic-sealed, the annular plastic sealing groove 51 can seal the plastic sealing material and further improve the quality of the plastic sealing; the double-sided copper-clad ceramic substrate is provided with In the middle of the heat dissipation substrate 6, and the distance in the horizontal direction between the edge of the double-sided copper-clad ceramic substrate and the edge of the heat dissipation substrate 6 is greater than 0.8 mm, because under different usage conditions, in order to prevent the chip 2 and the heat dissipation substrate 6 The contaminants that may appear on the surface of the double-sided copper-clad ceramic substrate between the two sides appear creepage phenomenon, which makes the double-sided copper-clad ceramic substrate electrically polarized and leads to the phenomenon of insulation failure. Under various conditions of use and environmental factors, such as the position direction, the duration of the withstand voltage, etc., according to empirical values, when the horizontal distance between the edge of the double-sided copper-clad ceramic substrate and the edge of the heat dissipation substrate 6 is greater than 0.8mm, the Prevent the occurrence of creepage phenomenon and prevent the failure of internal insulation.
综上，该封装结构整体结构简单，实现了功率半导体器件的内部绝缘，省去了应用安装时需要加装绝缘片的环节，提高了作业效率及安装良率，而且提高了功率半导体器件的散热性能。In summary, the overall structure of the package structure is simple, the internal insulation of the power semiconductor device is realized, the need to install an insulating sheet during application and installation is omitted, the operation efficiency and installation yield are improved, and the heat dissipation of the power semiconductor device is improved. performance.
上述功率半导体器件的封装结构的封装工艺，包括以下步骤：The packaging process of the packaging structure of the above-mentioned power semiconductor device includes the following steps:
1)通过结合材将双面覆铜陶瓷基板的底层焊接在散热基板6上，需要满足双面覆铜陶瓷基板的边缘与散热基板6的边缘之间在水平方向的距离大于0.8mm；1) The bottom layer of the double-sided copper-clad ceramic substrate is welded on the heat-dissipating substrate 6 through the bonding material, and the distance in the horizontal direction between the edge of the double-sided copper-clad ceramic substrate and the edge of the heat-dissipating substrate 6 needs to be greater than 0.8 mm;
2)通过结合材将芯片2焊接在双面覆铜陶瓷基板的上层；2) Weld the chip 2 on the upper layer of the double-sided copper-clad ceramic substrate through the bonding material;
3)将芯片2通过键合线3与引脚5进行电气连接，该芯片2包括两个电极，两个电极分别通过键合线3与对应的引脚5相连；3) the chip 2 is electrically connected with the pin 5 through the bonding wire 3, the chip 2 includes two electrodes, and the two electrodes are connected with the corresponding pin 5 through the bonding wire 3 respectively;
4)将连接好的芯片2、双面覆铜陶瓷基板、散热基板6、引脚5放置在注塑模具内塑封形成封装体1，同时使散热基板6的背面露出封装体1，使引脚5伸出封装体1外。4) Place the connected chip 2, the double-sided copper-clad ceramic substrate, the heat dissipation substrate 6, and the pins 5 in an injection mold to form a package body 1, and at the same time expose the back side of the heat dissipation substrate 6 to the package body 1, so that the pins 5 out of the package body 1 .
该封装工艺比较简单，具有实现规模化量产的可能，可提供性能较好、安装成本较低的功率半导体器件，适于推广使用。The packaging process is relatively simple, has the possibility of realizing large-scale mass production, can provide power semiconductor devices with better performance and lower installation cost, and is suitable for popularization and use.
以上所述，只是用图解说明本发明的一些原理，本说明书并非是要将本发明局限在所示所述的具体结构和适用范围内，故凡是所有可能被利用的相应修改以及等同物，均属于本发明所申请的专利范围。The above is only to illustrate some principles of the present invention. This specification is not intended to limit the present invention to the specific structure and scope of application shown. Therefore, all the corresponding modifications and equivalents that may be used are It belongs to the scope of the patent applied for by the present invention.
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