CN110611447B

CN110611447B - Pre-charging method for flying capacitor of multi-level inverter

Info

Publication number: CN110611447B
Application number: CN201910916296.4A
Authority: CN
Inventors: 张永
Original assignee: Fonrich Shanghai New Energy Technology Co ltd
Current assignee: Fonrich Shanghai New Energy Technology Co ltd
Priority date: 2019-09-26
Filing date: 2019-09-26
Publication date: 2021-07-30
Anticipated expiration: 2039-09-26
Also published as: CN110611447A

Abstract

The invention mainly relates to a method for precharging flying capacitors of a multi-level inverter. The level inverter comprises a single arm generating a multi-level output voltage, the upper arm and the lower arm being interconnected at an intermediate node. The single arm further comprises a first group of switches, considered an upper arm, and a second group of switches, considered a lower arm, connected in series between the first and second input terminals, wherein one or more flying capacitors are provided between an interconnection node between any adjacent pair of switches in the first group of switches and an interconnection node between a corresponding adjacent pair of switches in the second group of switches. The pre-charging method comprises the following steps: disconnecting the first and second input terminals from the first and second reference voltage sources, and connecting the second input terminal to a potential of the reference node; the remaining switches in the second set of switches except the last switch are all kept in an on state and a preliminary reverse charge is applied to all flying capacitors through the path of the first set of switches by an independent power supply coupled to the output.

Description

Pre-charging method for flying capacitor of multi-level inverter

Technical Field

The invention mainly relates to the technical field of photovoltaic power generation, in particular to a method for pre-charging a flying capacitor of a flying capacitor type multi-level inverter.

Background

The multilevel inverter is gradually becoming a field of power electronic technology in which high power is converted into a research object, and particularly, the flying capacitor type multilevel inverter has excellent advantages such as low harmonic distortion and extremely small electromagnetic interference, and shows outstanding inverter electrical performance. In the industry, a multilevel inverter as a high-voltage high-power converter has the following characteristics: each power device such as a switch and a capacitor only bears small voltage drop, and high-voltage high-power output can be realized by using a device with low voltage resistance; an increase in the number of levels means that the waveform of the output voltage can be improved, in particular that the distortion of the output waveform is reduced; the low switching frequency obtains the same output voltage waveform as the high switching frequency, but obtains the advantages of small switching loss and high efficiency; an isolated output transformer is not needed, so that the volume and the loss of the system are reduced; the harmonic wave of the input current is greatly reduced, and the pollution to a grid-connected network is reduced; neutral point level fluctuations can also be reduced or eliminated to a higher degree when used in a three-phase electric induction motor drive. On the main topological structure of an inverter circuit, a multi-level inverter has three basic topological structures of diode clamping, flying capacitors, H-bridge cascade connection and the like, and the flying capacitor type topological structure has higher multi-voltage configuration freedom.

The inverter provided by the application is applied to the photovoltaic power generation, and an inversion control scheme is established by fully considering the multi-level requirement of the output alternating current according to the technical advantages of the flying capacitor type multi-level inverter disclosed in the foregoing. However, the voltage build-up scheme of the flying capacitors must be reasonably set, because voltage imbalance among the flying capacitors inevitably causes level error and sinusoidal wave distortion, and because the bus direct-current voltage input to the inverter is too large, the capacitors or switches are damaged in the process of building the voltage from zero to the expected voltage for each flying capacitor. As a countermeasure to the above problem, before the inverter starts to perform inversion to generate ac power, the flying capacitor must be set to a suitable voltage level to prevent high-voltage dc power from the dc bus from causing impact on the switches, flying capacitor, and other devices. Therefore, the method applies the pre-charging measure of the capacitor voltage to the flying capacitor type inversion structure, pre-charges the flying capacitor in advance, and prevents the inverter from building voltage for the flying capacitor again at the moment of formally starting inversion action.

Disclosure of Invention

In an optional but non-limiting embodiment of the present application, a method of precharging a flying capacitor of a multilevel inverter is disclosed, which is primarily characterized in that a flying capacitor-type multilevel inverter includes a single arm for generating a multilevel output voltage, the single arm having an upper arm and a lower arm connected in series between first and second input terminals, the upper and lower arms being interconnected at an intermediate node; the single arm further comprises a first group of switches which are regarded as an upper arm and a second group of switches which are regarded as a lower arm, the first group of switches and the second group of switches are connected in series between the first input end and the second input end, and one or more flying capacitors are arranged between interconnection nodes between any adjacent pair of switches in the first group of switches and interconnection nodes between corresponding adjacent pair of switches in the second group of switches; the first set of switches is ordered from a first switch coupled to the first input to an end switch coupled to the intermediate node and the second set of switches is ordered from the first switch coupled to the second input to the end switch coupled to the intermediate node; first and second reference voltage sources coupled to the first and second input terminals, respectively, and generating an alternating current between an output terminal and a reference node, an inductor being provided between the output terminal and the intermediate node; the method comprises the following steps: disconnecting the first and second input terminals from the first and second reference voltage sources, respectively; connecting the second input terminal to a potential that the reference node has; the remaining switches in the second set of switches except the last switch are all kept in an on state and a preliminary reverse charge is applied to all flying capacitors through the path of the first set of switches by an independent power supply coupled to the output.

The method described above, wherein: and a stage of performing preliminary reverse charging on all flying capacitors, wherein all the switches of the first group are synchronously kept to be in an on state so that the switches of the first group are used as charging paths.

The method described above, wherein: and a stage of carrying out primary reverse charging on all flying capacitors, wherein all the other switches except the first switch in the first group of switches are synchronously kept to be in a turn-on state, so that the switches turned on in the first group of switches are used as charging paths.

The method described above, wherein: the first group of switches are respectively provided with at least anti-parallel diodes, and the anti-parallel diodes respectively provided by the first group of switches are used as charging paths in the stage of carrying out primary reverse charging on all flying capacitors.

The method described above, wherein: an upper capacitor and a lower capacitor connected in series between first and second reference voltage sources and coupled at said reference node to generate a series of said multilevel output voltages at intermediate nodes with the voltage level at the reference node serving as a voltage reference; a DC voltage equivalent to the difference between the first and second reference voltage sources is input between the first and second input terminals and a series of said multilevel output voltages are combined between the intermediate node and the reference node into a waveform which varies according to a sine wave law and is equivalent to an AC voltage.

The method described above, wherein: the switches in the first and second sets, each having the same rank, are set to complementary switches with one switched on and the other switched off.

The method comprises the following steps: setting the first group of switches and the second group of switches to have K switches respectively, and sequencing the first-stage flying capacitors coupled to the first pair of complementary switches to the K-1-stage flying capacitors coupled to the K-1-th pair of complementary switches in sequence; and after finishing the primary reverse charging, implementing subsequent step charging, and enabling the voltage of any previous-stage flying capacitor to be higher than that of the adjacent next-stage flying capacitor by a preset unit voltage in the step charging stage.

The method described above, wherein: in the step charging stage, Q is more than or equal to 1 and less than or equal to K, and the mode of charging the flying capacitor of any Q-th level is as follows: driving the switches ordered as Q +1 in the second set of switches to switch on and off at a high frequency by the pulse width modulated signal while the remaining switches in the second set of switches remain on, the switches ordered as Q +1 in the first set of switches also being switched on by the complementary high frequency and the other switches remaining at least from the Q +2 th stage to the K-th stage; the flying capacitor of the Q-th stage is charged to a preset voltage level in a manner that adjusts the duty cycle of the switches ordered as Q +1 in the second set of switches.

The method described above, wherein: after the flying capacitor of any Q-th level is charged to a preset voltage level, the switch which is sequenced into Q +1 in the first group of switches is controlled to be switched off in the process of charging the flying capacitors which are sequenced into the Q + 1-th level.

Without any doubt, before the multilevel inverter formally enters a steady-state inversion working mode, a reasonable expected voltage is established for the flying capacitor, and the pre-charging action ensures that the switch and the capacitor can enable the flying capacitor to reach a required voltage value or level value and realize voltage equalization within a bearable charging voltage and charging current range.

Drawings

The features and advantages of the present application will become apparent upon reading the following detailed description and upon reference to the following drawings.

Fig. 1 is a main topology circuit architecture adopted by the flying capacitor type multilevel inverter of the present application.

Fig. 2 is an example topology of an upper arm first set of six switches and a lower arm second set of six switches.

FIG. 3 is a multi-level inverter topology employed to pre-charge flying capacitors in advance.

FIG. 4 is an embodiment of early charging of a flying capacitor by an independent power supply coupled to an output.

Detailed Description

The technical solutions of the present invention will be clearly and completely explained below with reference to various embodiments, and the described embodiments are only used as illustrative embodiments of the present invention and not all embodiments, and the solutions obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

Referring to fig. 1, with the rapid development of control theory, power electronics technology and semiconductor devices, a lower-cost and higher-efficiency inverter is sought to realize that single-phase or multi-phase alternating current becomes a hot spot of power electronics, and a Flying capacitor type Flying-capacitor clamping type multi-level inversion scheme proposed by MEYNARD and FOCH in a multi-level inverter circuit in the alternating current field is very featured, thereby bringing great attention to the field of speed regulation of medium and high power alternating current motors, and having small harmonic distortion, low stress of semiconductor devices and low electromagnetic interference of an inversion system. In the figure, a direct current voltage source is provided between the transmission line LNA and the transmission line LNB, and if the transmission line LNA has a potential VD and the transmission line LNB has a potential VR, the direct current input to the multi-level inverter is VD minus VR.

Referring to fig. 1, a plurality of dc power supplies may be directly connected in series between the transmission line LNA and the transmission line LNB, i.e., between the first and second input terminals, and the dc power supplies typically include: photovoltaic modules, fuel cells, chemical cells and other types of energy storage battery packs, and the like. In the first case: the dc power supplies are allowed to be directly connected in series to obtain a cascade voltage having a high voltage level by superposition, and then the cascade voltage is used as a dc voltage to be input to the inverter between the first and second input terminals. As an alternative second case: the direct current power supply is not directly connected in series between the transmission line LNA and the transmission line LNB, but a plurality of voltage converters are connected in series between the first input end and the second input end, the voltage converters belong to a switch mode power supply SMPS, and the switch mode power supply is also called as an exchange power supply and a switch converter, and is a high-frequency electric energy conversion device for DC/DC conversion; at this time, the direct current power supply is not directly connected in series between the transmission line LNA and the transmission line LNB, the plurality of voltage converters are directly connected in series between the transmission line LNA and the transmission line LNB, the voltage converters are direct current to direct current voltage converters, each voltage converter is used for receiving electric energy provided by a corresponding direct current power supply and performing power conversion on the electric energy, and the voltages output by the plurality of voltage converters are superposed to be transmitted to the position between the transmission line LNA and the transmission line LNB as serial-level voltages. The advantages of the second case are: a certain voltage converter may adopt a scheme of maximum power point tracking in performing power conversion on electric energy provided by a corresponding direct current power supply. The output power of the photovoltaic module is affected by factors such as the irradiation intensity of peripheral sunlight and temperature in most occasions, and the voltage converter can track the maximum output power point of the photovoltaic module, namely the output voltage and the output current of the photovoltaic module are set at the maximum power point in the power conversion process. Because photovoltaic modules or chemical batteries and the like are influenced by various external factors such as irradiance, temperature and the like, the instability of the output power of the direct current power supply further causes that the cascade voltage between the transmission lines LNA and LNB is not very stable, the transmission lines LNA-LNB can be used as the direct current bus to obtain the voltage U of the allowed direct current bus, namely the input voltage of the inverter, and the voltage U of the direct current bus can be fixed by utilizing various existing voltage stabilizing devices such as a voltage stabilizer to avoid fluctuation.

Referring to fig. 1, the topology is widely representative using a single arm with a variable number of switches and the number of switches of the upper arm and the lower arm are both K. The upper arms SA _1 to SA _ K and the lower arms SB _1 to SB _ K respectively constitute a first group of switches and a second group of switches of the flying capacitor type multilevel inverter. A flying capacitor C _ K-1 is connected between an interconnection node NA _ K-1 between any adjacent pair of switches SA _ K-1 and SA _ K in the first set of switches and an interconnection node NB _ K-1 between a corresponding pair of adjacent switches SB _ K-1 and SB _ K in the second set of switches, and the K which is described as a natural number is more than or equal to 2. The single arm satisfies the condition: among the pair of switches SA _ K-1 and SA _ K and the corresponding pair of switches SB _ K-1 and SB _ K, one of the switches SA _ K of the first set is complementary to the switch SB _ K of the second set, and the switch SA _ K-1 of the first set is complementary to the switch SB _ K-1 of the second set. The single arm has an upper arm and a lower arm connected in series between a first input, transmission line LNA, and a second input, transmission line LNB, and is used to generate a multilevel output voltage: the upper arms SA _1 to SA _ K and the lower arms SB _1 to SB _ K are connected to a first intermediate node NX, i.e., an arm point, and two sets of switches K are respectively applied to the upper and lower arms. In this topology the first set of switches is defined to be ordered sequentially from the first switch SA _1 connected to the transmission line LNA to the switch SA _ K connected to the end of the intermediate node NX, and the second set of switches is defined to be ordered sequentially from SB _1 connected to the transmission line LNB, denoted as the first switch, to the switch SB _ K connected to the end of the intermediate node NX, any one of the switches of the first set and the one of the switches of the second set having the same ordering is set as a pair of complementary switches. The direct current voltage source is input from between the transmission line LNA and the transmission line LNB, the multi-level voltage is output from the intermediate node NX, and the filter inductor LX may be further connected to the intermediate node NX. The first set of switches and the second set of switches are generally considered to constitute a single leg of a multilevel inverter, and the combination of multiple single legs may constitute a multi-phase inverter.

Referring to FIG. 1, first, it is assumed that first and second sets of switches each have a number K of switches, defining flying capacitors C _ K-1 coupled to the first pair of complementary switches (i.e., SA _1 and SB _ 1) in order from the first-level flying capacitor C _1 coupled to the first pair of complementary switches (i.e., SA _ K-1 and SB _ K-1) to the K-1-level flying capacitor C _ K-1 coupled to the K-1-level complementary switches (i.e., SA _ K-1 and SB _ K-1), and in essence, the first-level flying capacitors are ordered to the second-level flying capacitors and then to the third-level flying capacitor … …, and so on until the flying capacitors ordered to the K-1-level are ordered from C _1, C _2, C _3 … … to C _ K-2, C _ K-1. The voltage build-up objective according to the present application is to achieve pre-charging based on two main steps of performing a preliminary reverse charging first and then performing a step charging: the primary reverse charging step needs to ensure that the flying capacitors C _1 to C _ K-1 from the first stage to the K-1 stage are all charged, the charging degrees of the flying capacitors are approximately the same, and the charging voltages are approximately the same; in the step charging step, the voltage of any previous flying capacitor is required to be ensured to be higher than that of an adjacent next flying capacitor by a preset unit voltage UID, for example, the voltage of a first flying capacitor C _1 is higher than that of a second flying capacitor C _2 by a unit voltage UID, for example, the voltage of the second flying capacitor C _2 is higher than that of a third flying capacitor C _3 by a unit voltage UID, and the voltage of a K-2-th flying capacitor C _ K-2 can be considered to be higher than that of a K-1-th flying capacitor C _ K-1 by a unit voltage UID.

Referring to fig. 2, taking as an example a first set of six switches and a second set of six switches, the first and second sets of switches are each controlled by a high frequency pulse width modulated signal/control signal PWM coupled to a control terminal of the switch to switch between off and on. In fact, the number of the switches of the first group and the second group is not limited to six, more or fewer switches can be selected adaptively as shown in fig. 1, and in the field of power electronics, power switches such as IGBTs and MOSFETs or power switches similar to thyristors can be adopted as the switches. The first set of switches SA1-SA6 and the second set of switches SB1-SB6 constitute a single arm of the multilevel inverter, the number of switches in each set may not be limited to six but a greater or lesser number, the individual switches SA1-SA6 in the first set of switches are connected in series between the transmission line LNA and the intermediate node NX, and the individual switches SB1-SB6 in the second set of switches are connected in series between the transmission line LNB and the intermediate node NX. The switch tube is provided with a first end, a second end and a control end for receiving a control signal, and the control signal is conducted between the first end and the second end if the switch tube is controlled to be conducted or is disconnected between the first end and the second end if the switch tube is controlled to be disconnected. The position relations of the switches in the first group of switches SA1-SA6 are, for example: the first terminal of the first switch SA1 is connected to the transmission line LNA, the first terminal of the following switch SA2 is connected to the second terminal of the adjacent previous switch SA1, the first terminal of the following switch SA3 is connected to the second terminal of the adjacent previous switch SA2, and so on, according to the rule, the first terminal of the following switch SA5 is connected to the second terminal of the adjacent previous switch SA4, the first terminal of the last switch SA6 is connected to the second terminal of the adjacent switch SA5 and the second terminal of the switch SA6 is connected to the intermediate node NX. The first terminal of the first switch SA1 in the first set of switches is connected to the transmission line LNA and the second terminal of the last switch SA6 is connected to the intermediate node NX and the first terminal of any subsequent switch is connected to the second terminal of the adjacent previous switch. The position relations of the switches in the second group of switches SB1-SB6 are as follows: the second end of the first switch SB1 is connected to the transmission line LNB, the second end of the next switch SB2 is connected to the first end of its adjacent previous switch SB1, the second end of the next switch SB3 is connected to the first end of its adjacent previous switch SB2, and so on, the second end of the next switch SB5 is connected to the first end of its adjacent previous switch SB4, and the second end of the last switch SB6 is connected to the switch SB5, i.e. the first ends of the adjacent switches and the first end of the last switch SB6 are connected to the intermediate node NX. The second terminal of the first switch SB1 in the second set of switches is connected to the transmission line LNB and the first terminal of the last switch SB6 is connected to the intermediate node NX with the second terminal of any subsequent switch being connected to the first terminal of the adjacent previous switch.

Referring to fig. 2, assuming that the first and second sets of switches each have 6 switches, the first through fifth stages of flying capacitors are substantially C1 through C5, ordered from the first stage flying capacitor C1 coupled to the first pair of complementary switches, SA1/SB1, to the fifth stage flying capacitor C5 coupled to the fifth pair of complementary switches, SA5/SB 5. Any one of the first group of switches is connected with a resistor R in parallel between the first end and the second end, any one of the second group of switches is connected with a resistor R in parallel between the first end and the second end, and the required voltage values of the first-fifth-stage flying capacitors C1-C5 can be established for the first-fifth-stage flying capacitors C1-C5 by adjusting the resistance value of the resistor R. However, in such an embodiment, although resistor R facilitates the pre-charging of the flying capacitor, it does produce inevitable power losses.

Referring to fig. 2, the first set of switches SA1-SA6 is ordered sequentially from the first switch SA1 connected to the transmission line LNA to the switch SA6 connected to the end of the intermediate node NX, and the second set of switches SB1-SB6 is ordered sequentially from the first switch SB1 connected to the transmission line LNB to the switch SB6 connected to the end of the intermediate node NX. The first switch SA1 of the first group and the first switch SB1 of the second group are complementary switches to each other, the second switch SA2 of the first group and the second switch SB2 of the second group are complementary switches, the third switch SA3 of the first group and the third switch SB3 of the second group are complementary switches, the fourth switch SA4 of the first group and the fourth switch SB4 of the second group are complementary, and the fifth switch SA5 of the first group and the fifth switch SB5 of the second group are complementary to each other, and so on until the sixth switch SA6 of the first group and the sixth switch SB6 of the second group are defined as complementary switches. Complementary switches mean that one of the complementary switches is on and the other is off. As a flying capacitor type multilevel inverter scheme, one or more capacitors are connected between one interconnection node between any adjacent pair of switches in the first group of switches and one interconnection node between a corresponding pair of adjacent switches in the second group of switches, thereby constituting a single arm of the flying capacitor type multilevel inverter.

Referring to fig. 2, one or more capacitors C1 are connected between an interconnection node NA1 between an adjacent pair of switches SA1-SA2 in the first set of switches and an interconnection node NB1 between a corresponding adjacent pair of switches SB1-SB2 in the second set of switches, wherein: the second terminal of switch SA1 and the first terminal of switch SA2 are connected to interconnection node NA1 and also the first terminal of switch SB1 and the second terminal of switch SB2 are connected to interconnection node NB 1.

Referring to fig. 2, one or more capacitors C2 are connected between an interconnection node NA2 between an adjacent pair of switches SA2-SA3 in the first set of switches and an interconnection node NB2 between a corresponding adjacent pair of switches SB2-SB3 in the second set of switches, wherein: the second terminal of switch SA2 and the first terminal of switch SA3 are connected to interconnection node NA2 and also the first terminal of switch SB2 and the second terminal of switch SB3 are connected to interconnection node NB 2.

Referring to fig. 2, one or more capacitors C3 are connected between an interconnection node NA3 between an adjacent pair of switches SA3-SA4 in the first set of switches and an interconnection node NB3 between a corresponding adjacent pair of switches SB3-SB4 in the second set of switches, wherein: the second terminal of switch SA3 and the first terminal of switch SA4 are connected to interconnection node NA3 and also the first terminal of switch SB3 and the second terminal of switch SB4 are connected to interconnection node NB 3.

Referring to fig. 2, one or more capacitors C4 are connected between an interconnection node NA4 between an adjacent pair of switches SA4-SA5 in the first set of switches and an interconnection node NB4 between a corresponding adjacent pair of switches SB4-SB5 in the second set of switches, wherein: the second terminal of switch SA4 and the first terminal of switch SA5 are connected to interconnection node NA4 and also the first terminal of switch SB4 and the second terminal of switch SB5 are connected to interconnection node NB 4.

Referring to fig. 2, one or more capacitors C5 are connected between an interconnection node NA5 between an adjacent pair of switches SA5-SA6 in the first set of switches and an interconnection node NB5 between a corresponding adjacent pair of switches SB5-SB6 in the second set of switches, wherein: the second terminal of switch SA5 and the first terminal of switch SA6 are connected to interconnection node NA5 and also the first terminal of switch SB5 and the second terminal of switch SB6 are connected to interconnection node NB 5.

Referring to fig. 3, an output stage is additionally provided in this embodiment compared to the single arm of fig. 1. The aforementioned series of multi-level output voltages is generated at a first intermediate node with a reference voltage source present at a second intermediate node as a voltage reference. Such as first and second reference voltage sources coupled to the first and second input terminals, respectively, with an upper capacitor (e.g., one or more capacitors CU) and a lower capacitor (e.g., one or more capacitors CD) coupled in series between the first and second reference voltage sources, and the upper and lower capacitors coupled at a second intermediate node NZ, with the second intermediate node having a voltage level, e.g., denoted as V3, as a voltage reference to produce a series of the multi-level output voltages at the first intermediate node. Take three reference voltage sources as an example: the highest voltage level reference voltage source V1 is coupled to transmission line LNA and the second voltage level reference voltage source V3 is coupled to transmission line LNE1/LNE2 through capacitive devices CU/CD respectively and the lowest voltage level reference voltage source V2 is coupled to transmission line LNB. In an alternative embodiment, the single-arm first intermediate node NX generates a series of multi-level output voltages referenced to a voltage reference from a reference voltage source V3, the load LD is connected between the first intermediate node NX and a second intermediate node NZ, the load is applied between the output terminals OUT1-OUT2, the output terminal OUT1 is coupled to the first intermediate node NX and the output terminal OUT2 is coupled to the second intermediate node NZ. Direct current is input between the first input end and the second input end, namely between the LNA-LNB, and a series of multi-level output voltages are generated to synthesize a waveform which changes according to a sine wave rule and is equivalent to alternating current between the first intermediate node NX-NZ and the second intermediate node NX-NZ. The third voltage, i.e., reference voltage source V3, may be an independent voltage source, the second voltage, i.e., reference voltage source V2, may be an independent voltage, and the first voltage, i.e., reference voltage source V1, may also be an independent voltage, without any relation therebetween being allowed. The intermediate node NX generates a multi-level output using a reference voltage source provided at the intermediate node NZ as a voltage reference, and the intermediate node NZ is also referred to as a reference node.

Referring to fig. 3, if transmission line LNE1 is directly connected to the transmission line with reference voltage source V1, correspondingly if transmission line LNE2 is directly connected to the transmission line with reference voltage source V2, two or more voltage dividing capacitors such as serial voltage dividing capacitors CU-CD are connected in series between transmission lines LNE1 and LNE 2. The voltage dividing capacitors CU and CD are interconnected at a voltage dividing node, which is also substantially a second intermediate node NZ: the capacitance values of the voltage dividing capacitors can be the same or different, which is equivalent to that a voltage dividing capacitor CU is connected between the transmission line LNE1 and the voltage dividing node NZ and a voltage dividing capacitor CD is connected between the transmission line LNE2 and the voltage dividing node NZ. A desired reasonable divided voltage value or a reasonable clamping voltage value can be obtained at the dividing node/the second intermediate node NZ. It can also be understood in essence that: the reference voltage source V3, which connects two or more voltage dividing capacitors in series between the first voltage V1 and the second voltage V2 to obtain the third voltage at the second intermediate node NZ, is equivalent to connecting two or more voltage dividing capacitors in series between the reference voltage sources V1 and V2 to obtain the third voltage at the voltage dividing node NZ. If the above-mentioned capacitors CU and CD are equal, the voltage drop of the first voltage, i.e., V1, with respect to the third voltage, i.e., V3, is equal to the voltage drop of the third voltage, i.e., V3, with respect to the second voltage, i.e., V2, in other words, the third voltage is allowed, and V1-V3= V3-V2 is a preferred embodiment. In an alternative embodiment the transmission line LNE1 with voltage V1 is coupled to the LNA and the transmission line LNE2 with voltage V2 is correspondingly coupled to the LNB, which is an alternative embodiment illustrated in fig. 3.

Referring to fig. 3, in an alternative embodiment, the second voltage, i.e. reference voltage source V2, is no longer an independent voltage and the aforementioned first voltage, i.e. reference voltage source V1, is no longer an independent voltage, but rather the potential of reference voltage source V1 is set equal to the potential VD present on transmission line LNA, while at the same time the potential of reference voltage source V2 is set equal to the potential VR present on transmission line LNB. As shown, the transmission line LNE1 with the reference voltage source V1 is directly coupled to the transmission line LNA with the potential VD, while the transmission line LNE2 with the reference voltage source V2 is directly coupled to the transmission line LNB with the potential VR. The capacitor CU-CD is interconnected at the voltage dividing node: a voltage dividing capacitor CU is connected between the transmission line LNE1 and the voltage dividing node NZ and a voltage dividing capacitor CD is also connected between the transmission line LNE2 and the voltage dividing node NZ, and the capacitance values of the voltage dividing capacitors CU-CD may be the same or different. A desired reasonable value of the divided voltage can be achieved at the divided voltage node NZ. If the capacitors CU and CD are equal, the voltage drop of the first voltage, i.e. V1, with respect to the third voltage, i.e. V3, is equal to the voltage drop of the third voltage, i.e. V3, with respect to the second voltage, i.e. V2, in other words, the third voltage is the midpoint potential of the first voltage and the second voltage, and VD-V3= V3-VR is a preferred embodiment, where the potential of the first voltage is equal to the potential VD of the first input terminal and the potential of the second voltage is equal to the potential VR of the second input terminal.

Referring to fig. 3, in an alternative embodiment, a multilevel inverter system for generating ac power controlled by high frequency switching single-leg switches is disclosed, where the multilevel inverter may comprise the single-leg of fig. 1-2, where the single-leg may output a plurality of level levels of output voltage, where the output level includes a plurality of reference voltage sources having different voltage levels. The function of the output stage comprises switching the output voltages of the plurality of level levels to suitable voltage references, since the output voltages of the plurality of level levels only exhibit a voltage level or a level magnitude with a relatively well-defined voltage reference.

Referring to fig. 3, in this embodiment the multilevel inverter includes a first set of switches SA1-SA3 connected between the transmission line LNA and the intermediate node NX, and a second set of switches SB1-SB3 connected between the transmission line LNB and the intermediate node NX, the upper arms SA1-SA3 of the multilevel inverter being connected in series between the transmission line LNA and the intermediate node NX and the lower arms SB1-SB3 of the multilevel inverter being connected in series between the transmission line LNB and the intermediate node NX, also directly expressed as the first set of switches and the second set of switches being connected in series between the transmission line LNA and the transmission line LNB. In a multilevel inverter: one or more capacitors C1 are connected between an interconnection node NA1 between any adjacent pair of switches SA1-SA2 in the first set of switches and an interconnection node NB1 between a corresponding adjacent pair of switches SB1-SB2 in the second set of switches, and one or more capacitors C2 are provided between an interconnection node NA2 between any adjacent pair of switches SA2-SA3 in the first set of switches and an interconnection node NB2 between a corresponding adjacent pair of switches SB2-SB3 in the second set of switches. As described above, the complementary switches SA1-SB1, SA2-SB2 and SA3-SB3 are satisfied to thereby constitute a single arm based on the flying capacitor type clamped inversion scheme. The power supply V1 in the output stage is connected at the second intermediate node NZ through some capacitors CU, the power supply V2 is connected at the second intermediate node NZ through some capacitors CD, and the reference power supply V3 in the output stage is equivalent to at the second intermediate node NZ. More than two voltage dividing capacitors such as voltage dividing capacitors CU-CD connected in series are connected between the transmission lines LNE1-LNE2, that is, the voltage dividing capacitor CU is connected between the transmission line LNE1 and the voltage dividing node and the voltage dividing capacitor CD is connected between the transmission line LNE2 and the voltage dividing node NZ, and the voltage dividing node obtains a desired reasonable voltage dividing value and serves as a voltage source V3. The transmission line LNE1 with the reference voltage source V1 is coupled to the input transmission line LNA with the potential VD, while the transmission line LNE2 with the reference voltage source V2 is directly coupled to the input transmission line LNB with the potential VR. To avoid confusion, the intermediate node NX of the single arm of the inverting part may be set as a first defined intermediate node, and the intermediate node NZ of the output stage may be set as a second defined intermediate node. The control switches, i.e. the first and second group of switches mentioned above, are power semiconductor switches having first and second terminals and a control terminal for receiving a control signal/modulation signal, which if controlling the switches to be on corresponds to the first and second terminals of the switch being on or the switches to be off corresponds to the first and second terminals of the switch being off, for example the first and second terminals may be drain and source terminals or vice versa of a field effect transistor, for example the collector and emitter of an insulated gate bipolar transistor or vice versa, of course the anode and cathode of a thyristor or vice versa, the control terminal of the switch is a gate or gate terminal or the like and the switch may also be a thyristor switching device or the like. Alternating current is generated between a first output terminal OUT1 and a second output terminal OUT2 as output terminals of the output stage, the first output terminal OUT1 is coupled to the intermediate node NX of the single arm and the corresponding second output terminal OUT2 is coupled to the intermediate node NZ, and an alternating current load LD portion is connected between the first and second output terminals OUT-OUT 2. A filter inductance LX may be connected between the first output terminal OUT1 and the intermediate node NX and a filter capacitance CX may also be connected between the first and second output terminals OUT-OUT 2. Direct current is input between the first and second input terminals, i.e. between the transmission lines LNA-LNB, whereby a waveform varying according to a sine wave law and equivalent to alternating current is synthesized between said first and second intermediate nodes NX-NZ by the series of multilevel output voltages, the alternating current load LD being coupled between the first and second intermediate nodes NX-NZ.

Referring to fig. 3, in an alternative embodiment, an alternative, but not necessary, way of generating alternating current is illustrated in conjunction with the topology of fig. 2. Assuming that the transmission line LNA has a potential VD and the transmission line LNB has a potential VR, the dc voltage input to the multilevel inverter is VD minus VR, and the difference is equal to U. Assuming that capacitors CS1-CS2 and the like are connected in series between the reference ground potential G and the transmission line LNA, and capacitors CS3-CS4 and the like are connected in series between the reference ground potential G and the transmission line LNB, it is equivalent to divide the dc input voltage U of the multilevel inverter into two equal parts, such as a positive U/2 potential of the transmission line LNA with respect to the reference ground potential G, and the potential of the transmission line LNB with respect to the reference ground potential G is a negative U/2 potential, and VD-VR = U is satisfied. In an alternative embodiment, capacitors C11-C12 are connected in series between node NA1 and another node NB1, a capacitor C2 is connected between node NA2 and node NB2, and capacitors C11-C12 are charged to U/2 in total during the initial charging establishing voltage phase to chargeAnd capacitor C2 is charged to U/4. The bus voltage U or notation U is explained hereinbefore_BUSIt is possible to float up and down, and it is not required that U be a continuously fixed value, particularly considering that the voltage of the cells in the field of photovoltaic power generation will inevitably fluctuate greatly with the alternation of day and night. The first set of switches is ordered from a first switch SA1 coupled to the first input to a last switch SA3 coupled to the intermediate node NX; the second set of switches is ordered from the first switch SB1 coupled to the second input to the last switch SB3 coupled to the intermediate node NX.

Referring to FIG. 4, in an alternative embodiment, a method of precharging a flying capacitor comprises: disconnecting the first input from the first reference voltage source, e.g. from the transmission line LNA having the potential VD, disconnecting the second input from the second reference voltage source, e.g. from the transmission line LNB having the potential VR, is sufficient if one front-side switch is arranged between the first input and the provider of the potential VD and is switched off, and another front-side switch is arranged between the second input and the provider of the potential VR and is switched off. The main purpose is that the dc busses are not suitable as a voltage source for precharging because they are the supplier of the dc voltage VD-VR with high voltage values that can damage the switches and capacitors. It is then necessary to connect the second input terminal to the potential provided by the reference node NZ, for example: a changeover switch Q1 is arranged between the second input and the interconnection between both the CS1-CS2 and both CS3-CS4 and the second input, the interconnection of which has substantially the same potential G as the reference node NZ if the capacitances CS1-CS2 are equal to the capacitances CS3-CS4, the second input being connectable to the potential which the reference node has with the changeover switch Q1 switched on. Then, the remaining switches except the last switch in the second group of switches are all turned on, for example, the remaining switches except the switch SB3 in the second group of switches SB1-SB3 are all turned on while the switch SB3 is turned off, the flying capacitors C11/C12 and C2 are initially charged in reverse direction by the independent power supply VB coupled to the output terminal OUT1 through the path in which the first group of switches are located, the capacitors C11/C12 can be equivalent to the first stage flying capacitor, the capacitor C2 is the second stage flying capacitor, the control switch Q2 can be arranged between the output terminal OUT1 and the independent power supply VB, and the control switch Q2 is turned on only when the control switch Q2 is turned off and the output terminal OUT1 cannot be connected to the independent power supply and the flying capacitor needs to be charged. First and second reference voltage sources are coupled to the first and second input terminals, respectively, and generate alternating currents between an output terminal OUT1 and a reference node (i.e., a second intermediate node NZ), with an inductor L disposed between the output terminal OUT1 and the first intermediate node NX.

Referring to fig. 4, in an alternative embodiment, no additional resistor R is required for each switch in the first and second sets compared to fig. 2, but each semiconductor power switch may be provided with a Body Diode Body-Diode or with an anti-parallel Diode connected in parallel directly for each switch, the first set of switches each being provided with an inverse Diode DA1-DA3 and the second set of switches each being provided with an inverse Diode DB1-DB 3. There are various examples of implementing the preliminary reverse charging: during the phase of performing a preliminary reverse charge to all flying capacitors, keeping all of the first set of switches SA1-SA3 turned on synchronously so that the first set of switches act as a charging path, the path of switches SA2-SA3 can charge both the first and second stage flying capacitors and these flying capacitors can reach almost the same voltage level. Or the phase of performing the preliminary reverse charging to all flying capacitors can synchronously keep all the remaining switches SA2-SA3 in the first group of switches SA1-SA3 except the first switch SA1 in an on state so that the switches SA2-SA3 turned on in the first group of switches are used as charging paths, and the first and second flying capacitors can be charged to the same level, but the first switch SA1 does not need to be turned on.

Referring to fig. 4, in an alternative embodiment, each of the first switches has an antiparallel diode DA1-DA3 such as a mosfet or an IGBT, a body diode is parasitic between the source and drain of an N-type NMOS fet, and the anode of the body diode is coupled to the drain and the cathode of the body diode is coupled to the source, even these reverse-connected parallel diodes can be additionally introduced and connected in parallel directly between the first and second terminals of the semiconductor fet instead of the body diode, so that during the preliminary reverse charging of all flying capacitors of the first and second stages, the antiparallel diodes of the first switches SA1-SA3 are used as charging paths, while the switches SA2-SA3 can be turned on or off completely, and the switch SA1 and its reverse parallel diode do not have to control the flying capacitors of the stages Preparing: switch SA1 can be both on and off completely. In an alternative embodiment, an upper capacitor CU and a lower capacitor CD are connected in series between the first and second reference voltage sources VD-VR and coupled to said reference node NZ, with a voltage level, e.g. G-potential, presented by the reference node NZ as a voltage reference to generate a series of said multilevel output voltages at the intermediate node NX, a dc voltage equivalent to the difference between the first and second reference voltage sources VD/VR being input between the first and second input terminals and a waveform equivalent to an alternating current varying in a sine wave law being synthesized between the intermediate node NX and the reference node NZ by the series of said multilevel output voltages. The rationale is also the SPWM mechanism.

Referring to fig. 4, in an alternative embodiment, the switches in the first and second sets of switches, which are respectively arranged in the same order, are set as complementary switches, such as SA1-SB1 complementary to SA2-SB2 complementary to SA3-SB3 complementary to each other, and the complementary relationship mainly refers to the switch states of the multilevel inverter during the inversion operation phase. Setting the first and second sets of switches to have K number of switches, and therefore, sequentially ordering from the first level of flying capacitors coupled to the first pair of complementary switches to the K-1 level of flying capacitors coupled to the K-1 pair of complementary switches; and after finishing the primary reverse charging, implementing subsequent step charging, and enabling the voltage of any previous-stage flying capacitor to be higher than that of the adjacent next-stage flying capacitor by a preset unit voltage in the step charging stage. Such as: setting the number of the first and second groups of switches to be 3 respectively, therefore, sequentially sequencing from the first stage flying capacitor C11-C12 coupled to the first pair of complementary switches SA1/SB1 to the flying capacitor C2 coupled to the second stage of the second pair of complementary switches SA2/SB2, similarly, after finishing the preliminary reverse charging, implementing the subsequent step charging, and in the step charging stage, making the voltage of any previous stage flying capacitor C11-C12 higher than that of the adjacent next stage flying capacitor C2 by a predetermined unit voltage UID. In an alternative embodiment, 1 ≦ Q ≦ K is set in the step charging stage, for example, K =3 and Q =1 ≦ 2, and the flying capacitor of any Q-th stage is charged by: driving the switches ordered as Q +1 in the second set of switches to switch on and off at high frequency by a pulse width modulation signal PWM while the remaining switches in the second set of switches all remain on, the switches ordered as Q +1 in the first set of switches also being switched by complementary high frequency and the other switches remaining at least from the Q +2 th stage to the K-th stage all remaining on; the flying capacitor of the Q-th stage may eventually be charged to a preset voltage level in a manner that adjusts the duty cycle of the switches ordered as Q +1 in the second set of switches. Still taking K =3 and Q = 1-2 as examples, the flying capacitor of the first stage is charged by: the switch SB2 ordered two in the second group of switches is driven by the pulse width modulation signal PWM to switch at high frequency between on and off while the remaining other switches SB1/SB3 in the second group of switches all remain on, the switch ordered two in the first group of switches corresponds to the switch SA2 complementary to SB2 also being switched at complementary high frequency, while keeping at least the other switches from the Q +2 th stage to the kth stage all on such as the first group of switches from the third stage to the kth stage all on, here, keeping the third stage switch SA3 on, the first stage flying capacitor C11/C12 may eventually be charged to a preset voltage level in a manner that adjusts the duty cycle of the second set of switches sequenced as two SA2, in the charging process, the modulation signal drives the switch SB2 to be switched on and then drives the SA2 to be switched off, and the pulse modulation signal drives the switch SB2 to be switched off and then drives the SA2 to be switched on. Taking six switching tubes at the upper part and the lower part as examples: the flying capacitor of the third stage is charged in the following mode: the switch SB4 ordered as four in the second set of switches is driven by the pulse width modulation signal PWM to switch at high frequency between on and off while the remaining switches in the second set of switches all remain on, the switch ordered as four in the first set of switches being equivalent to switch SA4 complementary to SB4 also being switched at complementary high frequency while the other switches at least from the fifth stage to the sixth stage all remain on, e.g., switches SA5-SA6 are all on, and finally the flying capacitor C3 of the third stage is charged in such a way that the duty cycle of the switch SB4 ordered as four in the second set of switches is adjusted.

Referring to FIG. 4, in an alternative embodiment, after the flying capacitors in any Q-th stage (1 ≦ Q ≦ K) are charged to a predetermined voltage level, the switches ordered as Q +1 in the first set of switches are controlled to turn off during the charging of the flying capacitors ordered as Q + 1. Such as: in fig. 4, after the flying capacitors C11/C12 in any first stage are charged to a predetermined voltage level, in the process of charging the flying capacitors C2 in the second stage, the switches SA2 in the second stage in the first group of switches are controlled to be turned off, so as to avoid voltage crosstalk between adjacent flying capacitors. Taking six switching tubes at the upper part and the lower part as examples: during the process of charging flying capacitor C4 which is sequenced to the fourth stage, switch SA5 which is sequenced to five in the first group of switches is controlled to be switched off. In an alternative embodiment, the first switch SA1 in the first set of switches is kept off while the step charging is performed on any one of the first stage flying capacitors, such as the first switch SA1 in fig. 4 while the step charging is performed on the first stage flying capacitor, and the first switch SA1 in the first set of switches is kept off while the step charging is performed on the second stage flying capacitor.

While the above description and drawings represent a typical example of the particular arrangements of the embodiments, the present disclosure is intended to be illustrative of the presently preferred embodiments and is not to be taken in a limiting sense. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above disclosure. It is therefore intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims of the present application should be considered to be within the intent and scope of the present invention.

Claims

1. A method of precharging flying capacitors of a multilevel inverter, said multilevel inverter comprising a single leg for generating a multilevel output voltage, said single leg having an upper leg and a lower leg connected in series between first and second input terminals, said upper and lower legs being interconnected at an intermediate node;

the single arm further comprises a first group of switches which are regarded as an upper arm and a second group of switches which are regarded as a lower arm, the first group of switches and the second group of switches are connected in series between the first input end and the second input end, and one or more flying capacitors are arranged between interconnection nodes between any adjacent pair of switches in the first group of switches and interconnection nodes between corresponding adjacent pair of switches in the second group of switches;

the first group of switches are respectively provided with at least anti-parallel diodes;

the first set of switches is ordered from a first switch coupled to the first input to a last switch coupled to the intermediate node;

a second set of switches ordered from a first switch coupled to the second input to a last switch coupled to the intermediate node;

first and second reference voltage sources coupled to the first and second input terminals, respectively, and generating an alternating current between an output terminal and a reference node, an inductor being provided between the output terminal and the intermediate node;

an upper capacitor and a lower capacitor connected in series between first and second reference voltage sources and coupled at said reference node to generate a series of said multilevel output voltages at intermediate nodes with the voltage level at the reference node serving as a voltage reference;

inputting a DC voltage equivalent to the difference between the first and second reference voltage sources between the first and second input terminals and synthesizing a waveform equivalent to an AC current varying according to a sine wave law from a series of said multilevel output voltages between the intermediate node and the reference node;

a capacitor is connected in series between a reference ground potential and the first input terminal, and a capacitor is connected in series between the reference ground potential and the second input terminal, the reference node having a voltage level that is the potential of the reference ground potential;

the method comprises the following steps:

disconnecting the first and second input terminals from the first and second reference voltage sources;

connecting the second input terminal to a potential that the reference node has;

keeping all the rest switches except the tail switch in the second group of switches to be in a switch-on state, and performing primary reverse charging on all flying capacitors through a path where the first group of switches are located by an independent power supply coupled to an output end;

the switches in the first and second groups are set to be complementary switches, wherein one switch is turned on and the other switch is turned off;

setting the first group of switches and the second group of switches to have K switches respectively, and sequencing the first-stage flying capacitors coupled to the first pair of complementary switches to the K-1-stage flying capacitors coupled to the K-1-th pair of complementary switches in sequence;

and after finishing the primary reverse charging, implementing subsequent step charging, and enabling the voltage of any previous-stage flying capacitor to be higher than that of the adjacent next-stage flying capacitor by a preset unit voltage in the step charging stage.

2. The method of claim 1, wherein:

and a stage of performing preliminary reverse charging on all flying capacitors, wherein all the switches of the first group are synchronously kept to be in an on state so that the switches of the first group are used as charging paths.

3. The method of claim 1, wherein:

and a stage of carrying out primary reverse charging on all flying capacitors, wherein all the other switches except the first switch in the first group of switches are synchronously kept to be in a turn-on state, so that the switches turned on in the first group of switches are used as charging paths.

4. The method of claim 1, wherein:

in the stage of carrying out preliminary reverse charging to all flying capacitors, the reverse parallel diodes carried by the first group of switches respectively are used as charging paths.

5. The method of claim 1, wherein:

in the step charging stage, Q is more than or equal to 1 and less than or equal to K, and the mode of charging the flying capacitor of any Q-th level is as follows:

driving the switch ordered as Q +1 in the second set of switches to switch on and off at high frequency by the pulse width modulated signal while the remaining switches in the second set of switches all remain on, the switch ordered as Q +1 in the first set of switches also being switched by the complementary high frequency and the other switches remaining at least from the Q +2 th stage to the K-th stage all remaining on;

the flying capacitor of the Q-th stage is charged to a preset voltage level in a manner that adjusts the duty cycle of the switches ordered as Q +1 in the second set of switches.

6. The method of claim 1, wherein:

after the flying capacitor of any Q-th level is charged to a preset voltage level, the switch which is sequenced into Q +1 in the first group of switches is controlled to be switched off in the process of charging the flying capacitors which are sequenced into the Q + 1-th level.

7. The method of claim 5, wherein:

during the step charging phase of any one-stage flying capacitor, the first switch in the first group of switches is kept turned off.