CN110579698A - Junction temperature test method of InAlN/GaN HEMT - Google Patents
Junction temperature test method of InAlN/GaN HEMT Download PDFInfo
- Publication number
- CN110579698A CN110579698A CN201910851323.4A CN201910851323A CN110579698A CN 110579698 A CN110579698 A CN 110579698A CN 201910851323 A CN201910851323 A CN 201910851323A CN 110579698 A CN110579698 A CN 110579698A
- Authority
- CN
- China
- Prior art keywords
- curve
- resistance
- temperature
- gate
- under
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
- G01R31/2603—Apparatus or methods therefor for curve tracing of semiconductor characteristics, e.g. on oscilloscope
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a junction temperature test method of InAlN/GaN HEMTs, belonging to the technical field of semiconductor device test. The invention selects the channel resistance R below the gridgThe highest temperature of the channel of the lattice-matched InAlN/GaN heterojunction HEMTs is measured for temperature-sensitive parameters, so that the problems of inconvenience and inaccuracy in measurement of the highest temperature of the channel in the prior art are solved, and the highest temperature of the channel can be measured more conveniently and more accurately; the junction temperature test method can be faster, simpler and more convenient to operate, can more effectively measure the highest temperature of the channel of the lattice-matched InAlN/GaN heterojunction HEMTs, can be suitable for reliability test in integrated circuits and industrial production, and has the advantages that the measurement result is closer to the actual temperature and the accuracy is high.
Description
Technical Field
The invention relates to a junction temperature test method of an InAlN/GaN HEMT, belonging to the technical field of semiconductor device test.
Background
GaN heterostructure field effect transistors (HEMTs) have good high frequency performance at high power density and high bias voltage, playing a central role in future radar and telecommunications technologies. However, despite the impressive good performance exhibited, long-term stability and reliability remain a major problem with power densities up to 30W/mm. Meanwhile, because a gallium nitride epitaxial substrate is still unavailable at present, sapphire or silicon carbide is generally used as the substrate in the prior art, and Si and GaAs can also be used; while such devices often exhibit self-heating effects, the thermal properties of the structure limit the effective conduction of heat from the active area of the device at high bias voltages or currents. Increasing device temperature leads to degradation of device performance such as mobility and electron saturation velocity, which make GaN an attractive choice.
power dissipation in semiconductor devices occurs primarily in very small areas of the device, typically 0.5-1 μm near the gate contact, causing local joule heating. The increased operating temperature results in decreased performance and increased failure rate, and reduced output power. The method of accurately measuring the temperature of the device is the key to optimizing the performance of the device.
The self-heating phenomenon can be clearly seen in the dc characteristic, but it is not easy to determine the actual elevated temperature of the device itself, especially in the active region channel. The average temperature rise is influenced by factors such as the structure of the device, the selection of a substrate and other heat conducting materials, and the actual temperature rise value of the device cannot be accurately reflected.
Effective methods for measuring device temperature can be divided into electrical, optical and physical contact methods: the electrical method is conventional, non-invasive, rapid, and can use widely available standard equipment. These methods typically derive device temperature from the relationship between self-heating and saturation current reduction, and therefore accuracy depends on calibration techniques and assumptions made. The disadvantage is that the temperature measured electrically is the temperature averaged over the active area of the device and does not reflect the maximum temperature of the device; however, currently very little data is available to quantify the temperature error caused thereby. On the other hand, the optical method is also lossless, and only the energy of the used laser is lower than the forbidden band width. The optical method mainly comprises micro-Raman spectroscopy, and the method can realize the temperature and the spatial resolution as high as +/-5 ℃ and 0.5-0.7 mu m and is enough for detecting micron-sized devices. However, the optical method requires that the surface of the device must be detected, and the surface of the device cannot be detected for the device packaged in the integrated circuit, so the method is not suitable for junction temperature test in the integrated circuit and industrial production. Physical contact methods such as scanning thermal microscopy, thermal probe on atomic force microscopy, can achieve nanometer-scale spatial resolution, but the uncertainty of the thermal resistance of the tip of the atomic force microscope and the surface of the device makes it difficult to accurately determine the temperature of the device. In addition, the optical method and the physical contact method are not applicable in actual industrial production, and the micro-raman spectroscopy detects the average temperature of GaN, not only the channel temperature. The average temperature of the entire channel is measured electrically, but the factor that determines the performance of the device in practical applications is often the maximum temperature of the device. Therefore, a method is sought that can measure the maximum or near maximum temperature of the device.
The currently available common junction temperature testing techniques mainly include the following:
1. Raman spectroscopy: among the existing junction temperature testing techniques, the accuracy and resolution of the Raman test method for measuring junction temperature are high, and the references "Kim, Jihyun, Freitas, j.a., middle, j., pitch, r., Kang, b.s., Pearton, s.j., and Ren, f.," Effective temperature measurement mechanisms of algan/GaN-based HEMT under vacuum loads lines using micro-Raman technique, "Solid State Electronics, vol.50, No.3, pp.408-411, jan.2006.doi:10.1016/j.sse.2005.11.009. However, when testing using this method as described above, it is required that the device surface must be detectable and therefore not suitable for junction temperature testing in integrated circuits and industrial production.
2. Grid transmission resistance test method: according to the method, a temperature-sensitive resistor is added to the grid, and the purpose of junction temperature detection is achieved by utilizing a sensor technology. The accuracy is higher than that of a common electrical method, but additional process steps are needed, the difficulty of wiring and other processes during tape-out is increased, and the method is not suitable for junction temperature test in integrated circuits and industrial production. The method can be referred to as the following documents: "Georges Pavlidis, ShamitSom, Jason Barrett, Wayne Struble, and Samuel Graham," The Impact of Temperature on GaN/Si HEMTs Under RF Operation Using gateway resistance thermometer, "IEEE Transactions on Electron Devices, vol.66, No.1, pp.330-336, Jan.2019.doi:10.1109/TED.2018.2876207.
3. The first electrical method comprises the following steps: the purpose of junction temperature detection is realized by using the principles of source parasitic resistance, threshold voltage changing along with temperature and the like, which is proposed by J.Kuzmi i k and the like. The method can be applied to the fields of integrated circuits and the like, but the electron saturation velocity is constant in the measurement process, and Monte Carlo simulation shows that when the temperature is increased from 300K to 500K, the electron saturation velocity of GaN is reduced by 5.6%. Thus making its measurement less accurate than the actual temperature of the heterojunction.
4. And (3) an electrical method II: mcalister et al propose to achieve the purpose of junction temperature detection by using the principle that the saturation leakage current drop rate is different at different dissipation powers and different temperatures. The method can be widely applied to various fields of integrated circuits and the like, but the measurement result is the average temperature of the whole device, the temperature nonuniformity is not considered, and the accuracy is low.
Disclosure of Invention
The invention provides a junction temperature test method of an InAlN/GaN HEMT, aiming at solving the problem that the prior art method can not accurately measure the highest temperature of a channel of a lattice-matched InAlN/GaN heterojunction HEMT device.
a method for testing junction temperature of a lattice matched InAlN/GaN heterojunction HEMT, the method comprising:
Step 11, measuring a source-drain alternating temperature I-V curve (current-voltage curve) under the condition of constant grid voltage;
Step 12, calculating the linear zone resistance R at different temperatures according to the variable temperature I-V curve in the step 11onAnd selecting channel resistance below the grid as temperature sensitive parameter, and marking as RgTo obtain RgT-Curve (temperature sensitive parameter R)g-temperature profile); when 300K is selected, the resistance of the channel under the non-gate is a constant resistance, denoted as R0；
Step 13, measuring an I-V curve between a source and a drain in a self-heating steady state when the HEMT works under different dissipation power conditions;
Step 14, calculating the linear region resistance R through the I-V curve between the source and the drain in the step 13onR as a function of dissipated poweron-PdissCurve (linear region resistance R)on-a dissipated power curve); and take Rg＝Ron-R0As Rg-PdissCurve (temperature sensitive parameter R)g-a dissipated power curve);
Step 15, according to R in step 12 and step 14g-T curve and Rg-PdissThe curves are compared to obtain T-PdissThe curve is a regular curve of junction temperature along with the variation of dissipated power.
Optionally, R is obtained in step 12g-channel resistance R under the gate on the T-curvegthe value of (A) is the ratio of the gate length to the source-drain spacing and the linear region resistance RonThe product of (a); said to obtain Rg-a T-curve comprising:
Obtaining the linear zone resistance R at different temperatures according to the variable temperature I-V curve in the step 11onThen, the channel resistance R under the gate at different temperatures is calculatedgAnd further to obtain Rg-a T-curve.
Optionally, when 300K is selected, the channel resistance under the non-gate is a constant resistance value, which is denoted as R0The method comprises the following steps:
The linear region resistance R at different temperatures obtained in step 12onObtaining the resistance R of the linear region at 300KonA value of (d);
According to RgThe T curve yields the channel resistance R under the gate at 300KgA value of (d);
R0The value of (1) is the linear region resistance R at 300KonChannel resistance R under the gate at 300KgThe difference of (a).
Optionally, the constant gate voltage range in step 11 is 0 ± 3V.
Optionally, the voltage scanning range of the source-drain alternating temperature I-V curve in step 11 and the source-drain I-V curve in step 13 is 0-1V.
Optionally, the temperature variation range in the step 11 is 300-500K.
Optionally, the dissipated power in step 13 is in a range of 0-1000 mW.
Optionally, the self-heating steady state in step 13 refers to a corresponding state when the HEMT operates for 15min or more under different dissipation power conditions.
optionally, the length of the gate of the lattice-matched InAlN/GaN heterojunction HEMT is not more than 1/2 of the source-drain spacing.
Optionally, In and Al components In the lattice-matched InAlN/GaN heterojunction HEMT barrier layer are 0.17 and 0.83, respectively.
Optionally, in the step 12, the variable temperature I-V curve in the step 11 is used to calculate the linear region resistance R at different temperaturesonWhile, the linear region resistance RonThe inverse of the slope of the I-V curve.
the invention has the beneficial effects that:
By selecting the channel resistance R under the gategThe highest temperature of the channel of the lattice-matched InAlN/GaN heterojunction HEMT device is measured for temperature-sensitive parameters, so that the problems of inconvenience and inaccuracy in measurement of the highest temperature of the channel in the prior art are solved, and the highest temperature of the channel can be measured more conveniently and more accurately; the junction temperature test method can be faster, simpler and more convenient to operate, can more effectively measure the highest temperature of the channel of the lattice-matched InAlN/GaN heterojunction HEMT device, can be suitable for reliability test in integrated circuits and industrial production, and has the advantages that the measurement result is closer to the actual temperature and the accuracy is high.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart illustrating the steps of the testing method of the present invention.
FIG. 2 is a schematic diagram of a lattice matched InAlN/GaN heterojunction HEMT.
FIG. 3 is a temperature variation I-V curve between source and drain under a constant gate voltage condition in an embodiment of the present invention.
FIG. 4Is the channel resistance R under the grid under the condition of constant grid voltage in the embodiment of the inventiongCurve as a function of temperature.
FIG. 5 is an I-V curve between source and drain during self-heating steady state under operating conditions of different dissipation powers in an embodiment of the present invention.
FIG. 6 is the linear region resistance R in the self-heating steady state under the working conditions of different dissipation powers in the embodiment of the present inventiononDependent on dissipated power PdissThe change curve of (2).
FIG. 7 shows the steady state R of self-heating under different dissipation power operating conditions in an embodiment of the present inventiong＝Ron-R0p with dissipated powerdissThe change curve of (2).
FIG. 8 shows a graph of R in an example of the present inventiong-T curve and Rg-PdissT-P obtained by curve iterationdissCurve line.
Fig. 9 is a graph comparing test results of the method of the present invention with results of a currently existing junction temperature test method in an embodiment of the present invention.
Detailed Description
in order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
In the process of researching the lattice matching InAlN/GaN heterojunction HEMT device, the inventor conducts a temperature-changing high-frequency capacitance-voltage (C-V) test on the lattice matching InAlN/GaN heterojunction HEMT device through experiments, and can calculate the capacitance curve integral (from the starting voltage to V ═ 0): the two-dimensional electron gas (2DEG) areal density of the heterojunction interface is about 1.0 × 1013cm-2And the value thereof does not substantially change with temperature change.
Furthermore, thermal profile testing of the device during operation showed that: the high temperature region is distributed near the grid electrode and near the side of the drain electrode, and the length of the high temperature region is approximately equal to that of the grid electrode.
according to the findings, the channel resistance between the source and the drain is divided into two parts: the channel resistance under the gate and the channel resistance under the non-gate. As shown in fig. 2, a gridThe channel resistance under the pole is RgThe channel resistances under the non-gate are respectively at RgR on both sides01And R02. (S is source, D is drain, G is gate).
The former varies greatly with temperature, while the latter is substantially invariant with temperature. Based on the method, the channel resistance below the grid is selected as a temperature-sensitive parameter, and the accurate measurement of the highest temperature of the channel of the lattice-matched InAlN/GaN heterojunction HEMT device is completed.
The specific implementation mode is as follows:
The first embodiment is as follows:
The embodiment provides a method for testing junction temperature of a lattice-matched InAlN/GaN heterojunction HEMT, and with reference to FIG. 1, the method comprises the following steps:
and 11, measuring a source-drain alternating temperature I-V curve under the condition of constant grid voltage, as shown in figure 3.
Selecting a variable temperature I-V curve within the temperature change range of 300-500K, wherein the voltage scanning range corresponding to the variable temperature I-V curve is 0-1V.
Step 12, calculating the linear zone resistance R at different temperatures according to the variable temperature I-V curve in the step 11onAnd selecting channel resistance below the grid as temperature sensitive parameter, and marking as RgTo obtain Rg-T-curve, as shown in fig. 4; when 300K is selected, the resistance of the channel under the non-gate is a constant resistance, denoted as R0。
Channel resistance R under the gategThe value of (A) is the ratio of the gate length to the source-drain spacing and the linear region resistance Ronthe linear region resistance R at different temperatures is obtained according to the following formulaoncorresponding channel resistance R under the gateg。
Wherein L isGIs the gate length, LSGIs the length between source and gate, LGDThe length between the gate and the drain.
First according to step 11The variable temperature I-V curve is used for solving the linear region resistance R at different temperaturesonCalculating the channel resistance R under the gate at different temperatures according to the above formulagAnd further to obtain Rg-T-curve, as shown in FIG. 4. And step 13, measuring an I-V curve between the source and the drain in a self-heating steady state when the HEMT works under different dissipation power conditions, as shown in FIG. 5.
The voltage scanning range corresponding to the I-V curve is 0-1V.
The self-heating steady state refers to a corresponding state when the HEMT works for more than or equal to 15min under different dissipation power conditions.
Step 14, calculating the linear region resistance R through the I-V curve between the source and the drain in the step 13onr as a function of dissipated poweron-PdissCurves, as shown in fig. 6; and take Rg＝Ron-R0As Rg-PdissThe curves are shown in fig. 7.
In the making of Rg-PdissDuring the curve, the linear region resistance R at different temperatures obtained in step 12 is usedonObtaining the resistance R of the linear region at 300KonA value of (d);
According to RgThe T curve yields the channel resistance R under the gate at 300KgA value of (d);
R0The value of (1) is the linear region resistance R at 300Konchannel resistance R under the gate at 300KgThe difference of (a).
Then obtain Rg-Pdissthe curves are shown in fig. 7.
Step 15, according to R in step 12 and step 14g-T curve and Rg-PdissThe T-P can be obtained by curve comparisondissThe curve is a regular curve of junction temperature with dissipated power, as shown in fig. 8.
Fig. 9 is a graph comparing the results of the method of the present invention with the current electrical junction temperature test method, and it can be clearly seen that: compared with the test results of other electrical methods, the method has higher accuracy.
In the above-mentioned prior junction temperature testing method shown in FIG. 9, the first electrical method can be usedReference is made to "j.kuzmi i, p.javorka, a.alam, m.marso, m.heuken and P.“Determination of channel temperature in AlGaN/GaN HEMTs grown on sapphire and silicon substrates using DCcharacterization method,”IEEE Transactions on Electron Devices,vol.49,no.8,pp.1496-1498,May 2002.doi:10.1109/TED.2002.801430.”。
Reference is made to "S.P.McAlister, J.A.Bardwell, S.Haffouz, and H.Tang," Self-updating and the temperature dependency of the dc characteristics of GaNthermal engineering field effects transistors "Journal of Vacuum Science & Technology A, vol.24, No.3, pp.624-628, May 2006.doi:10.1116/1.2172921.
The pulsed current method may be referred to as "Mei Wu, Men Zhang, Qing Zhu, Ling Yang, Xiaohua Ma, and Yue Hao," Characterization of selection-Characterization in GaN high electron mobility transistors using channel resistance measurement "Japanese Journal of applied physics, vol.58, pp.SCCB11, Apr.2019.doi: 10.7567/1347-.
some steps in the embodiments of the present invention may be implemented by software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A junction temperature test method of a lattice-matched InAlN/GaN heterojunction HEMT is characterized by comprising the following steps:
step 11, measuring a source-drain alternating temperature I-V curve under the condition of constant grid voltage;
Step 12, calculating the linear zone resistance R at different temperatures according to the variable temperature I-V curve in the step 11onAnd selecting the channel resistance below the grid as a temperature-sensitive parameterIs denoted as RgTo obtain Rg-a T-curve; when 300K is selected, the resistance of the channel under the non-gate is a constant resistance, denoted as R0；
Step 13, measuring an I-V curve between a source and a drain in a self-heating steady state when the HEMT works under different dissipation power conditions;
Step 14, calculating the linear region resistance R through the I-V curve between the source and the drain in the step 13onR as a function of dissipated poweron-PdissA curve; and take Rg＝Ron-R0As Rg-PdissA curve;
Step 15, according to R in step 12 and step 14g-T curve and Rg-PdissThe curves are compared to obtain T-PdissThe curve is a regular curve of junction temperature along with the variation of dissipated power.
2. The method of claim 1, wherein R is obtained in step 12g-channel resistance R under the gate on the T-curvegThe value of (A) is the ratio of the gate length to the source-drain spacing and the linear region resistance RonThe product of (a); said to obtain Rg-a T-curve comprising:
Obtaining the linear zone resistance R at different temperatures according to the variable temperature I-V curve in the step 11onThen, the channel resistance R under the gate at different temperatures is calculatedgAnd further to obtain Rg-a T-curve.
3. The method of claim 2, wherein the channel resistance under the non-gate at 300K is selected to be a constant resistance, denoted as R0The method comprises the following steps:
The linear region resistance R at different temperatures obtained in step 12onObtaining the resistance R of the linear region at 300KonA value of (d);
According to RgThe T curve yields the channel resistance R under the gate at 300KgA value of (d);
R0The value of (1) is the linear region resistance R at 300KonChannel resistance R under the gate at 300KgThe difference of (a).
4. The method of claim 1, wherein the constant gate voltage range in step 11 is 0 ± 3V.
5. The method of claim 1, wherein the voltage sweep ranges of the source-drain alternating temperature I-V curve in step 11 and the source-drain I-V curve in step 13 are 0-1V.
6. the method as claimed in claim 1, wherein the temperature variation range in step 11 is 300-500K.
7. The method according to claim 1, wherein the dissipated power in step 13 is in the range of 0-1000 mW.
8. The method according to claim 1, wherein the self-heating steady state in step 13 refers to a state corresponding to a time period when the HEMT operates for 15min or more under different dissipation power conditions.
9. The method of claim 1, wherein the gate length of the lattice matched InAlN/GaN heterojunction HEMT does not exceed 1/2 of the source-drain spacing.
10. The method of claim 1, wherein the In and Al compositions of the lattice matched InAlN/GaN heterojunction HEMT barrier layer are 0.17 and 0.83, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910851323.4A CN110579698A (en) | 2019-09-10 | 2019-09-10 | Junction temperature test method of InAlN/GaN HEMT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910851323.4A CN110579698A (en) | 2019-09-10 | 2019-09-10 | Junction temperature test method of InAlN/GaN HEMT |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110579698A true CN110579698A (en) | 2019-12-17 |
Family
ID=68813045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910851323.4A Pending CN110579698A (en) | 2019-09-10 | 2019-09-10 | Junction temperature test method of InAlN/GaN HEMT |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110579698A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111913094A (en) * | 2020-06-24 | 2020-11-10 | 中国电子科技集团公司第五十五研究所 | GaN chip high junction temperature testing device based on Raman method |
| CN111983415A (en) * | 2020-08-20 | 2020-11-24 | 湖南大学 | Power device junction temperature on-line measuring system |
| CN113533922A (en) * | 2021-06-07 | 2021-10-22 | 大连理工大学 | Method for quickly and accurately measuring junction temperature of GaN power electronic device with Cascode structure |
| WO2022178857A1 (en) * | 2021-02-26 | 2022-09-01 | Innoscience (Suzhou) Technology Co., Ltd. | SYSTEM AND METHOD FOR MEASURING INTERMITTENT OPERATING LIFE OF GaN-BASED DEVICE |
| CN117928769A (en) * | 2024-03-21 | 2024-04-26 | 山东大学 | Method for determining channel carrier temperature of gallium nitride device |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61155775A (en) * | 1984-12-27 | 1986-07-15 | Fuji Electric Co Ltd | Measurement for thermal resistance of mos type fet |
| JPH11121575A (en) * | 1997-10-16 | 1999-04-30 | Nec Corp | Method for measuring thermal resistance and channel temperature of fet |
| CN102313863A (en) * | 2010-05-20 | 2012-01-11 | 赛米控电子股份有限公司 | Be used to verify the method for temperature of power semiconductor |
| TW201205778A (en) * | 2010-03-23 | 2012-02-01 | Sumitomo Electric Industries | Semiconductor device |
| KR101280228B1 (en) * | 2011-12-20 | 2013-07-05 | 전자부품연구원 | automatic multi channel withstand voltage and registance measuring system for thermister |
| CN104764988A (en) * | 2015-03-31 | 2015-07-08 | 株洲南车时代电气股份有限公司 | Failure testing circuit and method of power device |
| CN105891693A (en) * | 2016-04-27 | 2016-08-24 | 江南大学 | Method for detecting GaN-based HEMT degradation through current fitting |
| CN106896307A (en) * | 2017-01-18 | 2017-06-27 | 浙江大学 | A kind of modeling method of silicon carbide MOSFET on-resistance characteristics |
| US9778311B2 (en) * | 2014-09-05 | 2017-10-03 | Kabushiki Kaisha Toshiba | Semiconductor inspection apparatus |
| CN107422243A (en) * | 2017-08-28 | 2017-12-01 | 中国电子产品可靠性与环境试验研究所 | Gallium nitride HEMT device junction temperature test device, test board, test system and its method |
| CN108287300A (en) * | 2018-01-16 | 2018-07-17 | 北京工业大学 | A kind of method and apparatus measuring operating insulation grid-type field-effect transistor junction temperature |
-
2019
- 2019-09-10 CN CN201910851323.4A patent/CN110579698A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61155775A (en) * | 1984-12-27 | 1986-07-15 | Fuji Electric Co Ltd | Measurement for thermal resistance of mos type fet |
| JPH11121575A (en) * | 1997-10-16 | 1999-04-30 | Nec Corp | Method for measuring thermal resistance and channel temperature of fet |
| TW201205778A (en) * | 2010-03-23 | 2012-02-01 | Sumitomo Electric Industries | Semiconductor device |
| CN102313863A (en) * | 2010-05-20 | 2012-01-11 | 赛米控电子股份有限公司 | Be used to verify the method for temperature of power semiconductor |
| KR101280228B1 (en) * | 2011-12-20 | 2013-07-05 | 전자부품연구원 | automatic multi channel withstand voltage and registance measuring system for thermister |
| US9778311B2 (en) * | 2014-09-05 | 2017-10-03 | Kabushiki Kaisha Toshiba | Semiconductor inspection apparatus |
| CN104764988A (en) * | 2015-03-31 | 2015-07-08 | 株洲南车时代电气股份有限公司 | Failure testing circuit and method of power device |
| CN105891693A (en) * | 2016-04-27 | 2016-08-24 | 江南大学 | Method for detecting GaN-based HEMT degradation through current fitting |
| CN106896307A (en) * | 2017-01-18 | 2017-06-27 | 浙江大学 | A kind of modeling method of silicon carbide MOSFET on-resistance characteristics |
| CN107422243A (en) * | 2017-08-28 | 2017-12-01 | 中国电子产品可靠性与环境试验研究所 | Gallium nitride HEMT device junction temperature test device, test board, test system and its method |
| CN108287300A (en) * | 2018-01-16 | 2018-07-17 | 北京工业大学 | A kind of method and apparatus measuring operating insulation grid-type field-effect transistor junction temperature |
Non-Patent Citations (1)
| Title |
|---|
| MEI WU 等: "Accurate Measurement of Channel Temperature for AlGaN/GaN HEMTs", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111913094A (en) * | 2020-06-24 | 2020-11-10 | 中国电子科技集团公司第五十五研究所 | GaN chip high junction temperature testing device based on Raman method |
| CN111983415A (en) * | 2020-08-20 | 2020-11-24 | 湖南大学 | Power device junction temperature on-line measuring system |
| WO2022178857A1 (en) * | 2021-02-26 | 2022-09-01 | Innoscience (Suzhou) Technology Co., Ltd. | SYSTEM AND METHOD FOR MEASURING INTERMITTENT OPERATING LIFE OF GaN-BASED DEVICE |
| US12038469B2 (en) | 2021-02-26 | 2024-07-16 | Innoscience (Suzhou) Technology Co., Ltd. | System and method for measuring intermittent operating life of GaN-based device |
| CN113533922A (en) * | 2021-06-07 | 2021-10-22 | 大连理工大学 | Method for quickly and accurately measuring junction temperature of GaN power electronic device with Cascode structure |
| CN113533922B (en) * | 2021-06-07 | 2022-06-14 | 大连理工大学 | Method for quickly and accurately measuring junction temperature of GaN power electronic device with Cascode structure |
| CN117928769A (en) * | 2024-03-21 | 2024-04-26 | 山东大学 | Method for determining channel carrier temperature of gallium nitride device |
| CN117928769B (en) * | 2024-03-21 | 2024-05-31 | 山东大学 | Method for determining channel carrier temperature of gallium nitride device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110579698A (en) | Junction temperature test method of InAlN/GaN HEMT | |
| Simms et al. | Channel temperature determination in high-power AlGaN/GaN HFETs using electrical methods and Raman spectroscopy | |
| Kuball et al. | Measurement of temperature in active high-power AlGaN/GaN HFETs using Raman spectroscopy | |
| Dumka et al. | Electrical and thermal performance of AlGaN/GaN HEMTs on diamond substrate for RF applications | |
| Aktas et al. | High temperature characteristics of AlGaN/GaN modulation doped field‐effect transistors | |
| Benbakhti et al. | Effects of self-heating on performance degradation in AlGaN/GaN-based devices | |
| Yilmazoglu et al. | Measured negative differential resistivity for GaN Gunn diodes on GaN substrate | |
| Green et al. | Microwave power limits of AlGaN/GaN HEMTs under pulsed-bias conditions | |
| Cutivet et al. | Scalable modeling of transient self-heating of GaN high-electron-mobility transistors based on experimental measurements | |
| Pavlidis et al. | Monitoring the Joule heating profile of GaN/SiC high electron mobility transistors via cross-sectional thermal imaging | |
| Xu et al. | Discrete-pulsed current time method to estimate channel thermal resistance of GaN-based power devices | |
| Temcamani et al. | Electrical and physical analysis of thermal degradations of AlGaN/GaN HEMT under radar-type operating life | |
| Arenas et al. | Integration of micro resistance thermometer detectors in AlGaN/GaN devices | |
| Odabaşı et al. | Improved T MAX estimation in GaN HEMTs using an equivalent hot point approximation | |
| Raj et al. | Thermal analysis of AlGaN/GaN HEMT: Measurement and analytical modeling techniques | |
| Triendl et al. | Evaluation of interface trap characterization methods in 4H-SiC metal oxide semiconductor structures over a wide temperature range | |
| Wu et al. | Correlation between field dependent electrical conduction and dielectric breakdown in a SiCOH based low-k (k= 2.0) dielectric | |
| Dumka et al. | Evaluation of thermal resistance of AlGaN/GaN heterostructure on diamond substrate | |
| Wu et al. | Thermal resistance extraction of AlGaN/GaN depletion-mode HEMTs on diamond | |
| Yang et al. | Study on the heat transfer of GaN-based high power HEMTs | |
| Bremer et al. | Electric-based thermal characterization of GaN technologies affected by trapping effects | |
| Cutivet et al. | Thermal transient extraction for GaN HEMTs by frequency‐resolved gate resistance thermometry with sub‐100 ns time resolution | |
| Dalle et al. | Theoretical investigation of terahertz GaN mesa transferred-electron device by means of time-domain energy/momentum modeling | |
| Pavlidis et al. | Steady State and Transient Thermal Characterization of Vertical GaN PIN Diodes | |
| Chiu et al. | AlGaAs/InGaAs heterostructure doped-channel FET's exhibiting good electrical performance at high temperatures |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191217 |
|
| RJ01 | Rejection of invention patent application after publication |