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CN110519536A - Power supply noise processing circuit and processing method, reading circuit and imaging sensor - Google Patents

Power supply noise processing circuit and processing method, reading circuit and imaging sensor Download PDF

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Publication number
CN110519536A
CN110519536A CN201810497404.4A CN201810497404A CN110519536A CN 110519536 A CN110519536 A CN 110519536A CN 201810497404 A CN201810497404 A CN 201810497404A CN 110519536 A CN110519536 A CN 110519536A
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CN
China
Prior art keywords
vramp
operational amplifier
voltage signal
power supply
vrampc
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CN201810497404.4A
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Chinese (zh)
Inventor
裴学用
王飞
郭先清
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BYD Semiconductor Co Ltd
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BYD Co Ltd
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Priority to CN201810497404.4A priority Critical patent/CN110519536A/en
Publication of CN110519536A publication Critical patent/CN110519536A/en
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60Noise processing, e.g. detecting, correcting, reducing or removing noise
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/71Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75Circuitry for providing, modifying or processing image signals from the pixel array
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/76Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

This disclosure relates to a kind of power supply noise processing circuit and processing method, reading circuit and imaging sensor.The power supply noise processing circuit includes: ramp voltage signal generator and the comparator that is connected with the ramp voltage signal generator;The ramp voltage signal generator exports ramp voltage signal Vramp and the first fixed voltage signal Vrampc, and the generation mechanism of the Vramp is identical with the generation mechanism of the Vrampc, and the voltage value of the Vrampc is the first fixed value;The Vramp is input to the first input end of the comparator, and the output signal of single column of pixels and the Vrampc are separately input to the second input terminal of the comparator in pixel array.

Description

Power supply noise processing circuit and processing method, reading circuit and imaging sensor
Technical field
This disclosure relates to electronic circuit field, and in particular, to a kind of power supply noise processing circuit and processing method, reading Circuit and imaging sensor.
Background technique
CIS (CMOS image sensors) is become more and more popular due to the advantages that low in energy consumption, integrated level is high.CIS generally by Pixel array and corresponding reading circuit composition.Due to the unstability of power supply, per translated line pixel in practice will lead to When power environment it is inconsistent, cause the capable difference between row, i.e. power supply noise.The relevant technologies, which are not directed to power supply noise and do, to be located Reason.
Summary of the invention
Purpose of this disclosure is to provide a kind of power supply noise processing circuit and processing methods, reading circuit and image sensing Device, to eliminate power supply noise.
To achieve the goals above, disclosure first aspect provides a kind of power supply noise processing circuit, comprising:
Ramp voltage signal generator and the comparator being connected with the ramp voltage signal generator;
The ramp voltage signal generator exports ramp voltage signal Vramp and the first fixed voltage signal Vrampc, The generation mechanism of the Vramp is identical with the generation mechanism of the Vrampc, and the voltage value of the Vrampc is the first fixed value;
The Vramp is input to the first input end of the comparator, in pixel array the output signal of single column of pixels with And the Vrampc is separately input to the second input terminal of the comparator.
Optionally, the comparator includes: first capacitor C1, the second capacitor C2, third capacitor C3, the 4th capacitor C4, answers Position circuit, operational amplifier and buffer, the capacitance of described C1, C2, C3 and C4 are identical;
The reverse phase that the output signal of the single column of pixels of the pixel array is input to the operational amplifier through the C1 is defeated Enter end;
The Vramp is input to the non-inverting input terminal of the operational amplifier through the C2;
The Vrampc is input to the inverting input terminal of the operational amplifier through the C3;
Second fixed voltage signal Vc is input to the non-inverting input terminal of the operational amplifier, the production of the Vc through the C4 Life system is different from the generation mechanism of the Vrampc, and the voltage value of the Vc is the second fixed value;
The reset circuit is connected with the operational amplifier, controls the operational amplifier and resets or operate normally;
The output signal of the operational amplifier inputs the buffer.
Optionally, the reset circuit includes:
The non-inverting input terminal of the operational amplifier and the reversed-phase output of the operational amplifier is arranged in first switch Between;
The inverting input terminal of the operational amplifier and the in-phase output end of the operational amplifier is arranged in second switch Between;
When the first switch and the second switch are both turned on, the non-inverting input terminal of the operational amplifier and reversed Input terminal is shorted with the corresponding output end of the operational amplifier respectively, and the operational amplifier resets;
When the first switch and the second switch disconnect, the operational amplifier is operated normally.
Optionally, the power supply noise processing circuit further include:
Fixed voltage signal generator exports the Vc.
Optionally, each column pixel shares the Vramp, the Vrampc and the Vc in the pixel array.
Optionally, the ramp voltage signal generator includes: multiple current sources, multiple switch and resistance, and one is opened Pass is connected with a current source;
Switch conduction is specified in the multiple switch by controlling, so that the electric current that specified current flow source provides flows through the electricity Resistance, to generate the Vrampc;
By controlling the conducting and disconnection that other are switched in addition to the assigned switch in the multiple switch, so that quantity becomes The electric current that the current source of change provides flows through the resistance, to generate the Vramp.
Disclosure second aspect provides a kind of reading circuit, comprising:
Power supply noise processing circuit described in disclosure first aspect, the counting being connected with the power supply noise processing circuit Device, the digital processing circuit being connected with the counter.
The disclosure third aspect provides a kind of imaging sensor, comprising:
Pixel array, including multiple row pixel;
Reading circuit described in disclosure second aspect, each column pixel for including with the pixel array are respectively connected with.
Disclosure fourth aspect provides a kind of power supply based on power supply noise processing circuit described in disclosure first aspect Method for processing noise, comprising:
Obtain the ramp voltage signal Vramp and the first fixed voltage signal of the output of ramp voltage signal generator Vrampc;
The Vramp and the Vrampc are subtracted each other by comparator, to eliminate power supply noise.
Through the above technical solutions, it is solid to export ramp voltage signal Vramp and first by ramp voltage signal generator Determining voltage signal Vrampc, due to the production of the generation mechanism and the first fixed voltage signal Vrampc of ramp voltage signal Vramp Life system is identical, so when making the voltage value of ramp voltage signal Vramp from Vramp_max+ due to the presence of power supply noise When Δ Vramp is begun to decline, the voltage value of the first fixed voltage signal Vrampc also becomes Vrampc+ Δ Vramp simultaneously.Also It is to say, power supply noise can influence ramp voltage signal Vramp and the first fixed voltage signal Vrampc simultaneously, so that the two is synchronous Variation.Thus, ramp voltage signal Vramp is input to the first input end of comparator, by single column of pixels in pixel array Output signal and the first fixed voltage signal Vrampc are separately input to the second input terminal of comparator, in a comparator will be oblique Slope voltage signal Vramp subtracts each other with the first fixed voltage signal Vrampc, eliminates power supply noise.
Other feature and advantage of the disclosure will the following detailed description will be given in the detailed implementation section.
Detailed description of the invention
Attached drawing is and to constitute part of specification for providing further understanding of the disclosure, with following tool Body embodiment is used to explain the disclosure together, but does not constitute the limitation to the disclosure.In the accompanying drawings:
Fig. 1 is the schematic diagram of imaging sensor in the related technology.
Fig. 2 is the schematic diagram of ramp signal generator Vramp Gen in the related technology.
Fig. 3 is the schematic diagram of the corresponding comparator Comp of a single column of pixels Pixel in the related technology.
Fig. 4 is the schematic diagram for the power supply noise processing circuit that the embodiment of the present disclosure provides.
Fig. 5 is that the power supply for the power supply noise processing circuit provided based on the embodiment of the present disclosure that the embodiment of the present disclosure provides is made an uproar The schematic diagram of acoustic processing method.
Fig. 6 is the schematic diagram of ramp signal generator Vramp Gen in the embodiment of the present disclosure.
Fig. 7 is the schematic diagram for the imaging sensor that the embodiment of the present disclosure provides.
Specific embodiment
It is described in detail below in conjunction with specific embodiment of the attached drawing to the disclosure.It should be understood that this place is retouched The specific embodiment stated is only used for describing and explaining the disclosure, is not limited to the disclosure.
Before the power supply noise processing circuit provided the embodiment of the present disclosure is illustrated, first in the related technology Imaging sensor is illustrated.Imaging sensor in the related technology includes: ramp signal generator Vramp Gen, pixel battle array Column, comparator Comp, counter Counter and digital processing circuit.Fig. 1 is the signal of imaging sensor in the related technology Figure.Fig. 1 includes multiple single column of pixels Pixel signals with pixel array.Fig. 1 shares slope with each column pixel that pixel array includes The output signal of signal generator Vramp Gen is illustrated, specifically, the output signal of Vramp Gen be separately input to each The corresponding comparator Comp of single column of pixels Pixel, the output signal of each single column of pixels Pixel are input to the single column of pixels The corresponding comparator Comp of Pixel.It is single-row that Fig. 1 with the output signal of the corresponding comparator Comp of each single column of pixels is input to this The corresponding counter Counter signal of pixel.
Fig. 2 is the schematic diagram of ramp signal generator Vramp Gen in the related technology.As shown in Fig. 2, ramp signal occurs Device Vramp Gen includes: multiple current sources, multiple switch, resistance, output end and ground terminal vssr.Each current source and one A switch is connected, and one end of resistance is connected with ground terminal vssr, and the other end of resistance is connected with output end.
Firstly, all switches are closed, so that the electric current that all current sources provide flows through resistance, thus the electricity of output end output The voltage value for pressing signal is Vramp_max.Since the sum of current source is preset, and the resistance value of resistance is to set in advance Fixed, so Vramp_max is fixed and invariable.Then, each switch is disconnected one by one, so that providing the electric current of electric current for resistance The quantity in source gradually decreases, thus the voltage value of the voltage signal of output end output is gradually reduced, and forms ramp signal Vramp.
Due to the unstability of power supply, the ramp voltage signal Vramp of ramp generator Vramp Gen output is in decline Voltage value be (Vramp_max+ Δ Vramp), wherein Δ Vramp characterize power-supply fluctuation caused by ramp voltage signal Vramp Voltage value variation.
Fig. 3 is the schematic diagram of the corresponding comparator Comp of a single column of pixels Pixel in the related technology.As shown in figure 3, than It include: first capacitor C1, the second capacitor C2, operational amplifier opamp, switch S1 and buffer buffer compared with device Comp.It is single The output signal Vpix of column pixel Pixel is connected to the inverting input terminal Vn of operational amplifier opamp, slope through first capacitor C1 The ramp voltage signal Vramp of generator Vramp Gen output is connected to the same phase of operational amplifier opamp through the second capacitor C2 The anti-phase output of the non-inverting input terminal Vp and operational amplifier opamp of operational amplifier opamp is arranged in input terminal Vp, switch S1 Between end, and the same phase output of the inverting input terminal Vn and operational amplifier opamp of operational amplifier opamp is arranged in switch S1 Between end, the output end of operational amplifier opamp is connected with the input terminal of buffer buffer, the output end of buffer buffer It is connected with the input terminal of counter Counter.
The working principle of circuit shown in Fig. 3 is as follows:
Firstly, switch S1 be connected so that the non-inverting input terminal Vp and inverting input terminal Vn of operational amplifier opamp respectively with The corresponding output end of operational amplifier opamp is shorted, and operational amplifier opamp resets.At this point, operational amplifier opamp's is same The end voltage of phase input terminal Vp is Vp0, and the end voltage of the inverting input terminal Vn of operational amplifier opamp is Vn0, Vn0=Vp0= Vref (Vref is the voltage value determined by the size of operational amplifier opamp).
When operational amplifier opamp resets, the output signal Vpix of single column of pixels Pixel is Reset signal, is denoted as The voltage value of the ramp voltage signal Vramp of Vr, ramp voltage signal generator Vramp Gen output is Vramp_max, is counted Device Counter zero setting.
When operational amplifier opamp resets, the charge stored on first capacitor C1 be Qc1_0=C1* (Vn0-Vr)= The charge stored on C1* (Vref-Vr), the second capacitor C2 is Qc2_0=C2* (Vp0-Vramp_max)=C2* (Vref- Vramp_max), wherein C1 is the capacitance of first capacitor C1, and C2 is the capacitance of the second capacitor C2.
Then, switch S1 is disconnected, and the output signal Vpix of single column of pixels is signal signal, is denoted as Vs.It is disconnected in switch S1 After opening, the voltage value of the ramp voltage signal Vramp of ramp voltage signal generator Vramp Gen output is by Vramp_max It begins to decline, meanwhile, counter Counter is started counting, and counter Counter is for recording from ramp voltage signal Vramp Voltage value at the time of begin to decline to comparator Comp output switching activity at the time of between duration, and convert thereof into clock week Issue is exported in the form of binary.
Wherein, comparator Comp output switching activity occur operational amplifier opamp non-inverting input terminal Vp end voltage with At the time of the end voltage of the inverting input terminal Vn of operational amplifier opamp is equal.
Specifically, when under the voltage value of the ramp voltage signal Vramp of ramp voltage signal generator Vramp Gen output When dropping to Vramp_max- (Vr-Vs), the non-inverting input terminal Vp in operational amplifier opamp occurs for comparator Comp output switching activity End voltage it is equal with the end voltage of inverting input terminal Vn of operational amplifier opamp, comparator Comp output switching activity, thus count Number device Counter stops counting, and completes the conversion to (Vr-Vs).
Due to the unstability of power supply, the ramp voltage signal Vramp of ramp generator Vramp Gen output is under Voltage value when drop is (Vramp_max+ Δ Vramp), wherein Δ Vramp characterizes ramp voltage signal caused by power-supply fluctuation The voltage value of Vramp changes.
At this point, the end voltage of the non-inverting input terminal Vp of operational amplifier opamp is Vp1, the reverse phase of operational amplifier opamp The end voltage of input terminal Vn is Vn1, then the charge stored on first capacitor C1 is Qc1_1=C1* (Vn1-Vs), the second capacitor C2 The charge of upper storage is Qc2_1=C2* [Vp1- (Vramp_max+ Δ Vramp)].
From charge conservation: Qc1_1=Qc1_0, that is, C1* (Vn1-Vs)=C1* (Vref-Vr) → Vn1-Vs= Vref-Vr, and then obtain Vn1=Vref- (Vr-Vs);Similarly, from charge conservation: Qc2_1=Qc2_0, that is, C2* [Vp1- (Vramp_max+ Δ Vramp)]=C2* (Vref-Vramp_max) → Vp1- (Vramp_max+ Δ Vramp)= Vref-Vramp_max, and then obtain Vp1=Vref+ Δ Vramp.Then Vp1-Vn1=Δ Vramp+ (Vr-Vs).It can not eliminate Power supply noise Δ Vramp.
Aiming at the problem that not processing in the prior art to power supply noise, the embodiment of the present disclosure is proposed at a kind of power supply noise Circuit is managed, to eliminate power supply noise.Fig. 4 is the schematic diagram for the power supply noise processing circuit that the embodiment of the present disclosure provides.Such as Fig. 4 institute Show, the power supply noise processing circuit that the embodiment of the present disclosure provides includes: ramp voltage signal generator Vramp Gen and and slope Voltage signal generator Vramp Gen connected comparator Comp.
Wherein, ramp voltage signal generator Vramp Gen exports ramp voltage signal Vramp and the first fixed voltage letter Number Vrampc, the generation mechanism of Vramp and the generation mechanism of Vrampc are identical, and the voltage value of Vrampc is the first fixed value. Vramp is input to the first input end of comparator Comp, in pixel array the output signal Vpix of single column of pixels Pixel and Vrampc is separately input to the second input terminal of comparator Comp.
Based on power supply noise processing circuit described in Fig. 4, the disclosure also provides a kind of power supply noise processing method.Fig. 5 is The power supply noise processing method for the power supply noise processing circuit provided based on the embodiment of the present disclosure that the embodiment of the present disclosure provides Schematic diagram.As shown in figure 5, this method comprises:
Step S11: the ramp voltage signal Vramp and the first fixed voltage letter of the output of ramp voltage signal generator are obtained Number Vrampc;
Step S12: the Vramp and the Vrampc are subtracted each other by comparator, to eliminate power supply noise.
In the embodiment of the present disclosure, ramp voltage signal generator Vramp Gen exports two-way voltage signal, first via voltage Signal is ramp voltage signal Vramp, and the second road voltage signal is the first fixed voltage signal Vrampc, ramp voltage signal The generation mechanism of the generation mechanism of Vramp and the first fixed voltage signal Vrampc are identical, and the first fixed voltage signal The voltage value of Vrampc is the first fixed value.
Due to the generation mechanism of ramp voltage signal Vramp and the generation mechanism phase of the first fixed voltage signal Vrampc Together, so when opening the voltage value of ramp voltage signal Vramp from Vramp_max+ Δ Vramp due to the presence of power supply noise When beginning to decline, the voltage value of the first fixed voltage signal Vrampc also becomes Vrampc+ Δ Vramp simultaneously.That is, power supply Noise can influence ramp voltage signal Vramp and the first fixed voltage signal Vrampc simultaneously, so that the synchronous variation of the two.
In order to eliminate power supply noise, ramp voltage signal Vramp is input to the first input end of comparator, by pixel battle array The output signal of single column of pixels and the first fixed voltage signal Vrampc are separately input to the second input terminal of comparator in column, Ramp voltage signal Vramp and the first fixed voltage signal Vrampc are subtracted each other in a comparator, power supply noise is eliminated with this.
Fig. 6 is the schematic diagram of ramp signal generator Vramp Gen in the embodiment of the present disclosure.As shown in fig. 6, ramp signal Generator Vramp Gen includes: multiple current sources, multiple switch, resistance, output end and ground terminal vssr.Each current source It is connected with a switch.
Multiple current source middle finger constant current sources and assigned switch are for generating the first fixed voltage signal Vrampc.Specifically Ground is closed assigned switch, so that the electric current that the specified current flow source being connected with assigned switch provides flows through resistance, it is solid to generate first Determining voltage signal Vrampc, assigned switch closure just no longer disconnect later, to guarantee the electricity of the first fixed voltage signal Vrampc Pressure value is the first fixed value.
Firstly, in other current sources and multiple switch in multiple current sources in addition to specified current flow source in addition to assigned switch Other switch and with other switch for generating ramp voltage signal Vramp.Firstly, it is closed every other switch, so that The electric current that every other current source provides flows through resistance, thus the ramp voltage letter of ramp signal generator Vramp Gen output The voltage value of number Vramp is maximum, as Vramp_max.Since the sum of current source is preset, and the resistance value of resistance is It is preset, so Vramp_max is fixed and invariable.Then, other each switches are disconnected one by one, so that providing for resistance The quantity of the current source of electric current gradually decreases, thus ramp signal generator Vramp Gen output voltage values are opened by Vramp_max The ramp voltage signal Vramp that beginning voltage value is gradually reduced.
Due to the unstability of power supply, the ramp voltage signal Vramp of ramp generator Vramp Gen output is in voltage value Voltage value when decline is (Vramp_max+ Δ Vramp), wherein Δ Vramp, which characterizes ramp voltage caused by power-supply fluctuation, to be believed The voltage value variation of number Vramp.
As shown in figure 4, comparator Comp includes: the first electricity in the power supply noise processing circuit that the embodiment of the present disclosure provides Hold C1, the second capacitor C2, third capacitor C3, the 4th capacitor C4, reset circuit, operational amplifier and buffer buffer, institute The capacitance for stating C1, C2, C3 and C4 is identical, is C;
The reverse phase that the output signal of the single column of pixels of the pixel array is input to the operational amplifier through the C1 is defeated Enter end;
The Vramp is input to the non-inverting input terminal of the operational amplifier through the C2;
The Vrampc is input to the inverting input terminal of the operational amplifier through the C3;
Second fixed voltage signal Vc is input to the non-inverting input terminal of the operational amplifier, the production of the Vc through the C4 Life system is different from the generation mechanism of the Vrampc, and the voltage value of the Vc is the second fixed value;
The reset circuit is connected with the operational amplifier, controls the operational amplifier and resets or operate normally;
The output signal of the operational amplifier inputs the buffer.
The working principle for the power supply noise processing circuit that the embodiment of the present disclosure provides is as follows:
Firstly, reset circuit control operational amplifier opamp resets.At this point, the non-inverting input terminal of operational amplifier opamp The end voltage of Vp is Vp0, and the end voltage of the inverting input terminal Vn of operational amplifier opamp is Vn0, Vn0=Vp0=Vref (Vref is the voltage value determined by the size of operational amplifier opamp).
When operational amplifier opamp resets, the charge stored on first capacitor C1 be Qc1_0=C1* (Vn0-Vr)= The charge stored on C* (Vref-Vr), the second capacitor C2 is Qc2_0=C2* (Vp0-Vramp_max)=C* (Vref-Vramp_ Max), the charge stored on third capacitor C3 is Qc3_0=C3* (Vn0-Vrampc)=C* (Vref-Vrampc), the 4th capacitor The charge stored on C4 is Qc4_0=C4* (Vp0-Vc)=C* (Vref-Vc).
When operational amplifier opamp resets, the output signal Vpix of single column of pixels Pixel is Reset signal, is denoted as The voltage value of the ramp voltage signal Vramp of Vr, ramp voltage signal generator Vramp Gen output is Vramp_max.
Then, reset circuit control operational amplifier opamp is operated normally, and the output signal Vpix of single column of pixels is Signal signal, is denoted as Vs.
After reset circuit control operational amplifier opamp is operated normally, ramp voltage signal generator Vramp Gen The voltage value of the ramp voltage signal Vramp of output is begun to decline by Vramp_max,
Due to the unstability of power supply, the ramp voltage signal Vramp of ramp generator Vramp Gen output is under Voltage value when drop is (Vramp_max+ Δ Vramp), wherein Δ Vramp characterizes ramp voltage signal caused by power-supply fluctuation The voltage value of Vramp changes.
At this point, the end voltage of the non-inverting input terminal Vp of operational amplifier opamp is Vp1, the reverse phase of operational amplifier opamp The end voltage of input terminal Vn is Vn1, then the charge stored on first capacitor C1 is Qc1_1=C1* (Vn1-Vs)=C* (Vn1- Vs), the charge stored on the second capacitor C2 is Qc2_1=C2* [Vp1- (Vramp_max+ Δ Vramp)]=C* [Vp1- (Vramp_max+ Δ Vramp)], the charge stored on third capacitor C3 is Qc3_1=C3* [Vn1- (Vrampc+ Δ Vramp)] The charge stored on=C* [Vn1- (Vrampc+ Δ Vramp)], the 4th capacitor C4 is Qc4_1=C4* (Vp1-Vc)=C* (Vp1-Vc)。
From charge conservation: Qc1_1+Qc3_1=Qc1_0+Qc3_0, that is, C* (Vn1-Vs)+C* [Vn1- (Vrampc+ Δ Vramp)]=C* (Vref-Vr)+C* (Vref-Vrampc), and then obtain Vn1=Vref- (Vr-Vs)/2+ Δ Vramp/2; Similarly, from charge conservation: Qc2_1+Qc4_1=Qc2_0+Qc4_0, that is, C* [Vp1- (Vramp_max+ Δ Vramp)]+ C* (Vp1-Vc)=C* (Vref-Vramp_max)+C* (Vref-Vc), and then obtain Vref+ Δ Vramp/2.Then Vp1-Vn1= (Vr-Vs)/2.Vp1-Vn1 is unrelated with power supply noise Δ Vramp, so eliminating power supply noise.
In one embodiment, the reset circuit includes:
The non-inverting input terminal of the operational amplifier and the reversed-phase output of the operational amplifier is arranged in first switch Between;
The inverting input terminal of the operational amplifier and the in-phase output end of the operational amplifier is arranged in second switch Between;
When the first switch and the second switch are both turned on, the non-inverting input terminal of the operational amplifier and reversed Input terminal is shorted with the corresponding output end of the operational amplifier respectively, and the operational amplifier resets;
When the first switch and the second switch disconnect, the operational amplifier is operated normally.
As shown in figure 4, the non-inverting input terminal Vp and operational amplifier opamp of operational amplifier opamp is arranged in switch S1 Reversed-phase output between, and the inverting input terminal Vn and operational amplifier opamp of operational amplifier opamp is arranged in switch S1 In-phase output end between.Switch S1 conducting, so that the non-inverting input terminal Vp and inverting input terminal Vn of operational amplifier opamp points It is not shorted with the corresponding output end of operational amplifier opamp, operational amplifier opamp resets.Switch S1 is disconnected, so that operation is put Big device opamp is operated normally.
In one embodiment, the power supply noise processing circuit that the embodiment of the present disclosure provides further include:
Fixed voltage signal generator exports the Vc.
Wherein, fixed voltage signal generator can adopt generation fixed voltage signal by any known method, as long as raw At the voltage value of voltage signal be fixed value, the voltage signal fixed value that fixed voltage signal generator generates can be with The voltage value of Vrampc is identical, can also be different, and the disclosure is without limitation.
In one embodiment, each column pixel shares the Vramp, the Vrampc and institute in the pixel array State Vc.That is, the output signal Vramp and Vrampc of Vc and Vramp Gen are separately input to and each single column of pixels Pixel Corresponding comparator Comp, the output signal of each single column of pixels Pixel are input to the corresponding comparator of single column of pixels Pixel Comp。
Based on the same inventive concept, the embodiment of the present disclosure also provides a kind of reading circuit, comprising:
The power supply noise processing circuit of embodiment of the present disclosure offer, the counting being connected with the power supply noise processing circuit Device, the digital processing circuit being connected with the counter.
The working principle for the reading circuit that the embodiment of the present disclosure provides is as follows:
Firstly, control operational amplifier opamp resets, when operational amplifier opamp resets, counter Counter is set Zero.
Then, control operational amplifier opamp is operated normally, and ramp voltage signal generator Vramp Gen is exported oblique The voltage value of slope voltage signal Vramp is begun to decline by Vramp_max, meanwhile, counter Counter is started counting, counter Counter is for recording at the time of beginning to decline from the voltage value of ramp voltage signal Vramp to comparator Comp output switching activity At the time of between duration, and convert thereof into clock periodicity, exported in the form of binary.
Wherein, comparator Comp output switching activity occur operational amplifier opamp non-inverting input terminal Vp end voltage with At the time of the end voltage of the inverting input terminal Vn of operational amplifier opamp is equal.
Specifically, when under the voltage value of the ramp voltage signal Vramp of ramp voltage signal generator Vramp Gen output When dropping to Vramp_max- (Vr-Vs), the non-inverting input terminal Vp in operational amplifier opamp occurs for comparator Comp output switching activity End voltage it is equal with the end voltage of inverting input terminal Vn of operational amplifier opamp, comparator Comp output switching activity, thus count Number device Counter stops counting, and completes the conversion to (Vr-Vs).
Based on the same inventive concept, the embodiment of the present disclosure also provides a kind of imaging sensor, comprising:
Pixel array, including multiple row pixel;
The reading circuit that the embodiment of the present disclosure provides, each column pixel for including with the pixel array are respectively connected with.
Fig. 7 is the schematic diagram for the imaging sensor that the embodiment of the present disclosure provides.As shown in fig. 7, the embodiment of the present disclosure provides Imaging sensor include: ramp signal generator Vramp Gen, pixel array, comparator Comp, counter Counter with And digital processing circuit.Fig. 7 includes multiple single column of pixels Pixel signals with pixel array.Each column that Fig. 7 includes with pixel array Pixel shares output signal Vramp and the Vrampc signal of ramp signal generator Vramp Gen, and Fig. 7 is with pixel array Including each column pixel share Vc signal.That is, the output signal Vramp and Vrampc of Vc and Vramp Gen are inputted respectively To comparator Comp corresponding with each single column of pixels Pixel, it is single-row that the output signal of each single column of pixels Pixel is input to this The corresponding comparator Comp of pixel Pixel.Fig. 7 is input to this with the output signal of the corresponding comparator Comp of each single column of pixels The corresponding counter Counter signal of single column of pixels.The corresponding comparator Comp of each single column of pixels is disclosure reality in Fig. 7 Comparator Comp in the power supply noise processing circuit of example offer is provided.
The preferred embodiment of the disclosure is described in detail in conjunction with attached drawing above, still, the disclosure is not limited to above-mentioned reality The detail in mode is applied, in the range of the technology design of the disclosure, a variety of letters can be carried out to the technical solution of the disclosure Monotropic type, these simple variants belong to the protection scope of the disclosure.
It is further to note that specific technical features described in the above specific embodiments, in not lance In the case where shield, can be combined in any appropriate way, in order to avoid unnecessary repetition, the disclosure to it is various can No further explanation will be given for the combination of energy.
In addition, any combination can also be carried out between a variety of different embodiments of the disclosure, as long as it is without prejudice to originally Disclosed thought equally should be considered as disclosure disclosure of that.

Claims (9)

1. a kind of power supply noise processing circuit characterized by comprising
Ramp voltage signal generator and the comparator being connected with the ramp voltage signal generator;
Ramp voltage signal generator output ramp voltage signal Vramp and the first fixed voltage signal Vrampc, it is described The generation mechanism of Vramp is identical with the generation mechanism of the Vrampc, and the voltage value of the Vrampc is the first fixed value;
The Vramp is input to the first input end of the comparator, the output signal of single column of pixels and institute in pixel array State the second input terminal that Vrampc is separately input to the comparator.
2. power supply noise processing circuit according to claim 1, which is characterized in that the comparator includes: first capacitor C1, the second capacitor C2, third capacitor C3, the 4th capacitor C4, reset circuit, operational amplifier and buffer, the C1, C2, The capacitance of C3 and C4 is identical;
The output signal of the single column of pixels of the pixel array is input to the inverting input terminal of the operational amplifier through the C1;
The Vramp is input to the non-inverting input terminal of the operational amplifier through the C2;
The Vrampc is input to the inverting input terminal of the operational amplifier through the C3;
Second fixed voltage signal Vc is input to the non-inverting input terminal of the operational amplifier, the generation machine of the Vc through the C4 System is different from the generation mechanism of the Vrampc, and the voltage value of the Vc is the second fixed value;
The reset circuit is connected with the operational amplifier, controls the operational amplifier and resets or operate normally;
The output signal of the operational amplifier inputs the buffer.
3. power supply noise processing circuit according to claim 2, which is characterized in that the reset circuit includes:
First switch, be arranged in the operational amplifier non-inverting input terminal and the operational amplifier reversed-phase output it Between;
Second switch, be arranged in the operational amplifier inverting input terminal and the operational amplifier in-phase output end it Between;
When the first switch and the second switch are both turned on, the non-inverting input terminal of the operational amplifier and reversed input End is shorted with the corresponding output end of the operational amplifier respectively, and the operational amplifier resets;
When the first switch and the second switch disconnect, the operational amplifier is operated normally.
4. power supply noise processing circuit according to claim 2, which is characterized in that further include:
Fixed voltage signal generator exports the Vc.
5. power supply noise processing circuit according to claim 2, which is characterized in that each column pixel is total in the pixel array With the Vramp, the Vrampc and the Vc.
6. power supply noise processing circuit according to claim 1, which is characterized in that the ramp voltage signal generator packet Include: multiple current sources, multiple switch and resistance, a switch are connected with a current source;
Switch conduction is specified in the multiple switch by controlling, so that the electric current that specified current flow source provides flows through the resistance, To generate the Vrampc;
By controlling the conducting and disconnection that other are switched in addition to the assigned switch in the multiple switch, so that quantity variation The electric current that current source provides flows through the resistance, to generate the Vramp.
7. a kind of reading circuit characterized by comprising
Claim 1-6 any power supply noise processing circuit, the counter that is connected with the power supply noise processing circuit, The digital processing circuit being connected with the counter.
8. a kind of imaging sensor characterized by comprising
Pixel array, including multiple row pixel;
Reading circuit as claimed in claim 7, each column pixel for including with the pixel array are respectively connected with.
9. a kind of power supply noise processing method based on any power supply noise processing circuit of claim 1-6, feature It is, comprising:
Obtain the ramp voltage signal Vramp and the first fixed voltage signal Vrampc of the output of ramp voltage signal generator;
The Vramp and the Vrampc are subtracted each other by comparator, to eliminate power supply noise.
CN201810497404.4A 2018-05-22 2018-05-22 Power supply noise processing circuit and processing method, reading circuit and imaging sensor Pending CN110519536A (en)

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