CN110415647B

CN110415647B - System for driving a display

Info

Publication number: CN110415647B
Application number: CN201910687137.1A
Authority: CN
Inventors: 亚沙尔·阿齐兹; 戈尔拉玛瑞扎·恰吉
Original assignee: Ignis Innovation Inc
Current assignee: Ignis Innovation Inc
Priority date: 2014-09-02
Filing date: 2015-09-02
Publication date: 2024-07-05
Anticipated expiration: 2035-09-02
Also published as: CN105390094A; DE102015216798A1; CN105390094B; CN110415647A

Abstract

The invention relates to a system for driving a display, the system comprising: a display module, the display module comprising: a display panel having a plurality of pixel circuits arranged in an array, each of the pixel circuits including a light emitting device and a driving transistor for transmitting a driving current flowing through the light emitting device; and a display driver including a plurality of frame buffers for driving the display panel, receiving and storing standby frame data for displaying a plurality of standby frames before entering a standby mode, and controlling display of the plurality of standby frames on the display panel during the standby mode; and a host system connected to the display module to transmit the standby frame data to the display driver before the standby mode.

Description

System for driving a display

The present application is a divisional application of patent application No. 2015155564. X, having application date 2015, 9, 2 and entitled "system for driving display".

Technical Field

The present invention relates generally to circuits used in displays, and in particular active matrix organic light emitting diode (active matrix organic LIGHT EMITTING diode, AMOLED) displays, and methods for driving, correcting, and programming displays.

Background

The display may be fabricated by an array of light emitting devices, each controlled by a separate circuit (i.e., pixel circuit) having transistors for selective control to program the circuits for display information and cause them to emit light in accordance with the display information. Thin film transistors ("TFTs") fabricated on the substrate may be incorporated into such displays. As the display ages, TFTs tend to exhibit non-uniform characteristics throughout the display panel. Compensation techniques may be applied to such displays to achieve image uniformity of the display and to eliminate degradation of the display as the display ages.

In some schemes for providing compensation for a display to eliminate time-dependent variations in the overall display panel, a monitoring system is utilized to measure time-dependent parameters related to aging (i.e., degradation) of the pixel circuits. The measured information can then be used to inform subsequent programming of the pixel circuit to ensure that any measured degradation is eliminated by adjusting the programming. Such monitored pixel circuits may require the use of additional transistors and/or wiring to selectively connect the pixel circuits to the monitoring system and provide for reading out the information. The addition of additional transistors and/or lines may undesirably reduce the pixel pitch (i.e., pixel density).

Disclosure of Invention

According to one embodiment of the invention, a method and system for determining characteristics of a driving device and a load device in selected ones of an array of pixels in a display, each of the pixels comprising the driving device for supplying current to the load device, is provided. The method and the system are as follows: in the selected pixel, supplying a current to the load device via the drive device, the current being a function of a current-efficient characteristic of at least one of the drive device and the load device; measuring the current via a measurement line shared by adjacent ones of the pixels; and extracting a value of a selected effective characteristic of one of the drive device and the load device based on an effect of the current on the other of the drive device and the load device.

According to another embodiment, a method and system for driving a display including a plurality of pixel circuits arranged in an array is provided. Each of the pixel circuits includes a light emitting device and a driving transistor for transmitting a driving current flowing through the light emitting device. Each of the power lines of a first plurality of power lines is associated with at least one of the pixel circuits in a preselected segment of the array, the first plurality of power lines providing drive current to the at least one pixel circuit in the preselected segment. Each of a plurality of voltage supplies for providing a supply voltage to said at least one pixel circuit in said preselected segment of said array, said voltage supplies being controllably connected to said pixel circuits in said preselected segment of said array. A controller is used to determine which of the plurality of voltage sources is connected to the preselected segment of the array.

In one embodiment, the current is provided to the load device in each of the pixels via the drive devices in each of the pixels, and the current is measured via a read transistor in each of the pixels. The current is measured in different states and the selected effective characteristic is extracted from the measurement.

In another embodiment, a controllable switch connects the voltage supply to the at least one pixel circuit in the preselected segment of the array.

The foregoing and other aspects and embodiments of the present invention will become more apparent to those of ordinary skill in the art after reviewing the detailed description of the various embodiments and/or aspects of the present invention. The above detailed description is made by referring to the accompanying drawings, which will be briefly described below.

Drawings

The above advantages and other advantages of the present invention will become more apparent upon reading the following detailed description and upon reference to the accompanying drawings.

Fig. 1 is a block diagram of an exemplary configuration of a system for driving an OLED display while monitoring degradation of individual pixels and providing compensation therefor.

Fig. 2A is a circuit diagram of a configuration of an exemplary pixel circuit.

Fig. 2B is a timing diagram of a first exemplary period of operation of the pixel shown in fig. 2A.

Fig. 2C is a timing diagram of a second exemplary period of operation of the pixel shown in fig. 2A.

Fig. 3 is a circuit diagram of another exemplary pixel circuit configuration.

Fig. 4 is a block diagram of a variant configuration of a system for driving an OLED display using a common readout circuit while monitoring degradation of individual pixels and providing compensation therefor.

Fig. 5 is a schematic diagram of a pixel circuit with a drive transistor, an optoelectronic device and a measurement line.

Fig. 6 is a circuit diagram of a pair of pixel circuits having a common monitor line.

Fig. 7 is a schematic diagram of a display with segmented VDD for power conservation.

Fig. 8 is a schematic diagram of a circuit for regulating a power supply at a segment level.

Fig. 9A is a schematic diagram of a circuit for regulating the power supplied to a pixel from a Vdd source.

Fig. 9B is a schematic diagram of a circuit for regulating the power supplied to a pixel from a Vss source.

Fig. 10 is a schematic diagram of a pixel arrangement for adjusting power supply at a pixel level.

Fig. 11 is a block diagram of a system in standby mode with a display displaying active content.

FIG. 12 is a block diagram of a display module having multiple frame buffers for supporting active content during standby.

Fig. 13 is a block diagram of a display module having a frame buffer and a content generator module for supporting active content during standby.

While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Detailed Description

Fig. 1 is a diagram of an exemplary display system 50. The display system 50 includes an address driver 8, a data driver 4, a controller 2, a memory 6, and a display panel 20. The display panel 20 comprises an array of pixels 10 arranged in rows and columns. Each pixel 10 can be individually programmed to emit light having an individually programmable intensity value. The controller 2 receives digital data indicating information to be displayed on the display panel 20. The controller 2 sends a signal 32 to the data driver 4 and a scheduling signal (scheduling signal) 34 to the address driver 8 to drive the pixels 10 in the display panel 20 to display the indicated information. Thus, the plurality of pixels 10 associated with the display panel 20 comprise a display array (display screen) adapted to dynamically display information in accordance with input digital data received by the controller 2. The display screen may display video information, for example, from a video data stream received by the controller 2. The voltage supply 14 may provide a constant supply voltage or may be an adjustable voltage supply controlled by a signal from the controller 2. The display system 50 may also include a current source or current sink (not shown) feature to provide bias current to the pixels 10 in the display panel 20, thereby reducing the programming time of the pixels 10.

For exemplary purposes, the display system 50 in FIG. 1 is illustrated by only four pixels 10 in the display panel 20. It should be appreciated that display system 50 may be implemented as a display screen having an array of similar pixels, such as pixels 10, and that the display screen is not limited to a particular number of rows and columns of pixels. For example, display system 50 may be implemented as a display screen having rows and columns of pixels commonly used in displays for mobile devices, monitor-like devices, and/or projection devices.

The pixel 10 is operated by a drive circuit (pixel circuit) typically including a drive transistor and a light emitting device. Hereinafter, the pixel 10 may refer to a pixel circuit. Alternatively, the light emitting device may be an organic light emitting diode, but the practice of the invention is applicable to pixel circuits having other electroluminescent devices, including current driven light emitting devices. Alternatively, the drive transistor in the pixel 10 may be an amorphous silicon thin film transistor of n-type or p-type, but the implementation of the present invention is not limited to a pixel circuit with a specific polarity transistor or to a pixel circuit with a thin film transistor only. The pixel circuit 10 may further include a storage capacitor for storing programming information and allowing the pixel circuit 10 to drive the light emitting device that has been addressed. Accordingly, the display panel 20 may be an active matrix display array.

As shown in fig. 1, the pixel 10 illustrated as the upper left pixel in the display panel 20 is connected to a selection line 24i, a power supply line 26i, a data line 22j, and a monitor line 28j. A read line may also be included to control the connection to the monitor line. In one embodiment, the voltage supply 14 may also provide a second power supply line to the pixel 10. For example, each pixel may be connected to a first power supply line 26 charged with Vdd and a second power supply line 27 charged with Vss, and the pixel circuit 10 may be located between the first and second power supply lines to facilitate a drive current between the two power supply lines during a light-emitting phase of the pixel circuit. The upper left pixel 10 in the display panel 20 may correspond to the pixels of the ith row and jth column in the display panel 20 in the display panel. Similarly, the upper right pixel 10 in the display panel 20 represents the ith row and the mth column; the lower left pixel 10 represents the nth row and the jth column; and the lower right pixel 10 represents the nth row and the mth column. Each pixel 10 is connected to appropriate select lines (e.g., select lines 24i and 24 n), power lines (e.g., power lines 26i, 26n and 27i, 27 n), data lines (e.g., data lines 22j and 22 m), and monitor lines (e.g., monitor lines 28j and 28 m). Note that aspects of the present invention are applicable to pixels having other connections, such as connections to other select lines, and to pixels having fewer connections, such as pixels lacking connections to monitor lines.

Referring to the upper left pixel 10 shown in display panel 20, select line 24i is provided by address driver 8 and may be used to initiate a programming operation of pixel 10, for example by activating a switch or transistor to cause data line 22j to program pixel 10. The data line 22j transmits programming information from the data driver 4 to the pixel 10. For example, the data line 22j may be used to apply a programming voltage or programming current to the pixel 10 in order to program the pixel 10 to emit a desired amount of brightness. The program voltage (or program current) supplied by the data driver 4 via the data line 22j is the following voltage (or current): the voltage (or current) is adapted to cause the pixel 10 to emit light having a desired amount of brightness in accordance with the digital data received by the controller 2. A programming voltage (or programming current) may be applied to the pixel 10 during a programming operation of the pixel 10 to charge a storage device, such as a storage capacitor, within the pixel 10, thereby enabling the pixel 10 to emit light having a desired amount of brightness during an emission operation after the programming operation. For example, the memory devices in the pixel 10 may be charged during a programming operation to apply a voltage to one or more of the gate and source terminals of the drive transistor during an emission operation, thereby causing the drive transistor to transmit a drive current through the light emitting device in accordance with the voltage stored in the memory device.

In general, in the pixel 10, the driving current flowing through the light emitting device, which is transmitted by the driving transistor during the emission operation of the pixel 10, is a current supplied by the first power supply line 26i and flowing out to the second power supply line 27 i. The first power supply line 26i and the second power supply line 27i are connected to the voltage power supply 14. The first power supply line 26i may provide a positive power supply voltage (e.g., a voltage commonly referred to as "Vdd" in a circuit design), while the second power supply line 27i may provide a negative power supply voltage (e.g., a voltage commonly referred to as "Vss" in a circuit design). Embodiments of the invention may be implemented as follows: one or the other of the power lines (e.g., power line 27 i) is fixed to a ground voltage or other reference voltage.

The display system 50 also includes the monitoring system 12. Referring again to the upper left pixel 10 in the display panel 20, a monitor line 28j connects the pixel 10 to the monitoring system 12. The monitoring system 12 may be integrated with the data driver 4 or may be a separate stand-alone system. In particular, the monitoring system 12 may alternatively be implemented to monitor the current and/or voltage of the data line 22j during a monitoring operation of the pixel 10, and the monitor line 28j can be omitted entirely. In addition, display system 50 may be implemented without monitoring system 12 or monitor line 28j. The monitor line 28j allows the monitoring system 12 to measure the current or voltage associated with the pixel 10 and thereby extract information indicative of the degradation of the pixel 10. For example, the monitoring system 12 may extract the current flowing in the drive transistor within the pixel 10 via the monitor line 28j and thereby determine the threshold voltage of the drive transistor or its offset based on the measured current and based on the voltage applied to the drive transistor during the measurement.

The monitor system 12 may also extract the operating voltage of the light emitting device (e.g., the voltage drop across the light emitting device while it is performing a light emitting operation). Monitor system 12 may then communicate signal 32 to controller 2 and/or memory 6 to cause display system 50 to store the extracted degradation information in memory 6. During a subsequent programming and/or emission operation of the pixel 10, the controller 2 retrieves degradation information from the memory 6 via the memory signal 36, and the controller 12 then compensates the extracted degradation information in the subsequent programming and/or emission operation of the pixel 10. For example, once the degradation information is extracted, the programming information transmitted to the pixel 10 via the signal line 22j may be appropriately adjusted during a subsequent programming operation of the pixel 10 so that the pixel 10 emits light having a desired amount of brightness and being independent of degradation of the pixel 10. In an example, an increase in the threshold voltage of the drive transistor within the pixel 10 may be compensated by appropriately increasing the programming voltage applied to the pixel 10.

Fig. 2A is a circuit diagram of an exemplary driving circuit of the pixel 110. The drive circuit shown in fig. 2A is used to correct, program and drive the pixel 110 and includes a drive transistor 112 for transmitting a drive current through an organic light emitting diode ("OLED") 114. The OLED 114 emits light according to the current flowing through the OLED 114, and may be replaced by any current-driven light emitting device. The OLED 114 has an inherent capacitance C _OLED. The pixels 110 may be used in the display panel 20 of the display system 50 described in connection with fig. 1.

The driving circuit of the pixel 110 further includes a storage capacitor 116 and a switching transistor 118. The pixel 110 is connected to a selection line SEL, a voltage power supply line Vdd, a data line Vdata, and a monitor line MON. The driving transistor 112 draws a current from the voltage power supply line Vdd according to a gate-source voltage (Vgs) between the gate terminal and the source terminal of the driving transistor 12. For example, in the saturation mode of the driving transistor 112, the current flowing through the driving transistor 112 is given by ids=β (Vgs-Vt) ², where β is a parameter depending on the device characteristics of the driving transistor 112, ids is the current from the drain terminal to the source terminal of the driving transistor 112, and Vt is the threshold voltage of the driving transistor 112.

In the pixel 110, a storage capacitor 116 is connected between the gate terminal and the source terminal of the driving transistor 112. The storage capacitor 116 has a first terminal and a second terminal, the first terminal being referred to as a gate-side terminal and the second terminal being referred to as a source-side terminal for convenience. The gate side terminal of the storage capacitor 116 is electrically connected to the gate terminal of the driving transistor 112. The source side terminal 116s of the storage capacitor 116 is electrically connected to the source terminal of the driving transistor 112. Thus, the gate-source voltage Vgs of the driving transistor 112 is also the voltage charged on the storage capacitor 116. As will be explained further below, the storage capacitor 116 is thereby able to maintain a drive voltage across the drive transistor 112 during the light emitting phase of the pixel 110.

The drain terminal of the driving transistor 112 is connected to the voltage power supply line Vdd, and the source terminal of the driving transistor 112 is (1) connected to the anode terminal of the OLED 114 and (2) connected to the monitor line MON via the read transistor 119. The cathode terminal of OLED 114 may be grounded or alternatively connected to a second voltage supply line, such as supply line Vss shown in fig. 1. Thereby, the OLED 114 is connected in series with the current path of the driving transistor 112. Once the voltage drop between the anode terminal and the cathode terminal of the OLED 114 reaches the operating voltage (V _OLED) of the OLED 114, the OLED 114 emits light according to the magnitude of the current flowing through the OLED 114. That is, when the difference between the voltage at the anode terminal and the voltage at the cathode terminal is greater than the operating voltage V _OLED, the OLED 114 is turned on and emits light. When the difference between the voltage at the anode terminal and the voltage at the cathode terminal is less than V _OLED, current does not flow through the OLED 114.

The switching transistor 118 is operated according to the selection line SEL (e.g., the switching transistor 118 is turned on when the voltage on the selection line SEL is at a high level, and the switching transistor is turned off when the voltage on the selection line SEL is at a low level). When the switching transistor 118 is turned on, it electrically connects the node a (the gate terminal of the driving transistor 112 and the gate-side terminal of the storage capacitor 116) to the data line Vdata.

The read transistor 119 is operated according to the read line RD (e.g., when the voltage on the read line RD is at a high level, the read transistor 119 is turned on, and when the voltage on the read line RD is at a low level, the read transistor 119 is turned off). When the read transistor 119 is turned on, it electrically connects the node B (the source terminal of the drive transistor 112, the source side terminal of the storage capacitor 116, and the anode of the OLED 114) to the monitor line MON.

Fig. 2B is a timing diagram of an exemplary cycle of operation of the pixel 110 shown in fig. 2A. During the first period 150, both the SEL line and the RD line are high, so the respective transistors 118 and 119 are both on. The switching transistor 118 applies a voltage Vd1 having a level sufficient to turn on the driving transistor 112 from the data line Vdata to the node a. The read transistor 119 applies a monitor line voltage Vb at a level capable of turning off the OLED 114 from the monitor line MON to the node B. As a result, the gate-source voltage Vgs (Vd 1-Vb-Vds3, where Vds3 is the voltage drop across the read transistor 119) is independent of V _OLED. At the end of the period 150, the select line SEL and the read line RD become low, turning off the transistors 118 and 119.

During the second period 154, the select line SEL is low to turn off the switching transistor 118 and the drive transistor 112 is turned on by the charge on the storage capacitor 116 at node a. The voltage on the read line RD goes high to turn on the read transistor 119 and thereby allow a first sample of the drive transistor current to be taken via the monitor line MON when the OLED 114 is off. The voltage on the monitor line MON is Vref, which may have the same level as the voltage Vb of the previous cycle.

During the third period 158, the voltage on the select line SEL is high to turn on the switching transistor 118 and the voltage on the read line RD is low to turn off the read transistor 119. Thereby, the gate of the driving transistor 112 is charged to the voltage Vd2 of the data line Vdata, and the source of the driving transistor 112 is set to V _OLED by the OLED 114. Thus, the gate-source voltage Vgs of the driving transistor 112 is a function of V _OLED (vgs=vd2-V _OLED).

During the fourth period 162, the voltage on the select line SEL is low to turn off the switching transistor 118 and the drive transistor 112 is turned on by the charge on the storage capacitor 116 at node a. The voltage on the read line RD is high to turn on the read transistor 119 and a second sample of the current of the drive transistor 112 is taken via the monitor line MON.

If the first and second samples of the driving current are not identical, the voltage Vd2 on the Vdata line is adjusted, the program voltage Vd2 is changed, and the sampling operation and the adjusting operation are repeated until the second sample of the driving current is identical to the first sample. When the two samples of the drive current are the same, then the two gate-source voltages should also be the same, that is:

V_OLED＝Vd2–Vgs

＝Vd2–(Vd1–Vb–Vds3)

＝Vd2–Vd1+Vb+Vds3。

after some operation time (t), the change in V _OLED between time 0 and time t is Δv _OLED＝V_OLED(t)–V_OLED (0) =vd2 (t) -Vd2 (0). Thus, the difference between the program voltages Vd2 (t) and Vd2 (0) can be used to extract the OLED voltage.

Fig. 2C is a schematic timing diagram of a variation of another set of exemplary operating cycles of the pixel 110 shown in fig. 2A, wherein a single read of the drive current is made and the read value is compared to a known reference value. For example, the reference value may be a driving current expected value derived by the controller for compensating for degradation of the driving transistor 112 caused by aging. The OLED voltage V _OLED can be extracted by the difference between the pixel currents measured when programming the pixel with a fixed voltage in two methods (the method affected by V _OLED and the method unaffected by V _OLED). This difference, as well as the current-voltage characteristics of the pixel, can then be used to extract V _OLED.

During the first period 200 of the exemplary timing diagram in fig. 2C, the select line SEL is high to turn on the switching transistor 118 and the read line RD is low to turn off the read transistor 119. The data line Vdata supplies the voltage Vd2 to the node a via the switching transistor 118. During the second period 201, the selection line SEL is low to turn off the switching transistor 118, and the read line RD is high to turn on the read transistor 119. The monitor line MON supplies the voltage Vref to the node B via the read transistor 119, while the driving current value is read via the read transistor 119 and the monitor line MON. The read value is compared with a known reference value of the drive current and if the read value and the reference value of the drive current are different, the periods 200 and 201 are repeated using the adjusted value of the voltage Vd2. The above process is repeated until the read value and the reference value of the drive current are substantially the same, and then the adjusted value of Vd2 can be used to determine V _OLED.

Fig. 3 is a circuit diagram of two pixels 110a and 110b, similar to the pixel shown in fig. 2A, but modified to share a common monitor line MON, while still allowing independent measurements of the drive current and OLED voltage for each pixel separately. The two pixels 110a and 110b are located in the same row but in different columns, and the two columns share the same monitor line MON. During the measurement period, only the selected pixel for measurement is programmed with the effective voltage while the other pixels are programmed to turn off the drive transistor 112. Thus, the drive transistor of one pixel will not have an effect on the current measurement in the other pixel.

Fig. 4 shows a modified drive system that employs readout circuitry 300 that is common to multiple columns of pixels, while still allowing the drive current and OLED voltage of each individual pixel 10 to be measured independently. Although only four columns are shown in fig. 4, it should be understood that a typical display contains a much larger number of columns and that they all can use the same readout circuitry. Or multiple readout circuits may be employed, where each readout circuit is still shared by multiple columns, such that the number of readout circuits is significantly smaller than the number of columns. When programming all other pixels sharing the same gate signal with voltages that turn off the respective drive transistors, the active voltage is used to program the pixel selected for measurement at any given time. Thus, the drive transistors of the other pixels will not have an effect on the current measurement being performed by the selected pixel. In addition, when the driving current in the selected pixel is used to measure the OLED voltage, the measurement of the OLED voltage is also independent of the driving transistors of the other pixels.

Fig. 5 shows one of the pixel circuits in the solid-state device including the pixel array. In the illustrated pixel circuit, the driving transistor 500 is connected in series with a load such as the photo device 501. The remaining components 502 of the pixel circuit are connected to measurement lines 503, which measurement lines 503 allow extracting characteristics of the driving components and/or the driven load for further correcting the performance of the solid state device. In this example, the optoelectronic device is an OLED, but any other device may be used.

Sharing of multiple column pairs of measurement (monitor) lines may reduce footprint. However, the sharing of monitor lines affects the OLED measurement. In most cases, using an OLED in one of the adjacent columns of a common monitor line will interfere with the measurement of the selected OLED in the other of the adjacent columns.

In one aspect of the invention, the OLED characteristics are measured indirectly by measuring the effect of the OLED voltage or current on another pixel element.

In yet another aspect of the invention, the OLEDs of adjacent pixels having a common monitor line are forced to a known state (stage). The characteristics of the selected OLED are measured in different states and extracted from the measured data.

In another aspect of the invention, the OLED samples are forced to a known state using a drive transistor. Here, the driving transistor is programmed to a fully on state. In addition, the power supply line may be changed to make the OLED state independent of the driving TFT characteristics. For example, where the pixel circuit has an n-type transistor and the OLED is at the source of the drive transistor, the drain voltage (e.g., power supply) of the drive transistor may be forced to be lower than (or close to) the full turn-on voltage of the drive transistor. In this case, the driving transistor will act as a switch for forcing the OLED voltage to be equal to the drain voltage of the driving TFT.

In yet another aspect of the invention, the status of the selected OLED is controlled by a measurement line. Thus, the measurement line may pass the characteristics of the selected OLED to the measurement circuit without being significantly affected by another OLED connected to the measurement line.

In yet another aspect of the invention, the state of all OLED samples connected to a common monitor line is forced to a known state. The characteristics are measured and then the selected OLED is set to be uncontrolled by the measurement line. The characteristics of the selected OLED samples are then measured. The difference between the two measurements is used to eliminate any possible interference from unwanted OLED sampling.

In yet another aspect of the invention, the voltage of the unwanted OLED samples is forced to be equal to the voltage of the measurement line. Thus, no current flows from the OLED line into the measurement line.

Fig. 6 shows a pair of pixel circuits sharing a common monitor line 602 of adjacent pixel circuits having drive transistors 600a, 600b for driving respective photo devices 601a, 601b, respectively. The adjacent pixel circuits also have write transistors 603a, 603b, read transistors 604a, 604b, storage capacitors 605a, 605b, and data lines 606a, 606b, respectively. The methods described above and later can be applied to different pixel circuits, and this is merely an example.

During the first phase, the voltage Vdd is set to the voltage of the monitor line and the drive transistors 600a, 600b are programmed to be in a fully conductive state. The currents in these transistors and monitor line 602 are measured when the read transistors 604a, 604b are on. This current includes leakage current to the monitor line and other non-ideal currents. This stage may be omitted if leakage current (and non-ideal current) is ignored. Furthermore, if the drive transistor is very stable, no change of the drive voltage Vdd is required.

During the second phase, the drive transistor of the selected OLED is set to an off state. Thus, the corresponding optoelectronic device is controlled by the monitor line 602. The current of monitor line 602 is again measured.

These measurements can highlight the current change of the optoelectronic device for a fixed voltage on the monitor line. The measurement may be repeated for different OLED voltages to fully obtain the characteristics of the OLED device.

The display is capable of displaying some basic information while the device is in standby. For example, in some wearable devices (e.g., smartwatches or exercise belts), the display always displays some content. The challenge in this case is the power consumption associated with the display. This power includes both static power from the backlight or light emitting device in the pixel and dynamic power associated with display refresh.

To reduce the static power, the brightness of the display may be reduced, or only a portion of the display may be turned on in the body on and the rest off (or the portion may be made at a low brightness). This also contributes to a reduction of dynamic power consumption, since only a small part of the display is programmed.

Fig. 7 shows a display with segmented power supplies Vdd1-Vdd5 for power saving. Here, each of the five horizontal segments of the display is supplied with a different voltage, so that the voltage of each segment can be controlled individually. Each segment is assigned to a different voltage or disconnected from any voltage level. For example, as shown in fig. 7, in standby mode, only the 3 rd segment may be turned on. Thus, only the content for segment 3 needs to be transferred to the display, thus reducing both dynamic and static power consumption by 80%. The display may be segmented in the horizontal and/or vertical directions and each segment receives a separate power source. In one example, VDD and VSS may be adjusted in the same direction (horizontal or vertical). In another example, VDD and VSS may be adjusted in different directions (one in the horizontal direction and the other in the vertical direction). Segmentation in other directions (e.g., diagonal directions) can also be performed. Here, the power supply lines can be connected to different voltage levels or disconnected from all voltages by switches.

In one case of power supply regulation, multiplexers are used to connect different voltage levels to different segments. In another case, the power supply is adjusted at the pixel level. In this case, the power supply is regulated in vertical or horizontal segments or a combination thereof. In one example, VDD and VSS are adjusted in the same direction (horizontal, vertical, or other directions such as diagonal). In another example, VDD and VSS are adjusted in different directions (one in the horizontal direction and the other in the vertical direction, or in other directions such as the diagonal direction).

Fig. 8 shows a schematic diagram of a circuit for regulating a power supply at a segment level. Here, the segment (i) can be connected to or disconnected from a pair of different voltages Vdd1 and Vdd2 by means of a pair of controllable switches EM1 (i) and EM2 (i). In one case of a power supply change at the pixel level, a light-emitting switch is used to connect each pixel or group of pixels to a different power supply. The light switch may be controlled by a common signal for each segment. In this case, the power supply is regulated in vertical or horizontal segments or a combination thereof. In one example, VDD and VSS are adjusted in the same direction (horizontal, vertical, diagonal, etc.). In another example, VDD and VSS are adjusted in different directions (e.g., one in a horizontal direction and the other in a vertical direction).

Fig. 9A and 9B are schematic diagrams of circuits for adjusting power supply at the pixel level. Here, the power supply lines from Vdd1 and Vdd2 or Vss1 and Vss2 may be connected to different pixels through respective controllable switches EM1 and EM 2. Or any of the pixels may be commonly disconnected from the voltage.

Fig. 10 is a schematic diagram of a pixel arrangement for adjusting power supply at a pixel level. For dynamic power consumption, the refresh rate (frame rate) of the display may be reduced. However, if the content of the display changes over time (e.g., a dial), the content needs to be generated and transmitted to the display. A portion of the host system will then be turned on and there is power consumption associated with transferring data from the host system to the display. Fig. 11 shows the system in standby mode, wherein the display displays dynamic content.

To eliminate the additional power consumption associated with data transfer between the host system and the display during standby mode, some basic functionality may be added to the display driver to produce a recursive variation of content (recursive change). For example, the driver may have a plurality of frame buffers that are pre-filled by the host system (e.g., before entering standby mode, or during power-on or power-up), depending on different conditions, one frame buffer may be used to program the display. For example, a timer may be used to switch between frame buffers (see fig. 9). The main problem in this case is that for some applications (e.g. dials), there are many different combinations that will require a very large amount of memory as a full frame buffer (full frame buffer) to store them.

Fig. 12 shows a display module with multiple frame buffers for supporting active content during standby. The drive has multiple full frame buffers and the other partial frame buffers (PARTIAL FRAME buffers) store only the changes that are applied to one full frame buffer based on certain conditions. For example, the pointer positions in the dial may be stored in a partial frame buffer as a change in the dial, while the dial itself is stored in a full frame buffer. Fig. 13 shows an exemplary block diagram of a display having a full frame buffer and a partial frame buffer, and shows a display module having a frame buffer and a content generator module for supporting active content during standby. Here, the content generator module selects the full frame buffer and the partial frame buffer based on certain conditions, and it changes the image stored in the full frame buffer based on information in the partial frame buffer. Also, multiple full and partial frame buffers may be used to create new content.

Alternatively, the drive may perform some basic calculations such as moving the object through a trajectory. In this case, for different conditions, a certain part of the image in the full frame buffer is moved based on the trajectory, or an object stored in the partial frame buffer is moved, and the full frame buffer is changed by the newly calculated object.

While particular embodiments and examples of the present invention have been illustrated and described, it is to be understood that the invention is not limited to the precise construction and compositions disclosed herein, and that various changes, variations and modifications may be readily made in light of the foregoing descriptions without departing from the spirit and scope of the invention as defined in the appended claims.

The present application claims priority from U.S. patent application Ser. No. 14/474,977, filed on day 2 of 9 in 2014, and U.S. patent application Ser. No. 14/491,763, filed on day 19 of 9 in 2014, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. An apparatus, the apparatus comprising:

a display module, the display module comprising:

A display panel having a plurality of pixel circuits arranged in an array, each of the pixel circuits including a light emitting device and a driving transistor for transmitting a driving current flowing through the light emitting device; and

A display driver including a plurality of frame buffers, the display driver for driving the display panel, for receiving standby frame data for displaying a plurality of standby frames prior to entering a standby mode of the apparatus, for storing the standby frame data in the plurality of frame buffers, and for controlling display of the plurality of standby frames on the display panel during the standby mode; and

A host system connected to the display module to transmit the standby frame data to the display driver prior to the standby mode of the device and not transmit the standby frame data to the display driver during the standby mode of the device.

2. The apparatus of claim 1, wherein the host system transmits the standby frame data to the display driver during at least one of a power-on start-up and a power-up start-up.

3. The apparatus of claim 1, wherein the display driver controls the display of each standby frame on the display panel by programming the display panel with the standby frame data.

4. The apparatus of claim 1, wherein the display driver controls the display of the plurality of standby frames by recursively varying content displayed in the display panel.

5. The apparatus of claim 1, wherein the display driver selects each standby frame for display on the display panel according to different conditions.

6. The apparatus of claim 5, wherein at least one of the different conditions is time.

7. The apparatus of claim 6, wherein the display driver controls display of the standby frame on the display panel by switching between different standby frames over time.

8. The apparatus of claim 1, wherein the display driver further comprises an event controller.

9. The apparatus of claim 2, wherein the frame buffer comprises a full frame buffer.

10. The apparatus of claim 1, wherein the frame buffer comprises a partial frame buffer.

11. The apparatus of claim 10, wherein the partial frame buffer stores changes to be applied to the standby frame data for display on the display panel based on certain conditions.

12. The apparatus of claim 11, wherein the frame buffer comprises a full frame buffer, each of the partial frame buffers storing a change in the standby frame data to be applied to the full frame buffer.

13. The apparatus of claim 12, wherein the display driver includes a content generator that selects a partial frame buffer based on certain conditions and applies it to a full frame buffer for display as a standby frame on the display panel.

14. The apparatus of claim 12, wherein the display driver comprises a content generator that selects a plurality of full and partial frame buffers to create content for display as standby frames on the display panel.