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CN110334470B - Multiband negative group delay circuit based on coupling line - Google Patents

Multiband negative group delay circuit based on coupling line Download PDF

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CN110334470B
CN110334470B CN201910643553.1A CN201910643553A CN110334470B CN 110334470 B CN110334470 B CN 110334470B CN 201910643553 A CN201910643553 A CN 201910643553A CN 110334470 B CN110334470 B CN 110334470B
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万发雨
李宁东
顾韬琛
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Nanjing University of Information Science and Technology
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Abstract

本发明公开了一种基于耦合线的多频段负群时延电路,该电路为对称结构,包括微带线ILi,i={1、2、3}和三条微带线组成的耦合微带线,所述微带线IL1、微带线IL2和微带线IL3都为两条;耦合微带线的上端微带连接线分别对称连接一个微带线IL1,该两个微带线IL1分别连接端口三和端口四,耦合微带线的中间微带连接线分别对称连接一个端口微带线IL3,该两个端口微带线IL3分别连接端口一和端口二,耦合微带线的下端微带连接线分别对称连接一个微带线IL2,该两个微带线IL2分别连接端口五和端口六;耦合微带线的长度L1为10.7mm,耦合微带线之间的耦合间距S1和S2分别为1.7mm和1.8mm,微带线IL1的长度L2为10mmm和1.9mm;所述端口微带线IL3的长度L4为9mm;微带线IL2的长度为L3为7.4mm,微带线IL1、IL2、IL3和耦合微带线的宽度w都为1.9mm。

Figure 201910643553

The invention discloses a multi-band negative group delay circuit based on coupled lines. The circuit has a symmetrical structure and includes a microstrip line IL i , i={1, 2, 3} and a coupled microstrip composed of three microstrip lines. line, the microstrip line IL 1 , microstrip line IL 2 and microstrip line IL 3 are all two; the upper end microstrip connection line of the coupled microstrip line is respectively symmetrically connected to a microstrip line IL 1 , the two microstrip lines The strip line IL 1 is respectively connected to port three and port four, and the middle microstrip connection line of the coupled microstrip line is respectively symmetrically connected to one port microstrip line IL 3 , and the two port microstrip line IL 3 are respectively connected to port one and port two, The microstrip connection line at the lower end of the coupled microstrip line is respectively symmetrically connected to a microstrip line IL 2 , and the two microstrip lines IL 2 are respectively connected to port five and port six; the length L 1 of the coupled microstrip line is 10.7mm, and the coupled microstrip line The coupling spacing S 1 and S 2 between the strip lines are 1.7mm and 1.8mm respectively, the length L 2 of the microstrip line IL 1 is 10mm and 1.9mm; the length L 4 of the port microstrip line IL 3 is 9mm; The length L3 of the microstrip line IL 2 is 7.4 mm, and the width w of the microstrip lines IL 1 , IL 2 , IL 3 and the coupling microstrip line is 1.9 mm.

Figure 201910643553

Description

一种基于耦合线的多频段负群时延电路A Multiband Negative Group Delay Circuit Based on Coupled Lines

技术领域technical field

本发明属于微波工程的技术领域,具体涉及一种基于耦合线的多频段负群时延电路。The invention belongs to the technical field of microwave engineering, in particular to a multi-band negative group delay circuit based on coupled lines.

背景技术Background technique

20世纪早期,美国科学家A.Sommerfeld和L.Brillouin提出了群时延为负的可能性后,在相当长的一段时间内“负群时延”颇受争议,直到贝尔实验室的Chu和Wong第一次在激光脉冲穿过GaP:N样品的实验中观察到了负群速。此后,在其他光学、量子试验中,群速为负或大于光速也被多次被证实。进入二十世纪后,随着左手材料等新型材料的发展和对通信系统性能的要求越来越高,更多的研究人员开始对群时延展开研究。尤其是近些年来,负群时延电路因其特殊的性能和在前馈放大器、天线阵列等领域的广泛应用,吸引了世界各国研究者的注意,成为又一个研究热点。In the early 20th century, after American scientists A.Sommerfeld and L.Brillouin proposed the possibility of negative group delay, "negative group delay" was controversial for a long time, until Chu and Wong of Bell Laboratories Negative group velocity is observed for the first time in experiments where laser pulses pass through a GaP:N sample. Since then, in other optical and quantum experiments, it has been confirmed many times that the group velocity is negative or greater than the speed of light. After entering the 20th century, with the development of new materials such as left-handed materials and the higher and higher requirements for the performance of communication systems, more researchers began to study group delay. Especially in recent years, the negative group delay circuit has attracted the attention of researchers all over the world because of its special performance and wide application in the fields of feedforward amplifiers and antenna arrays, and has become another research hotspot.

近年来,负群时延电路从最简单的RLC谐振单元开始,但基于RLC的基本负群时延电路的损耗比较大,所以常用RLC谐振网络和放大器组合的方式可将电路的损耗降低。此外,除了上述利用RLC和放大器的组成的有源负群时延电路外,近来,利用微带线相关的结构形成的无源负群时延电路由于其损耗低,可往高频发展的特征,相关的一些无源结构被提出。诸如此类的一些工作大多数由外国研究者所探索,在国内负群时延电路却很少被探索。In recent years, the negative group delay circuit starts from the simplest RLC resonant unit, but the loss of the basic negative group delay circuit based on RLC is relatively large, so the combination of RLC resonant network and amplifier is often used to reduce the loss of the circuit. In addition, in addition to the above-mentioned active negative group delay circuit composed of RLC and amplifier, recently, the passive negative group delay circuit formed by using the structure related to the microstrip line can be developed to high frequency due to its low loss. , some related passive structures are proposed. Some works like this are mostly explored by foreign researchers, but negative group delay circuits are rarely explored in China.

发明内容Contents of the invention

本发明所要解决的技术问题是针对上述现有技术的不足,基于微波工程理论,为了降低负群时延电路的损耗和反射,提高群时延,提供一种基于耦合线的多频段负群时延电路。The technical problem to be solved by the present invention is aimed at the deficiencies of the above-mentioned prior art. Based on microwave engineering theory, in order to reduce the loss and reflection of the negative group delay circuit and improve the group delay, a multi-band negative group time delay based on coupled lines is provided. delay circuit.

为实现上述技术目的,本发明采取的技术方案为:For realizing above-mentioned technical purpose, the technical scheme that the present invention takes is:

一种基于耦合线的多频段负群时延电路,所述电路为对称结构,包括微带线ILi,i={1、2、3}和三条微带连接线组成的耦合微带线,所述微带线IL1、微带线IL2和微带线IL3均为两条;所述耦合微带线的上端微带连接线分别对称连接一个微带线IL1,该两个微带线IL1分别连接端口三和端口四,所述耦合微带线的中间微带连接线分别对称连接一个端口微带线IL3,该两个端口微带线IL3分别连接端口一和端口二,所述耦合微带线的下端微带连接线分别对称连接一个微带线IL2,该两个微带线IL2分别连接端口五和端口六;A multi-band negative group delay circuit based on coupled lines, the circuit is a symmetrical structure, including a microstrip line IL i , i={1, 2, 3} and a coupled microstrip line composed of three microstrip connecting lines, The microstrip line IL 1 , the microstrip line IL 2 and the microstrip line IL 3 are two; the microstrip connecting line at the upper end of the coupled microstrip line is respectively symmetrically connected to a microstrip line IL 1 , and the two microstrip lines Strip line IL 1 is respectively connected to port three and port four, and the middle microstrip connection line of the coupled microstrip line is symmetrically connected to one port microstrip line IL 3 respectively, and the two port microstrip lines IL 3 are respectively connected to port one and port 2. The microstrip connection lines at the lower end of the coupled microstrip line are respectively symmetrically connected to a microstrip line IL 2 , and the two microstrip lines IL 2 are respectively connected to port five and port six;

所述耦合微带线的长度L1为10.7mm,所述耦合微带线之间的耦合间距S1和S2分别为1.7mm和1.8mm,微带线IL1的长度L2为10mmm和1.9mm;所述端口微带线IL3的长度L4为9mm;所述微带线IL2的长度为L3为7.4mm,所述微带线IL1、IL2、IL3和耦合微带线的宽度w都为1.9mm。The length L 1 of the coupled microstrip line is 10.7mm, the coupling spacing S 1 and S 2 between the coupled microstrip lines are 1.7mm and 1.8mm respectively, and the length L 2 of the microstrip line IL 1 is 10mm and 1.9mm; the length L 4 of the port microstrip line IL 3 is 9mm; the length of the microstrip line IL 2 is 7.4mm, and the microstrip line IL 1 , IL 2 , IL 3 and the coupling microstrip line The width w of the strip lines is all 1.9 mm.

为优化上述技术方案,采取的具体措施还包括:In order to optimize the above technical solutions, the specific measures taken also include:

上述的电路尺寸为28.7mm×30.6mm。The above-mentioned circuit size is 28.7mm×30.6mm.

上述的电路采用FR4板材,所述板材厚度为1.6mm,介电常数是4.4,正切损耗为0.02,铜厚为0.035mm。The above-mentioned circuit adopts FR4 plate, the thickness of which is 1.6mm, the dielectric constant is 4.4, the tangent loss is 0.02, and the copper thickness is 0.035mm.

上述的电路工作于S频段,在电路的端口一和端口二之间能实现双频,该端口一和端口二分别为信号的输入端口和输出端口,在中心频率2.48GHz、2.9GHz时,电路的群时延分别为-1.6ns,-1.2ns,电路的插入损耗S21分别为-3.6dB、-3.3dB,电路的反射系数S11分别为-11dB、-12dB。The above-mentioned circuit works in the S-band, and dual-frequency can be realized between port 1 and port 2 of the circuit. The port 1 and port 2 are the input port and output port of the signal respectively. When the center frequency is 2.48GHz and 2.9GHz, the circuit The group delays are -1.6ns, -1.2ns respectively, the insertion loss S 21 of the circuit is -3.6dB, -3.3dB respectively, and the reflection coefficient S 11 of the circuit is -11dB, -12dB respectively.

上述的电路工作于S频段,在电路的端口三和端口四之间能实现双频,该端口三和端口四分别为信号的输入端口和输出端口,在中心频率2.6GHz、2.95GHz时,电路的群时延分别为-1.3ns,-0.2ns,电路的插入损耗S43分别为-3.3dB、-1.6dB,电路的反射系数S33分别为-12dB、-15dB。The above-mentioned circuit works in the S-band, and dual-frequency can be realized between port 3 and port 4 of the circuit. The port 3 and port 4 are the input port and output port of the signal respectively. When the center frequency is 2.6GHz and 2.95GHz, the circuit The group delays are -1.3ns, -0.2ns respectively, the insertion loss S 43 of the circuit is -3.3dB, -1.6dB respectively, and the reflection coefficient S 33 of the circuit is -12dB, -15dB respectively.

上述的电路工作于S频段,在电路的端口五和端口六之间能实现双频,该端口五和端口六分别为信号的输入端口和输出端口,在中心频率2.43GHz、2.82GHz时,电路的群时延分别为-0.5ns,-1.7ns,电路的插入损耗S65分别为-3.3dB、-1.6dB,电路的反射系数S55分别为-20dB、-12dB。The above-mentioned circuit works in the S-band, and dual-frequency can be realized between port 5 and port 6 of the circuit. The port 5 and port 6 are the input port and output port of the signal respectively. When the center frequency is 2.43GHz and 2.82GHz, the circuit The group delays are -0.5ns, -1.7ns respectively, the insertion loss S 65 of the circuit is -3.3dB, -1.6dB respectively, and the reflection coefficient S 55 of the circuit is -20dB, -12dB respectively.

本发明的有益效果:Beneficial effects of the present invention:

为了实现电路的小型化,降低电路的损耗和反射,提高群时延带宽和时延,设计了一种基于耦合线的多频段负群时延电路,并对设计的电路进行优化设计,最终可得到多频段的负群时延电路。最终可得:在电路的端口一和端口二之间能实现双频,在中心频率2.48GHz、2.9GHz时,电路的群时延分别为-1.6ns,-1.2ns,电路的插入损耗S21分别为-3.6dB、-3.3dB,电路的反射系数S11分别为-11dB、-12dB。In order to realize the miniaturization of the circuit, reduce the loss and reflection of the circuit, and improve the bandwidth and delay of the group delay, a multi-band negative group delay circuit based on coupled lines is designed, and the designed circuit is optimized. A multi-band negative group delay circuit is obtained. Finally, it can be obtained that dual frequency can be realized between port 1 and port 2 of the circuit. When the center frequencies are 2.48GHz and 2.9GHz, the group delay of the circuit is -1.6ns and -1.2ns respectively, and the insertion loss of the circuit is S 21 They are -3.6dB and -3.3dB respectively, and the reflection coefficient S 11 of the circuit is -11dB and -12dB respectively.

在电路的端口三和端口四之间能实现双频,在中心频率2.6GHz、2.95GHz时,电路的群时延分别为-1.3ns,-0.2ns,电路的插入损耗S43分别为-3.3dB、-1.6dB,电路的反射系数S33分别为-12dB、-15dB。Dual frequency can be realized between port 3 and port 4 of the circuit. When the center frequency is 2.6GHz and 2.95GHz, the group delay of the circuit is -1.3ns, -0.2ns respectively, and the insertion loss S 43 of the circuit is -3.3 dB, -1.6dB, the reflection coefficient S 33 of the circuit is -12dB, -15dB respectively.

在电路的端口五和六之间能实现双频,在中心频率2.43GHz、2.82GHz时,电路的群时延分别为-0.5ns,-1.7ns,电路的插入损耗S65分别为-3.3dB、-1.6dB,电路的反射系数S55分别为-20dB、-12dB。这种多频段的负群时延电路可以用于多种频段的微波电路中,以解决电路信号的延时问题。Dual frequency can be realized between ports 5 and 6 of the circuit. When the center frequency is 2.43GHz and 2.82GHz, the group delay of the circuit is -0.5ns, -1.7ns respectively, and the insertion loss S 65 of the circuit is -3.3dB , -1.6dB, the reflection coefficient S 55 of the circuit is -20dB, -12dB respectively. This multi-band negative group delay circuit can be used in microwave circuits of various frequency bands to solve the delay problem of circuit signals.

附图说明Description of drawings

图1本发明的电路原理图;Fig. 1 schematic circuit diagram of the present invention;

图2为本发明电路结构示意图;Fig. 2 is a schematic diagram of the circuit structure of the present invention;

图3为本发明电路ADS模型;Fig. 3 is the circuit ADS model of the present invention;

图4为本发明电路的群时延delay(2,1)仿真结果示意图;Fig. 4 is the group time delay delay (2,1) simulation result schematic diagram of circuit of the present invention;

图5为本发明电路的S(2,1)仿真结果示意图;Fig. 5 is the S (2,1) simulation result schematic diagram of circuit of the present invention;

图6为本发明电路的S(1,1)仿真结果示意图;Fig. 6 is the S (1,1) simulation result schematic diagram of circuit of the present invention;

图7为本发明电路的群时延delay(4,3)仿真结果示意图;Fig. 7 is the group time delay delay (4,3) simulation result schematic diagram of circuit of the present invention;

图8为本发明电路的损耗S(4,3)仿真结果示意图;Fig. 8 is the schematic diagram of the simulation result of the loss S (4,3) of the circuit of the present invention;

图9为本发明电路的反射S(3,3)仿真结果示意图;Fig. 9 is the schematic diagram of the reflection S (3,3) simulation result of the circuit of the present invention;

图10为本发明电路的群时延delay(6,5)仿真结果示意图;Fig. 10 is a schematic diagram of the group delay delay (6,5) simulation result of the circuit of the present invention;

图11为本发明电路的损耗S(6,5)仿真结果示意图;Fig. 11 is the schematic diagram of the simulation result of the loss S(6,5) of the circuit of the present invention;

图12为本发明电路的反射S(5,5)仿真结果示意图。Fig. 12 is a schematic diagram of the reflection S(5,5) simulation result of the circuit of the present invention.

具体实施方式Detailed ways

以下结合附图对本发明的实施例作进一步详细描述。Embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings.

如图1所示,本发明为一种基于耦合线的多频段负群时延电路,所述电路为对称结构,包括微带线ILi,i={1、2、3}和三条微带连接线组成的耦合微带线,所述微带线IL1、微带线IL2和微带线IL3都为两条;所述耦合微带线的上端微带连接线分别对称连接一个微带线IL1,该两个微带线IL1分别连接端口三和端口四,所述耦合微带线的中间微带连接线分别对称连接一个端口微带线IL3,该两个端口微带线IL3分别连接端口一和端口二,所述耦合微带线的下端微带连接线分别对称连接一个微带线IL2,该两个微带线IL2分别连接端口五和端口六;As shown in Figure 1, the present invention is a multi-band negative group delay circuit based on coupled lines, the circuit is a symmetrical structure, including microstrip line IL i , i={1, 2, 3} and three microstrips A coupled microstrip line composed of connection lines, the microstrip line IL 1 , microstrip line IL 2 and microstrip line IL 3 are all two; the upper end microstrip connection line of the coupled microstrip line is respectively symmetrically connected to a microstrip line Strip line IL 1 , the two microstrip lines IL 1 are respectively connected to port three and port four, and the middle microstrip connection line of the coupled microstrip line is respectively symmetrically connected to one port microstrip line IL 3 , the two port microstrip lines Line IL 3 is respectively connected to port 1 and port 2, and the microstrip connection line at the lower end of the coupled microstrip line is symmetrically connected to a microstrip line IL 2 respectively, and the two microstrip lines IL 2 are respectively connected to port 5 and port 6;

所述耦合微带线的长度L1为10.7mm,所述耦合微带线之间的耦合间距S1和S2分别为1.7mm和1.8mm,微带线IL1的长度L2为10mmm和1.9mm;所述端口微带线IL3的长度L4为9mm;所述微带线IL2的长度为L3为7.4mm,所述微带线IL1、IL2、IL3和耦合微带线的宽度w都为1.9mm。The length L 1 of the coupled microstrip line is 10.7mm, the coupling spacing S 1 and S 2 between the coupled microstrip lines are 1.7mm and 1.8mm respectively, and the length L 2 of the microstrip line IL 1 is 10mm and 1.9mm; the length L 4 of the port microstrip line IL 3 is 9mm; the length of the microstrip line IL 2 is 7.4mm, and the microstrip line IL 1 , IL 2 , IL 3 and the coupling microstrip line The width w of the strip lines is all 1.9 mm.

如图2和图3所示,本发明电路结构是对称结构。As shown in Fig. 2 and Fig. 3, the circuit structure of the present invention is a symmetrical structure.

ADS对该电路尺寸的优化结果如下表所示:The optimization results of ADS for this circuit size are shown in the table below:

表1.电路基本参数尺寸Table 1. Basic parameter dimensions of the circuit

ww 1.9mm1.9mm L1 L 1 10.7mm10.7mm L2 L 2 10mm10mm L3 L 3 7.4mm7.4mm L4 L 4 9mm9mm S1 S 1 1.7mm1.7mm S2 S 2 1.8mm1.8mm 尺寸size 28.7mm×30.6mm28.7mm×30.6mm

图4、图5和图6分别为本专利电路的端口一和端口二之间的群时延delay21、插入损耗S21、反射系数S11的仿真结果示意图。由示意图可知:该电路工作于S频段,在电路的端口一和端口二之间能实现双频,在中心频率2.48GHz、2.9GHz时,电路的群时延分别为-1.6ns,-1.2ns,电路的插入损耗S21分别为-3.6dB、-3.3dB,电路的反射系数S11分别为-11dB、-12dB。Fig. 4, Fig. 5 and Fig. 6 are schematic diagrams of simulation results of group delay delay 21 , insertion loss S 21 , and reflection coefficient S 11 between port 1 and port 2 of the patented circuit respectively. It can be seen from the schematic diagram that the circuit works in the S-band, and dual-band can be realized between port 1 and port 2 of the circuit. When the center frequency is 2.48GHz and 2.9GHz, the group delay of the circuit is -1.6ns and -1.2ns respectively. , the insertion loss S 21 of the circuit is -3.6dB, -3.3dB respectively, and the reflection coefficient S 11 of the circuit is -11dB, -12dB respectively.

图7、图8、图9分别为本专利电路的端口三和端口四之间的群时延delay43、插入损耗S43、反射系数S33的仿真结果示意图。由示意图可知:该电路工作于S频段,在电路的端口三和端口四之间能实现双频,在中心频率2.6GHz、2.95GHz时,电路的群时延分别为-1.3ns,-0.2ns,电路的插入损耗S21分别为-3.3dB、-1.6dB,电路的反射系数S11分别为-12dB、-15dB。Fig. 7, Fig. 8, and Fig. 9 are schematic diagrams of simulation results of group delay delay 43 , insertion loss S 43 , and reflection coefficient S 33 between port three and port four of the patented circuit, respectively. It can be seen from the schematic diagram that the circuit works in the S-band, and dual-band can be realized between port 3 and port 4 of the circuit. When the center frequency is 2.6GHz and 2.95GHz, the group delay of the circuit is -1.3ns, -0.2ns respectively , the insertion loss S 21 of the circuit is -3.3dB, -1.6dB respectively, and the reflection coefficient S 11 of the circuit is -12dB, -15dB respectively.

图10、图11、图12分别为本专利电路的端口五和端口六之间的群时延delay65、插入损耗S65、反射系数S55的仿真结果示意图。由示意图可知:该电路工作于S频段,在电路的端口五和端口六之间能实现双频,在中心频率2.43GHz、2.82GHz时,电路的群时延delay65分别为-0.5ns,-1.7ns,电路的插入损耗S65分别为-3.3dB、-1.6dB,电路的反射系数S55分别为-20dB、-12dB。Fig. 10, Fig. 11, and Fig. 12 are schematic diagrams of simulation results of group delay delay 65 , insertion loss S 65 , and reflection coefficient S 55 between ports five and six of the patented circuit, respectively. It can be seen from the schematic diagram that the circuit works in the S-band, and dual-band can be realized between port 5 and port 6 of the circuit. When the center frequency is 2.43GHz and 2.82GHz, the group delay delay 65 of the circuit is -0.5ns, - 1.7ns, the insertion loss S 65 of the circuit is -3.3dB, -1.6dB respectively, and the reflection coefficient S 55 of the circuit is -20dB, -12dB respectively.

本实施例中,电路ADS模型,采用FR4板材,该板材的厚度是1.6mm,尺寸是28.7mm×30.6mm,介电常数是4.4,正切损耗角为0.02,且铜厚为0.035mm。In this embodiment, the ADS model of the circuit adopts FR4 plate, the thickness of which is 1.6mm, the size is 28.7mm×30.6mm, the dielectric constant is 4.4, the tangent loss angle is 0.02, and the copper thickness is 0.035mm.

利用仿真软件ADS对提出的电路进行仿真设计优化,可得到如表1所示的电路基本参数尺寸。Using the simulation software ADS to simulate the design optimization of the proposed circuit, the basic parameter size of the circuit shown in Table 1 can be obtained.

以上仅是本发明的优选实施方式,本发明的保护范围并不仅局限于上述实施例,凡属于本发明思路下的技术方案均属于本发明的保护范围。应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理前提下的若干改进和润饰,应视为本发明的保护范围。The above are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims (3)

1.一种基于耦合线的多频段负群时延电路,其特征在于:所述电路为对称结构,包括微带线ILi,i={1、2、3}和三条微带连接线组成的耦合微带线,所述微带线IL1、微带线IL2和微带线IL3均为两条;所述耦合微带线的上端微带连接线分别对称连接一个微带线IL1,该两个微带线IL1分别连接端口三和端口四,所述耦合微带线的中间微带连接线分别对称连接一个端口微带线IL3,该两个端口微带线IL3分别连接端口一和端口二,所述耦合微带线的下端微带连接线分别对称连接一个微带线IL2,该两个微带线IL2分别连接端口五和端口六;1. A multi-band negative group delay circuit based on coupled lines, characterized in that: said circuit is a symmetrical structure, comprising microstrip line IL i , i={1, 2, 3} and three microstrip connecting lines are formed The coupled microstrip line, the microstrip line IL 1 , the microstrip line IL 2 and the microstrip line IL 3 are two; the upper end microstrip connection line of the coupled microstrip line is respectively symmetrically connected to a microstrip line IL 1 , the two microstrip lines IL 1 are respectively connected to port three and port four, and the middle microstrip connection line of the coupled microstrip line is symmetrically connected to one port microstrip line IL 3 respectively, and the two port microstrip lines IL 3 Port 1 and port 2 are respectively connected, and the microstrip connection line at the lower end of the coupled microstrip line is respectively symmetrically connected to a microstrip line IL 2 , and the two microstrip lines IL 2 are respectively connected to port 5 and port 6; 所述耦合微带线的长度L1为10.7mm,所述耦合微带线之间的耦合间距S1和S2分别为1.7mm和1.8mm,微带线IL1的长度L2为10mmm和1.9mm;所述端口微带线IL3的长度L4为9mm;所述微带线IL2的长度为L3为7.4mm,所述微带线IL1、IL2、IL3和耦合微带线的宽度w均为1.9mm;所述电路工作于S频段,在电路的端口一和端口二之间能实现双频,该端口一和端口二分别为信号的输入端口和输出端口,在中心频率2.48GHz、2.9GHz时,电路的群时延分别为-1.6ns,-1.2ns,电路的插入损耗S21分别为-3.6dB、-3.3dB,电路的反射系数S11分别为-11dB、-12dB;所述电路工作于S频段,在电路的端口三和端口四之间能实现双频,该端口三和端口四分别为信号的输入端口和输出端口,在中心频率2.6GHz、2.95GHz时,电路的群时延分别为-1.3ns,-0.2ns,电路的插入损耗S43分别为-3.3dB、-1.6dB,电路的反射系数S33分别为-12dB、-15dB;所述电路工作于S频段,在电路的端口五和端口六之间能实现双频,该端口五和端口六分别为信号的输入端口和输出端口,在中心频率2.43GHz、2.82GHz时,电路的群时延分别为-0.5ns,-1.7ns,电路的插入损耗S65分别为-3.3dB、-1.6dB,电路的反射系数S55分别为-20dB、-12dB。The length L 1 of the coupled microstrip line is 10.7mm, the coupling spacing S 1 and S 2 between the coupled microstrip lines are 1.7mm and 1.8mm respectively, and the length L 2 of the microstrip line IL 1 is 10mm and 1.9mm; the length L 4 of the port microstrip line IL 3 is 9mm; the length of the microstrip line IL 2 is 7.4mm, and the microstrip line IL 1 , IL 2 , IL 3 and the coupling microstrip line The width w of the strip line is 1.9mm; the circuit works in the S frequency band, and dual frequency can be realized between the port one and the port two of the circuit, and the port one and port two are respectively the input port and the output port of the signal. When the center frequency is 2.48GHz and 2.9GHz, the group delay of the circuit is -1.6ns, -1.2ns respectively, the insertion loss S 21 of the circuit is -3.6dB, -3.3dB respectively, and the reflection coefficient S 11 of the circuit is -11dB respectively , -12dB; the circuit works in the S frequency band, and dual frequency can be realized between the port three and the port four of the circuit. During GHz, the group time delay of circuit is respectively-1.3ns,-0.2ns, and the insertion loss S43 of circuit is respectively-3.3dB,-1.6dB, and the reflection coefficient S33 of circuit is respectively-12dB,-15dB; The circuit works in the S-band, and dual-frequency can be realized between port five and port six of the circuit. The port five and port six are the input port and output port of the signal respectively. When the center frequency is 2.43GHz and 2.82GHz, the group of the circuit The time delays are -0.5ns, -1.7ns respectively, the insertion loss S 65 of the circuit is -3.3dB, -1.6dB respectively, and the reflection coefficient S 55 of the circuit is -20dB, -12dB respectively. 2.根据权利要求1所述的一种基于耦合线的多频段负群时延电路,其特征在于:所述电路尺寸为28.7mm×30.6mm。2. A multi-band negative group delay circuit based on coupled lines according to claim 1, characterized in that: said circuit size is 28.7mm×30.6mm. 3.根据权利要求1所述的一种基于耦合线的多频段负群时延电路,其特征在于:所述电路采用FR4板材,所述板材厚度为1.6mm,介电常数是4.4,正切损耗为0.02,铜厚为0.035mm。3. a kind of multi-band negative group delay circuit based on coupled lines according to claim 1, is characterized in that: described circuit adopts FR4 plate material, and described plate material thickness is 1.6mm, and dielectric constant is 4.4, and tangent loss is 0.02, and the copper thickness is 0.035mm.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108566175A (en) * 2018-03-26 2018-09-21 西南电子技术研究所(中国电子科技集团公司第十研究所) Adjustable negative group delay circuitry
CN109918864A (en) * 2019-05-05 2019-06-21 南京信息工程大学 Negative group delay circuit and design method based on sector stub and coupled microstrip line

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108566175A (en) * 2018-03-26 2018-09-21 西南电子技术研究所(中国电子科技集团公司第十研究所) Adjustable negative group delay circuitry
CN109918864A (en) * 2019-05-05 2019-06-21 南京信息工程大学 Negative group delay circuit and design method based on sector stub and coupled microstrip line

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
一种新型的可配置传输型微带负群时延电路;刘刚等;《东南大学学报》;20170930;第47卷(第5期);第856-860页 *

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