CN110326099A - Conductor integrated circuit device - Google Patents

Abstract

Cell (1) is a logic cell and includes three-dimensional transistor devices (P11, P12, N11, N12). Cell (2) is a delay cell and includes three-dimensional transistor devices (P21-P24, N21-N24). The length (D2) of the local wiring (31) protruding from the three-dimensional diffusion layer parts (21a, 21b) in the direction away from the power supply line (VDD) in the cell (2) is greater than that of the local wiring (16) in the cell (1) from the three-dimensional diffusion layer The length (D1) of the portion (11) protruding away from the power supply line (VDD). In a semiconductor integrated circuit device using a three-dimensional transistor device, a delay cell having a large delay value per unit area is realized.

Description

Semiconductor integrated circuit device

technical field

The present disclosure relates to a semiconductor integrated circuit device using three-dimensional transistor devices such as fin-type FET (Field Effect Transistor: Field Effect Transistor) and nanowire FET.

Background technique

The standard cell approach is a known method of forming semiconductor integrated circuits on a semiconductor substrate. The standard cell method refers to the method in which basic units with specific logic functions (such as inverters, latches, flip-flops, full adders, etc.) are prepared as standard units in advance, and then multiple standard units are prepared. Cells are arranged on a semiconductor substrate, and these standard cells are connected by wiring, so that an LSI chip is designed.

In recent years, in the field of semiconductor devices, FETs having a fin structure (hereinafter referred to as fin FETs) have been proposed. FIG. 9 is a schematic diagram showing a schematic configuration of a fin FET. Unlike a two-dimensional FET, the source and drain of a fin FET have a three-dimensional structure called a fin. And, a gate electrode is arranged so as to surround the fin. According to this fin-type structure, the channel region is formed by the three surfaces of the fin, so that the controllability of the channel is greatly improved compared with the prior art. Therefore, effects such as reducing leakage power consumption, increasing on-current, and further reducing operating voltage can be obtained, thereby improving the performance of the semiconductor integrated circuit. It should be noted that the fin FET is a so-called three-dimensional transistor device having a three-dimensional diffusion layer portion. In addition to this, three-dimensional transistor devices also have structures known as nanowire FETs, for example.

On the other hand, the delay unit is used for timing adjustment of the circuit operation and the like, and is realized by, for example, a buffer or the like. Patent Document 1 shows an example of such a delay adjustment unit.

Patent Document 1: Japanese Laid-Open Patent Publication No. 2003-60487

SUMMARY OF THE INVENTION

-Technical problem to be solved by invention-

When packaging three-dimensional transistor devices, local interconnects are generally used. The local wiring refers to a wiring that is in direct contact with the diffusion layer and gate of the transistor without going through a contact.

In a semiconductor integrated circuit device using the local wiring, how to realize a delay cell having a large delay value per unit area is a problem.

The present disclosure realizes a delay cell with a larger delay value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device such as a fin FET and a nanowire FET.

-Technical solutions to solve technical problems-

In a first aspect of the present disclosure, a semiconductor integrated circuit device includes a first standard cell that is a logic cell and has a three-dimensional transistor device and a second standard cell that is a delay cell, and has a three-dimensional transistor device. The first standard unit includes: a first three-dimensional diffusion layer portion extending along a first direction, or a plurality of first three-dimensional diffusion layer portions extending along the first direction, wherein a plurality of the first three-dimensional diffusion layers The parts are arranged along a second direction perpendicular to the first direction; and a first local wiring extends along the second direction and connects the first three-dimensional diffusion layer part and the power line, the power line along the The first direction extends and a predetermined first power supply voltage is supplied. The second standard unit includes: one second three-dimensional diffusion layer part extending along the first direction, or a plurality of second three-dimensional diffusion layer parts extending along the first direction, wherein a plurality of the second three-dimensional diffusion layer parts The three-dimensional diffusion layer parts are arranged along the second direction; the second local wirings extend along the second direction and connect the second three-dimensional diffusion layer parts and the power supply lines; and the gate wirings extend along the second direction. The second direction extends to intersect the second three-dimensional diffusion layer portion in plan view, and is formed to surround the second three-dimensional diffusion layer portion, and a predetermined second power supply voltage is applied to the gate wiring. The length of the protruding length of the second local wiring from the second three-dimensional diffusion layer portion in the direction away from the power supply line in the second standard cell is greater than that of the first local wiring in the first standard cell. The length of the first three-dimensional diffusion layer portion protruding in a direction away from the power supply line.

According to the above aspect, the length of the local wiring in the second standard cell, which is the delay cell, protrudes from the three-dimensional diffusion layer part in the direction away from the power supply line is greater than the length of the local wiring in the logic cell, which is the first standard cell, from the three-dimensional diffusion layer part in the direction away from the power supply line. The length of the direction protrusion. That is, in the delay cell, the local wiring connected to the three-dimensional diffusion layer portion of the three-dimensional transistor device extends longer from the three-dimensional diffusion layer portion. In this way, the parasitic capacitance between the local wiring and the gate wiring becomes larger, so that a delay cell with a large delay value per unit area can be realized.

-Effect of invention-

According to the present disclosure, in a semiconductor integrated circuit device using a three-dimensional transistor device, a delay cell having a large delay value per unit area can be realized. Therefore, the performance of the semiconductor integrated circuit device can be improved.

Description of drawings

FIG. 1 is a plan view showing an example of a layout structure of standard cells included in the semiconductor integrated circuit device according to the first embodiment.

FIGS. 2( a ) and 2 ( b ) are cross-sectional views of the structure of FIG. 1 .

FIG. 3( a ) and FIG. 3( b ) are circuit diagrams of the standard cell of FIG. 1 .

4(a) and 4(b) are other circuit examples of the delay unit.

FIG. 5 is a plan view showing the shape of the metal wiring in the standard cell 2 of FIG. 1 .

FIG. 6 is a plan view showing the comparative example of FIG. 5 .

FIG. 7 is a plan view showing a modification of the standard cell 2 of FIG. 1 .

FIG. 8 is a plan view showing a modification of the standard cell 2 of FIG. 1 .

FIG. 9 is a schematic diagram showing a schematic configuration of a fin FET.

Figure 10 is a schematic diagram showing the schematic configuration of a nanowire FET.

FIG. 11 is a schematic diagram showing the schematic configuration of a nanowire FET.

Detailed ways

Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, the semiconductor integrated circuit device includes a plurality of standard cells, and at least a part of the plurality of standard cells uses a fin FET (Field Effect Transistor). In addition, a fin FET is an example of a three-dimensional transistor device, and the fin which comprises a fin FET is an example of a three-dimensional diffusion layer part.

(first embodiment)

FIG. 1 is a plan view showing an example of a layout structure of standard cells included in the semiconductor integrated circuit device according to the first embodiment. In FIG. 1 , the horizontal direction in the drawing is defined as the X direction (corresponding to the first direction), and the vertical direction in the drawing is defined as the Y direction (corresponding to the second direction). The same is true for the top view of the layout after that. In Figure 1, the standard cells 1, 2 are arranged in the same cell column extending in the X direction. CF is the cell frame. Fig. 2(a) is a cross-sectional view taken along line A1-A1 in Fig. 1 , and Fig. 2(b) is a cross-sectional view taken along line A2-A2 in Fig. 1 .

3(a) and 3(b) are circuit diagrams showing the circuit structures of standard cells 1 and 2, respectively. As shown in FIG. 3( a ), the standard cell 1 constitutes a two-input NAND circuit. The standard cell 1 is an example of a logic cell that contributes to realizing the logic function of the circuit. As shown in FIG. 3(b), the standard cell 2 constitutes a delay cell. The delay cell has four inverters connected in series.

In FIG. 1, power supply lines VDD, VSS extending in the X direction are formed in the metal wiring layer M1. In the standard cells 1 and 2, the P-type transistor region PA and the N-type transistor region NA are arranged in the Y direction between the power supply line VDD and the power supply line VSS. The standard cell 1 has two fins 11 extending in the X direction in the P-type transistor region PA, and two fins 12 extending in the X direction in the N-type transistor region NA. The standard cell 2 has two fins 21a extending in the X direction and two fins 21b extending in the X direction in the P-type transistor region PA, and two fins 22a extending in the X direction in the N-type transistor region NA and two fins 22b extending in the X direction. The fins 21a and 21b are arranged on the same line, and the fins 22a and 22b are arranged on the same line. In FIG. 1 and other top views, a fin FET is constituted by a fin and a gate wiring formed thereon. The gate wiring surrounds the fin from three directions. It should be noted that, in FIG. 1 and other plan views, the fins are shown in gray for the sake of clarity.

In the wiring layer L1 in direct contact with the fin layer, local wiring is provided. A portion of the local wiring that overlaps with the fin or gate wiring in a plan view is formed so as to be in contact with the upper layer of the fin or gate wiring, and the local wiring is electrically connected to the fin or gate wiring. The metal wiring is located on the upper layer of the local wiring, and is connected to the local wiring via a contact.

The standard cell 1 includes gate wirings 13 and 14 extending in the Y direction across the P-type transistor region PA and the N-type transistor region NA. The fin 11 and the gate wirings 13 and 14 constitute the fin FETs P11 and P12, respectively. The fin 12 and the gate wirings 13 and 14 constitute the fin FETs N11 and N12, respectively. 15a and 15b are dummy gate wirings. Local wirings 16 extending in the Y direction are provided between both ends of the fins 11 and 12 and the gate wirings 13 and 14 , respectively. Both ends of the fin 11 are connected to the power supply line VDD via the local wiring 16 and the contact 17 . One end (the left end in the figure) of the fin 12 is connected to the power supply line VSS via the local wiring 16 and the contact 17 . The gate wiring 13 is connected to the metal wiring 18a via the local wiring 16 and the contact 17, wherein the input A is applied to the metal wiring 18a; the gate wiring 14 is connected to the metal wiring 18b via the local wiring 16 and the contact 17, wherein, Input B is applied to metal wiring 18b. The metal wiring 18c outputs Y output, and the metal wiring 18c is connected to the other end (right end in the figure) of the fin 11 and the fin 12 between the gate wirings 13 and 14 via the local wiring 16 and the contact 17 .

The standard cell 2 includes gate wirings 23, 24, 25, 26 extending in the Y direction across the P-type transistor region PA and the N-type transistor region NA. In the P-type transistor region PA, the fin 21 a and the gate wiring 23 constitute the fin FET P21 , and the fin 21 a and the gate wiring 24 constitute the fin FET P22 . The fin FETs P21 and P22 share one source, and the source is connected to the power supply line VDD via the local wiring 31 and the contact 28 extending in the Y direction. The fin 21 b and the gate wiring 25 constitute the fin FET P23 , and the fin 21 b and the gate wiring 26 constitute the fin FET P24 . The fin FETs P23 and P24 share one source, and the source is connected to the power supply line VDD via the local wiring 31 and the contact 28 extending in the Y direction.

In the N-type transistor region NA, the fin 22a and the gate wiring 23 constitute the fin FET N21, and the fin 22a and the gate wiring 24 constitute the fin FET N22. The fin FETs N21 and N22 share one source, and the source is connected to the power supply line VSS via the local wiring 31 and the contact 28 extending in the Y direction. The fin 22b and the gate wiring 25 constitute the fin FET N23, and the fin 22b and the gate wiring 26 constitute the fin FET N24. The fin FETs N23 and N24 share one source, and the source is connected to the power supply line VSS via the local wiring 31 and the contact 28 extending in the Y direction.

27a, 27b, and 27c are dummy gate wirings. The dummy gate wiring 27c extends in the Y direction and passes between the fins 21a and 21b and between the fins 22a and 22b. The dummy gate wiring 27c is provided at a distance from the fins 21a, 21b, 22a, and 22b.

In the standard cell 2, metal wirings 29a to 29e are provided. The metal wiring 29a is connected to the gate wiring 23 . That is, the metal wiring 29 a is connected to the gates of the fin FETs P21 and N21 and corresponds to the input C of the standard cell 2 . The metal wiring 29b connects one end (the left end in the figure) of the fins 21a and 22a to the gate wiring 24 . That is, the metal wiring 29b connects the drains of the fin FETs P21 and N21 and the gates of the fin FETs P22 and N22. The metal wiring 29c connects the other ends (right ends in the figure) of the fins 21a and 22a to the gate wiring 25 . That is, the metal wiring 29c connects the drains of the fin FETs P22 and N22 and the gates of the fin FETs P23 and N23. The metal wiring 29d connects one end (the left end in the figure) of the fins 21b and 22b to the gate wiring 26 . That is, the metal wiring 29d connects the drains of the fin FETs P23 and N23 and the gates of the fin FETs P24 and N24. The metal wiring 29e connects the other end (right end in the figure) of the fin 21b and the other end (the right end in the figure) of the fin 22b. That is, the metal wiring 29e connects the drains of the fin FETs P24 and N24 to each other, and corresponds to the output Z of the standard cell 2 .

Here, focus on the local routing that connects the fins to the power lines.

In the P-type transistor region PA of the standard cell 2, the local wiring 31 is connected to the fins 21a and 21b and extends in the Y direction. That is, the protruding length (protrusion length) D2 of the local wiring 31 from the fins 21 a and 21 b in the direction away from the power supply line VDD is larger than that of the local wiring 16 in the P-type transistor region PA of the standard cell 1 protruding from the fin 11 in the direction away from the power supply line VDD The length (protrusion length) D1. Similarly, in the N-type transistor region NA of the standard cell 2, the local wiring 31 is connected to the fins 22a, 22b and extends in the Y direction, and the local wiring 31 goes beyond the fins 22a, 22b to further extend a long distance inside the cell.

In a general standard cell, in order to suppress the increase of parasitic capacitance, the length of the local wiring is set to a minimum. For example, the protruding length D1 of the local wiring 16 in the standard cell 1 is preferably the minimum value allowed by the manufacturing process. On the other hand, in the present embodiment, in the standard cell 2 that is a delay cell, in order to increase the wiring capacitance and further increase the delay, the local wiring 31 is extended further inside the cell beyond the fins 21a, 21b, 22a, and 22b. long distance. By extending the local wiring 31 a long distance, the parasitic capacitance between the local wiring 31 and the gate wirings 23 , 24 , 25 , and 26 becomes larger, so that the delay value can be increased. Therefore, the standard cell 2 , which is a delay cell having a large delay value per unit area, can be realized.

It should be noted that, in the structure of FIG. 1 , in the standard cells 1 and 2, the number of fins 11 is equal to the number of fins 21a and 21b, and the position of the fin 11 in the Y direction is the same as that of the fins 21a and 21b in the Y direction. The position in the direction is the same. However, the present disclosure is not limited thereto, the number of fins 11 may not be equal to the number of fins 21a, 21b, and the position of the fin 11 in the Y direction may be different from the position of the fins 21a, 21b in the Y direction. In either case, it is sufficient to compare the protruding length of the local wiring from the end of the fin closer to the inside of the cell as the protruding length.

In the structure of FIG. 1 , the standard cells 1 and 2 are arranged in the same cell column extending along the X direction, but the present disclosure is not limited thereto, and the standard cells 1 and 2 may also be arranged in different cell columns.

In addition, the circuit configuration of the delay unit is not limited to the configuration shown in FIG. 3( b ). For example, the number of inverters connected in series may be other than four, such as two or six. Alternatively, the circuit configuration of the delay unit may be the circuit configuration shown in FIG. 4 . In FIG. 4( a ), a structure in which an inverter and a switch circuit are connected in series, and the switch circuit is constituted by a group of transistors of a P-type transistor and an N-type transistor is adopted. It should be noted that, in FIG. 4( a ), two partial circuits F1 composed of switching circuits and inverters are connected, but N (N is an even number) partial circuits F1 may be connected. A structure in which two or more switch circuits are connected in series may also be employed. In FIG. 4( b ), the P-type transistors and the N-type transistors are vertically stacked to form an inverter, and a part of the circuit F2 is formed by the inverter. It should be noted that, in FIG. 4( b ), two partial circuits F2 are connected, but N (N is an even number) partial circuits F2 may be connected. The inverter constituting part of the circuit F2 may also be constituted by vertically stacking three or more P-type transistors and three or more N-type transistors. That is, the delay unit may have any circuit configuration as long as it has a circuit configuration in which the input signal is delayed and then output.

(shape of metal wiring)

FIG. 5 is a plan view showing the shape of the metal wiring in the standard cell 2 of FIG. 1 . It should be noted that, in FIG. 5 , fins and gate wirings are omitted for simplicity of illustration. As described above, the standard cell 2 is provided with the metal wirings 29 a to 29 e , and the metal wirings 29 a to 29 e are used for connection to constitute the logic of the standard cell 2 .

In the present embodiment, redundant parts (parts marked with black dots in FIG. 5 ) are added to the metal wiring for connecting the logic for configuring the standard cell 2 , and the redundant parts are not used for configuring the logic. part. With this redundant portion, the wiring capacitance of the signal line can be increased, and the delay can be further increased.

Specifically, the metal wiring 29c has a main portion 40a and redundant portions 41 and 42 . The main portion 40a (the portion of the metal wiring 29c without the black dots) connects the logic for constituting the standard cell 2. Specifically, the main portion 40a connects the drains of the fin FETs P22 and N22 to the fin FETs P23, The gate of N23 is connected. On the other hand, the redundant parts 41 and 42 are branched from the main part 40a in a direction (here, the X direction) different from the extending direction (here, the Y direction) of the main part 40a, and are electrically connected only to the main part 40a.

Likewise, the metal wiring 29d has the main portion 40b and the redundant portions 43 and 44 . The main portion 40b (the portion of the metal wiring 29d without the black dots) connects the logic for constituting the standard cell 2. Specifically, the main portion 40b connects the drains of the fin FETs P23 and N23 to the fin FETs P24, The gate of N24 is connected. On the other hand, the redundant parts 43 and 44 are branched from the main part 40b in a direction (here, the X direction) different from the extending direction (here, the Y direction) of the main part 40b, and are electrically connected only to the main part 40b. The metal wiring 29e has a main portion 40c and redundant portions 45 and 46 . The main part 40c (the part without black dots in the metal wiring 29e) connects the logic for configuring the standard cell 2, and specifically, the main part 40c connects the drains of the fin FETs P24 and N24 to each other. On the other hand, the redundant parts 45 and 46 are branched from the main part 40c in a different direction (here, the X direction) from the extending direction (here, the Y direction) of the main part 40c, and are electrically connected only to the main part 40c.

FIG. 6 is a diagram showing the layout structure of the standard cell 2 in the case where the redundant portion is not included in the metal wiring as a comparative example. As can be seen from FIG. 6 , even if the redundant parts 41 to 46 are removed from the layout of FIG. 5 , there is no problem with the logic constituting the standard cell 2 .

As described above, in the metal wirings 29c, 29d, and 29e for connecting the logic for configuring the standard cell 2, the redundant portions 41 to 46 that are not used for configuring the logic are provided, so that the wiring capacitance of the signal line can be increased. , so that the delay can be further increased.

In the structure of FIG. 5 , the metal wiring 29d corresponding to the first wiring has the redundant portion 43, and the metal wiring 29e corresponding to the second wiring has the redundant portion 45, and the redundant portion 43 and the redundant portion 45 are in the same direction ( X direction here), and in the direction perpendicular to the same direction (Y direction here), the redundant portion 43 and the redundant portion 45 are adjacent to each other without other metal wiring. Similarly, the metal wiring 29d has a redundant portion 44, and the metal wiring 29e has a redundant portion 46. The redundant portion 44 and the redundant portion 46 extend in the same direction (here, the X direction) and in a direction perpendicular to the same direction. In the Y direction (here, the Y direction), the redundant portion 44 and the redundant portion 46 are adjacent to each other without any other metal wiring. According to the above configuration, the wiring capacitance of the signal line can be further increased, and the delay can be further increased.

Furthermore, in the inverter constituted by the fin FETs P24 and N24, the metal wiring 29d is connected to the input terminal of the inverter, and the metal wiring 29e is connected to the output terminal of the inverter. In this way, in the metal wirings 29d and 29e, which are the input signal lines and the output signal lines of the same inverter, by making the redundant parts 43 and 45 adjacent to each other and the redundant parts 44 and 46 adjacent to each other, it is possible to further improve the Increase the delay of the signal line. In addition, in the metal wiring which becomes the input signal line and the output signal line of the logic gate other than an inverter, you may adjoin a redundant part.

(Variation)

FIG. 7 shows a modification of the layout structure of the standard cell 2 of FIG. 1 . In addition, in FIG. 7, illustration of a fin is abbreviate|omitted for illustration simplicity. In the structure of FIG. 7, the dummy gate wiring 27c is connected to the gate wiring 25 and the metal wiring 29c via the local wiring 51 (portion with black dots). That is, the dummy gate wiring 27c is connected to the signal line to constitute a capacitance. The signal line connects the inverter composed of the fin FETs P22 and N22 and the inverter composed of the fin FETs P23 and N23. In this way, the wiring capacitance of the signal line can be increased, and the delay can be further increased.

FIG. 8 shows a modification of the layout structure of the standard cell 2 of FIG. 1 . In addition, in FIG. 8, illustration of a fin is abbreviate|omitted for illustration simplicity. In the structure of FIG. 8 , the dummy gate wiring 27c is connected to the metal wiring 29c via the local wiring 61 (portion with black dots), and is connected to the gate wiring 25 via the local wiring 62 (portion with black dots). That is, the dummy gate wiring 27c is connected to constitute a part of the signal line. The signal line connects the inverter composed of the fin FETs P22 and N22 and the inverter composed of the fin FETs P23 and N23. In this way, the dummy gate wiring 27c contributes to both the delay of the signal line and the increase of the wiring capacitance, so that the delay of the signal line can be further increased.

(Another example of a three-dimensional transistor device)

In each of the above-mentioned embodiments, the fin-type FET is used as an example for description, but a three-dimensional transistor device other than the fin-type FET, such as a nanowire FET, may also be used.

10 is a schematic diagram showing a basic configuration example of a nanowire FET (also referred to as a gate-all-around (GAA: Gate AllAround) type configuration). Nanowire FETs are FETs using thin wires (nanowires) through which current flows. Nanowires are formed of silicon, for example. As shown in FIG. 10 , the nanowire extends in a horizontal direction on the substrate, ie, extends parallel to the substrate, and the two ends of the nanowire are connected to the structures constituting the source region and the drain region of the nanowire FET. In the specification of the present application, a structure connected to both ends of the nanowire and constituting the source region and the drain region of the nanowire FET is referred to as a pad. In FIG. 10 , an STI (Shallow Trench Isolation) structure is formed on a silicon substrate, and the silicon substrate is exposed below the nanowires (parts with oblique lines). In addition, although the shaded part is actually covered with a thermal oxide film etc., in FIG. 10, illustration of a thermal oxide film etc. is abbreviate|omitted in order to simplify illustration.

The nanowire is surrounded by a gate electrode made of polysilicon, for example, through an insulating film such as a silicon oxide film. Pads and gate electrodes are formed on the surface of the substrate. According to this configuration, since the upper portion, both sides, and lower portion of the channel region of the nanowire are all surrounded by the gate electrode, a uniform electric field can be generated in the channel region. In this way, the FET will have good switching characteristics.

It should be noted that at least the portion of the pad to which the nanowire is connected constitutes the source region/drain region, but the portion lower than the portion to which the nanowire is connected may not necessarily constitute the source region/drain region. . Also, in some cases, a part of the nanowire (the part not surrounded by the gate electrode) constitutes the source/drain region.

In FIG. 10, two nanowires are arranged in the longitudinal direction, ie, the direction perpendicular to the substrate. However, the number of nanowires arranged in the longitudinal direction is not limited to two, and may be one, or three or more nanowires may be arranged in the longitudinal direction. In Figure 10, the upper end of the uppermost nanowire is flush with the upper end of the pad. However, it is not necessary for them to be flush in height, and the upper end of the pad can also be higher than the upper end of the uppermost nanowire.

There is also a case shown in FIG. 11 in which a BOX (Buried Oxide) is formed on the upper surface of the substrate, and a nanowire FET is formed on the BOX.

It should be noted that, in the above-mentioned embodiment, when the nanowire FET is used instead of the fin FET to form a semiconductor integrated circuit device, the following part corresponds to the fin of the fin FET, and the part is: one of the nanowire FETs a nanowire or a plurality of nanowires arranged in a direction perpendicular to the substrate; and a pad connected to both ends of the nanowire. For example, the two fins 21a in the standard cell 2 of FIG. 1 can be respectively changed to a configuration in which one extending in the X direction or a plurality of nanowires arranged in the direction perpendicular to the substrate are alternately connected to the pads formed structure. That is, in the configuration using the nanowire FET, the nanowire and the pads connected to both ends thereof correspond to the three-dimensional diffusion layer portion. The local wirings are connected to the pads in the structure corresponding to the three-dimensional diffusion layer portion.

In addition, each component in a some embodiment can be combined arbitrarily in the range which does not deviate from the summary of invention.

-Industrial applicability-

According to the present disclosure, in a semiconductor integrated circuit device using a three-dimensional transistor device, a delay cell having a large delay value per unit area can be realized. Therefore, it is advantageous to improve the performance of the semiconductor integrated circuit device.

-Symbol Description-

1 first standard unit

2 Second standard unit

11, 12, 21a, 21b, 22a, 22b Fin (three-dimensional diffusion layer part)

13, 14, 23, 24, 25, 26 Gate wiring

16, 31 Local wiring

P11, P12, N11, N12, P21, P22, P23, P24, N21, N22, N23, N24

FinFET (Three-Dimensional Transistor Device)

27c Dummy gate routing

29a to 29e Metal wiring

40a, 40b, 40c main part

41 to 46 Redundant part

VDD power line

VSS power cord

Claims (9)

1. a kind of conductor integrated circuit device, it is characterised in that:

The conductor integrated circuit device includes the first standard block and the second standard block,

First standard block is logic unit, and has three-dimensional crystal tube device,

Second standard block is delay cell, and has three-dimensional crystal tube device,

First standard block includes:

The three-dimensional diffusion layer portion of one first extended in a first direction or the multiple first three-dimensional expansions extended along the first direction Dissipate layer portion, wherein multiple described first three-dimensional diffusion layer portions are arranged along the second direction vertical with the first direction；And

First partial wiring, extends along the second direction, and connects the described first three-dimensional diffusion layer portion and power supply line, described Power supply line extends along the first direction and supplies defined first supply voltage,

Second standard block includes:

Along the one second three-dimensional diffusion layer portion that the first direction extends or along multiple the second of first direction extension Three-dimensional diffusion layer portion, wherein multiple described second three-dimensional diffusion layer portions are arranged along the second direction；

Second local wiring extends along the second direction, and connects the described second three-dimensional diffusion layer portion and the power supply line； And

Grid wiring extends along the second direction and intersects when looking down with the described second three-dimensional diffusion layer portion, and is formed To surround the described second three-dimensional diffusion layer portion, and defined second source voltage is applied on the grid wiring,

Second local wiring described in second standard block is from the described second three-dimensional diffusion layer portion towards far from the power supply line Direction length outstanding, be greater than the wiring of first partial described in first standard block from the described first three-dimensional diffusion layer portion Towards the direction length outstanding far from the power supply line.

2. conductor integrated circuit device according to claim 1, it is characterised in that:

The number in the described first three-dimensional diffusion layer portion is equal to the number in the described second three-dimensional diffusion layer portion, and the described first three-dimensional expansion It is identical as the position of the described second three-dimensional diffusion layer portion in this second direction to dissipate the position of layer portion in this second direction.

3. conductor integrated circuit device according to claim 1, it is characterised in that:

Second standard block includes metal line, and the metal line is formed in the upper layer of second local wiring,

The metal line includes the first wiring,

First wiring has principal part and redundancy portion,

The principal part carries out the connection to constitute the logic of second standard block,

The redundancy portion from the principal part to the direction branch different from the extending direction of the principal part, and only with principal part electricity Connection.

4. conductor integrated circuit device according to claim 3, it is characterised in that:

The metal line includes the second wiring, and second wiring has the principal part and the redundancy portion,

Described first, which is routed the possessed redundancy portion and described second, is routed the possessed redundancy portion in the same direction Extend, and on the direction vertical with the same direction, described first is routed the possessed redundancy portion and second cloth It is adjacent without others metal line between the redundancy portion possessed by line.

5. conductor integrated circuit device according to claim 4, it is characterised in that:

Second standard block includes the logic gate being made of three-dimensional crystal tube device,

First wiring is connected with the input terminal of the logic gate,

Second wiring is connected with the output end of the logic gate.

6. conductor integrated circuit device according to claim 5, it is characterised in that:

The logic gate is phase inverter.

7. conductor integrated circuit device according to claim 1, it is characterised in that:

Second standard block includes dummy gate wiring, and the dummy gate wiring extends along the second direction, and with Described second three-dimensional diffusion layer portion is arranged with keeping spacing,

The dummy gate wiring is connected with following wirings, which carries out the company to constitute the logic of second standard block It connects.

8. conductor integrated circuit device according to claim 7, it is characterised in that:

The dummy gate wiring constitutes a part of following wirings, which carries out to constitute patrolling for second standard block The connection collected.

9. according to claim 1 to conductor integrated circuit device described in any one of 8 claims, it is characterised in that:

The three-dimensional crystal tube device is fin formula field effect transistor or nano-wire field effect transistor.