CN110287071B - PCIE interface speed measuring card compatible with high and low speed - Google Patents
PCIE interface speed measuring card compatible with high and low speed Download PDFInfo
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- CN110287071B CN110287071B CN201910510935.7A CN201910510935A CN110287071B CN 110287071 B CN110287071 B CN 110287071B CN 201910510935 A CN201910510935 A CN 201910510935A CN 110287071 B CN110287071 B CN 110287071B
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- 238000005259 measurement Methods 0.000 claims abstract description 17
- 238000012360 testing method Methods 0.000 claims abstract description 7
- 238000001514 detection method Methods 0.000 claims abstract description 6
- 230000015654 memory Effects 0.000 claims description 46
- 230000005669 field effect Effects 0.000 claims description 24
- 239000003990 capacitor Substances 0.000 claims description 21
- 239000013256 coordination polymer Substances 0.000 claims description 15
- 230000006870 function Effects 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000001105 regulatory effect Effects 0.000 claims 1
- 238000013461 design Methods 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Mathematical Physics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a PCIE speed measuring card, which belongs to the field of PCIE test cards, wherein four card interfaces of X1, X4, X8 and X16 are integrated on a circuit board through an optimized circuit design and a circuit multiplexing mechanism. The invention expands the speed measurement application range, achieves one card with multiple purposes, saves the use cost and time, and improves the test efficiency. The specific technical characteristics of the invention are as follows: 1. the system is multiparty optimized and the detection is accurate; 2. the circuit is simple and reasonable, and the structure is optimized; 3. 4 kinds of plug-in card interfaces are integrated, and the compatibility is good.
Description
Technical Field
The invention relates to the field of PCIE speed measurement cards, in particular to a high-low-speed compatible PCIE interface speed measurement card.
Background
With the development of modern computer technology, it is a trend to use high-speed differential buses with superior performance instead of parallel buses. High-speed differential signals can use higher clock frequencies than single-ended parallel signals, thus using fewer signal lines, completing the bus bandwidth that previously required many single-ended parallel data signals.
The PCIE bus is a high-speed differential bus, and adopts an end-to-end connection mode, so that besides the PCIE bus topology structure and the connection mode are different from those of the PCI bus, some technologies used in network communication are used, such as supporting multiple data routing modes, a data transmission mode based on multiple paths, and a data transmission mode based on messages, and the problem of quality of service QoS (QualityofService) in data transmission is fully considered.
For the above reasons, modern computer systems often need several PCIE interfaces, taking PCIE3.0 version as an example, the data transmission peak value is 8GT/s, and the theoretical data throughput of X1, X4, X8 and X16 channel interfaces reach 980MB/s, 3.9GB/s, 7.8GB/s and 15.7GB/s, respectively, so that the data transmission performance is very superior.
In practice, for different PCIE interfaces on various boards, it is necessary to detect transmission performance of the PCIE interfaces to ensure reliability of the product. Because PCIE versions are more, and different versions have different channel specifications, a certain challenge is brought to detection means.
At present, most PCIE speed measuring cards on the market have the problems of complex circuits, poor detection precision, poor reliability and single function, and have great improvement space in the aspects of compatibility, stability and expansibility.
Disclosure of Invention
In order to solve the problems, the invention redesigns and analyzes the PCIE interface speed measuring circuit, finds out key factors influencing the accuracy of the PCIE interface speed measuring circuit, adopts an accurate, economical and reliable digital technical scheme, develops a novel PCIE interface speed measuring card, ensures the detection effect and is popular with users.
The technical problems to be solved by the invention are realized by adopting the following scheme:
A PCIE interface speed measuring card compatible with high and low speed comprises 1 channel golden finger, 4 channel golden fingers, 8 channel golden fingers, 16 channel golden fingers, speed measuring circuit and the like.
The 1, 4, 8 and 16 channel golden fingers are respectively designed on 4 edges of the speed measuring card so as to be maximally suitable and compatible with the slots of different specifications of the tested equipment, and achieve the design target of circuit multiplexing.
The speed measuring circuit comprises a logic control circuit, a switching circuit and a memory unit.
The logic control circuit is used for receiving the voltage signal, the reset signal and the differential reference clock signal transmitted by the peripheral component interface and outputting a control signal in normal time.
In the logic control circuit, a differential clock signal is connected with a CP pin of a trigger U3 through a resistor R1 by an auxiliary power supply pin of a capacitor C1 and 3.3V; the clock signal pin CP of the trigger U1 is also grounded through a resistor R2; VCC of the trigger U3 is connected with an auxiliary power supply of 3.3V and grounded through a capacitor C2; the SD pin of the trigger U3 is connected with a 3.3V auxiliary power supply through a resistor R3; the RD pin of the trigger U3 is connected with a 3.3V auxiliary power supply through a R4, and is grounded through a capacitor C3 and a resistor R4; the output pin Q of the trigger U3 is connected with the grid electrode of the field effect transistor P1 through R12 so as to receive a control signal output by the trigger U3; GND of the flip-flop U3 is grounded.
In the logic control circuit, a 3.3V auxiliary power supply pin of a PCIE interface is connected with a clock signal pin CP of a trigger U1 through a resistor R6; the differential reference clock signal pin of the PCIE interface is connected with the clock signal pin CP of the trigger U1 through the capacitor C4 so as to receive the differential reference clock signal output by the PCIE interface; the clock signal pin CP of the flip-flop U1 is also grounded through a resistor R7; the power supply pin VCC of the trigger U1 is connected with the 3.3V auxiliary power supply pin of the PCIE interface and is grounded through a capacitor C5; the reset pin of the PCIE interface is connected with the signal input pin D of the trigger U1 to receive a reset signal output by the PCIE interface; the 3.3V auxiliary power supply pin of the PCIE interface U1 is connected with the control pin SD of the trigger U1 through a resistor R8. The 3.3V voltage pin of the PCIE interface is connected with the control pin RD of the trigger U1 through a resistor R9, is grounded through a resistor R10, and is connected with a capacitor C6 in parallel with the resistor R10. The ground pin GND of the flip-flop U1 is grounded.
The switching circuit is used for receiving the control signal output by the logic control circuit and outputting a switching signal according to the received control signal.
The switching circuit mainly comprises two field effect transistors P1 and P2. The 12V voltage pin of the PCIE interface is connected with the drain electrode of the field effect transistor P1 through the R11 and the light emitting diode D2; the source electrode of the field effect transistor P1 is connected with the drain electrode of the field effect transistor P2; the source electrode of the field effect transistor P2 is grounded; the output pin Q of the trigger U1 is connected with the grid electrode of the field effect transistor P2 through a resistor R13; the control pin C1 of the relay U2 is grounded; the differential signal sending pin and the differential signal receiving pin of the PCIE interface are connected with the pin of the relay U2; the 12V voltage pin of the PCIE interface is connected with the power pin VCC of the relay U2; a freewheeling diode D1 is also connected in anti-parallel between the ground pin GND and the power pin VCC of the relay U2.
Preferably, the types of the triggers U1 and U3 are 74ALVC D, the type of the relay U2 is G8K-4F, and the types of the field effect transistors P1 and P2 are 2N3904.
A 3.3V voltage pin of a PCIE interface of a memory U4 in the memory unit is connected with a U4 power pin VCC and grounded through a capacitor C7; the function pin WP of the memory U4 is grounded; the system management bus clock pin SMCLK of the PCIE interface U1 is connected with the clock pin SCL of the memory U4; the system management bus data pin SMDAT of the PCIE interface is connected to the data pin SDA of the memory U4; pin GND of memory U4 is grounded.
And the ends 1,2 and 3 of the dial switch are connected with 3.3V voltage pins of the PCIE interface. The dial switch port 4 is grounded through a resistor R16 and is connected with a third address pin A2 of the memory U4; the dial switch port 5 is grounded through a resistor R15 and is connected with a second address pin A1 of the memory U4; the dial switch port 6 is grounded through a resistor R14 and is connected to the address pin A0 of the memory U4. The switching combination of the 3-bit dial switch in the dial switch unit SW is selected to output different high-low level signals to the first to third address pins of the memory U4, so that the PCIE interface reads the data of the memory U4, and further tests whether the system management bus clock signal and the data signal transmitted by the PCIE interface are normal.
Preferably, the memory U4 is a charged erasable programmable read-only memory (EEPROM), and the model is AT32C64; the dial switch SW model is DIP-3.
The invention simplifies the design, optimizes the adjustment and configuration of the speed measuring circuit, and improves the reliability and adaptability of the invention; the invention can enrich the application range by developing functional software, improve the speed measurement performance and reduce the maintenance cost of the computer system.
Drawings
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a schematic block diagram of the present invention;
FIG. 3 is a circuit diagram of a processing unit according to the present invention;
FIG. 4 is a circuit diagram of a dial switch unit according to the present invention;
x1:1 channel golden finger 11
X4: 4-channel golden finger 22
X8: 8-channel golden finger 33
X16: 16-channel golden finger 44
Speed measuring circuit 55
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in FIG. 1, the invention is composed of 1 channel golden finger 11, 4 channel golden fingers 22, 8 channel golden fingers 33, 16 channel golden fingers 44, a speed measuring circuit 55 and the like, and the measuring result can be directly read out through a card-carried nixie tube or can be matched with on-line detection through matched software.
As shown in fig. 2, the tachometer circuit portion includes a logic control circuit, a switching circuit, and a memory unit.
As shown in fig. 3, the logic control circuit is configured to receive the voltage signal, the reset signal, the differential reference clock signal and the normal output control signal transmitted by the peripheral component interface; the switching circuit is used for receiving the control signal output by the logic control circuit and outputting a switching signal according to the received control signal.
As shown in fig. 4, the memory unit includes a number of memories and a dial switch.
Preferably, a differential clock signal in the logic control circuit is connected with a CP pin of the trigger U3 through a resistor R1 by an auxiliary power supply pin of the capacitor C1 and 3.3V; the clock signal pin CP of the trigger U1 is also grounded through a resistor R2; VCC of the trigger U3 is connected with an auxiliary power supply of 3.3V and grounded through a capacitor C2; the SD pin of the trigger U3 is connected with a 3.3V auxiliary power supply through a resistor R3; the RD pin of the trigger U3 is connected with a 3.3V auxiliary power supply through a R4, and is grounded through a capacitor C3 and a resistor R4; the output pin Q of the trigger U3 is connected with the grid electrode of the field effect transistor P1 through R12 so as to receive a control signal output by the trigger U3; GND of the flip-flop U3 is grounded.
Preferably, a 3.3V auxiliary power supply pin of a PCIE interface in the logic control circuit is connected with a clock signal pin CP of a trigger U1 through a resistor R6; the differential reference clock signal pin of the PCIE interface is connected with the clock signal pin CP of the trigger U1 through the capacitor C4 so as to receive the differential reference clock signal output by the PCIE interface; the clock signal pin CP of the flip-flop U1 is also grounded through a resistor R7; the power supply pin VCC of the trigger U1 is connected with the 3.3V auxiliary power supply pin of the PCIE interface and is grounded through a capacitor C5; the reset pin of the PCIE interface is connected with the signal input pin D of the trigger U1 to receive a reset signal output by the PCIE interface; the 3.3V auxiliary power supply pin of the PCIE interface U1 is connected with the control pin SD of the trigger U1 through a resistor R8. The 3.3V voltage pin of the PCIE interface is connected with the control pin RD of the trigger U1 through a resistor R9, is grounded through a resistor R10, and is connected with a capacitor C6 in parallel with the resistor R10. The ground pin GND of the flip-flop U1 is grounded.
Preferably, the main part of the switching circuit comprises two field effect transistors P1 and P2. The 12V voltage pin of the PCIE interface is connected with the drain electrode of the field effect transistor P1 through the R11 and the light emitting diode D2; the source electrode of the field effect transistor P1 is connected with the drain electrode of the field effect transistor P2; the source electrode of the field effect transistor P2 is grounded; the output pin Q of the trigger U1 is connected with the grid electrode of the field effect transistor P2 through a resistor R13; the control pin C1 of the relay U2 is grounded; the differential signal sending pin and the differential signal receiving pin of the PCIE interface are connected with the pin of the relay U2; the 12V voltage pin of the PCIE interface is connected with the power pin VCC of the relay U2; a freewheeling diode D1 is also connected in anti-parallel between the ground pin GND and the power pin VCC of the relay U2.
Preferably, a 3.3V voltage pin of a PCIE interface of a memory U4 in the memory unit is connected to a U4 power pin VCC and grounded through a capacitor C7; the function pin WP of the memory U4 is grounded; the system management bus clock pin SMCLK of the PCIE interface U1 is connected with the clock pin SCL of the memory U4; the system management bus data pin SMDAT of the PCIE interface is connected to the data pin SDA of the memory U4; pin GND of memory U4 is grounded.
Preferably, the 1,2 and 3 ends of the dial switch in the memory unit are all connected with the 3.3V voltage pin of the PCIE interface. The dial switch port 4 is grounded through a resistor R16 and is connected with a third address pin A2 of the memory U4; the dial switch port 5 is grounded through a resistor R15 and is connected with a second address pin A1 of the memory U4; the dial switch port 6 is grounded through a resistor R14 and is connected to the address pin A0 of the memory U4. The switching combination of the 3-bit dial switch in the dial switch unit SW is selected to output different high-low level signals to the first to third address pins of the memory U4, so that the PCIE interface reads the data of the memory U4, and further tests whether the system management bus clock signal and the data signal transmitted by the PCIE interface are normal.
Preferably, the types of the triggers U1 and U3 are 74ALVC D, the type of the relay U2 is G8K-4F, the types of the field effect transistors P1 and P2 are 2N3904, the type of the memory U4 is AT32C64, and the type of the dial switch SW is DIP-3.
The principle of the invention is as follows:
The invention can independently complete the task of testing the speed of the PCIE sending data, and can also complete the task of sending and receiving bidirectional speed measurement by combining special matched software. When the speed measurement is transmitted, the integrated test code generator generates high-quality data flow with the maximum speed of 8Gbps, the parameters of the signals can be written in advance by matched software and can be adjusted by the software, the data is transmitted out through an interface, the integrated speed measurement circuit measures the transmission speed in real time, and the measured value can be directly read out through a card-mounted nixie tube and can be displayed in real time on a software interface; and when the speed measurement is received, the speed measurement is completed by matching the matched software with a speed measurement card, and the measurement result is displayed on a software interface. The invention can also support high-speed serial data of 28Gbps at the highest through subsequent upgrading, and can fully consider future higher-speed application.
The foregoing has outlined and simplified the main features of the present invention and the advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (1)
1. A high-low speed compatible PCIE interface speed measuring card, characterized by comprising: 1 channel golden finger, 4 channel golden fingers, 8 channel golden fingers, 16 channel golden fingers and a speed measuring circuit; the measurement result can be directly read out through the card-carried nixie tube, or matched with the on-line detection through matched software;
Wherein the following steps: the 1 channel golden finger, the 4 channel golden fingers, the 8 channel golden fingers and the 16 channel golden fingers are respectively designed on 4 edges of the speed measuring card;
The speed measuring circuit comprises a logic control circuit, a switching circuit and a memory unit;
the logic control circuit is used for receiving the voltage signal, the reset signal and the differential reference clock signal transmitted by the peripheral component interface and outputting a control signal in normal time;
the switching circuit is used for receiving the control signal output by the logic control circuit and outputting a switching signal according to the received control signal;
the memory unit comprises a plurality of memories and a dial switch;
In the logic control circuit, differential reference clock signals are connected with a CP pin of a trigger U3 through auxiliary power supply pins of capacitors C1 and 3.3V and a resistor R1;
The clock signal pin CP of the flip-flop U3 is also grounded through a resistor R2;
The VCC pin of the trigger U3 is connected with an auxiliary power supply of 3.3V and grounded through a capacitor C2;
the SD pin of the trigger U3 is connected with a 3.3V auxiliary power supply through a resistor R3;
The RD pin of the trigger U3 is connected with a 3.3V auxiliary power supply through a resistor R4 and grounded through a capacitor C3 and a resistor R5;
the output pin Q of the trigger U3 is connected with the grid electrode of the field effect transistor P1 through a resistor R12 so as to receive a control signal output by the trigger U3;
The GND pin of the trigger U3 is grounded;
In the logic control circuit, a 3.3V auxiliary power supply pin of a PCIE interface is connected with a clock signal pin CP of a trigger U1 through a resistor R6; the differential reference clock signal pin of the PCIE interface is connected with the clock signal pin CP of the trigger U1 through the capacitor C4 so as to receive the differential reference clock signal output by the PCIE interface;
The clock signal pin CP of the flip-flop U1 is also grounded through a resistor R7; the power supply pin VCC of the trigger U1 is connected with the 3.3V auxiliary power supply pin of the PCIE interface and is grounded through a capacitor C5;
The reset pin of the PCIE interface is connected with the signal input pin D of the trigger U1 to receive a reset signal output by the PCIE interface;
the 3.3V auxiliary power supply pin of the PCIE interface is connected with the control pin SD of the trigger U1 through a resistor R8;
The 3.3V voltage pin of the PCIE interface is connected with the control pin RD of the trigger U1 through a resistor R9, is grounded through a resistor R10, and a capacitor C6 is connected with the resistor R10 in parallel;
The ground pin GND of the trigger U1 is grounded;
the main part of the switching circuit comprises two field effect transistors P1 and P2;
the 12V voltage pin of the PCIE interface is connected with the drain electrode of the field effect transistor P1 through a resistor R11 and a light emitting diode D2; the source electrode of the field effect transistor P1 is connected with the drain electrode of the field effect transistor P2; the source electrode of the field effect transistor P2 is grounded;
The output pin Q of the trigger U1 is connected with the grid electrode of the field effect transistor P2 through a resistor R13;
the control pin of the relay U2 is grounded;
The differential signal sending pin and the differential signal receiving pin of the PCIE interface are connected with the pin of the relay U2;
the 12V voltage pin of the PCIE interface is connected with the power pin VCC of the relay U2, and a freewheeling diode D1 is also reversely connected in parallel between the ground pin GND of the PCIE interface and the power pin VCC of the relay U2;
The 3.3V voltage pin of the PCIE interface of the memory U4 in the memory unit is connected with the power pin VCC of the memory U4 and is grounded through a capacitor C7;
The function pin WP of the memory U4 is grounded, and the system management bus clock pin SMCLK of the PCIE interface is connected with the clock pin SCL of the memory U4; the system management bus data pin SMDAT of the PCIE interface is connected to the data pin SDA of the memory U4; the GND pin of the memory U4 is grounded;
The ends 1,2 and 3 of the dial switch are connected with a 3.3V voltage pin of the PCIE interface; the dial switch port 4 is grounded through a resistor R16 and is connected with a third address pin A2 of the memory U4; the dial switch port 5 is grounded through a resistor R15 and is connected with a second address pin A1 of the memory U4; the dial switch port 6 is grounded through a resistor R14 and is connected with an address pin A0 of the memory U4;
The switching combination of the 3-bit dial switch in the dial switch unit SW is selected to output different high-low level signals to the first to third address pins of the memory U4, so that the PCIE interface reads the data of the memory U4, and whether the system management bus clock signal and the data signal transmitted by the PCIE interface are normal or not is tested;
the model of the triggers U1 and U3 is selected as 74ALVC D;
the type of the relay U2 is G8K-4F;
the model number of the field effect transistors P1 and P2 is 2N3904;
the memory U4 is selected to be of a type AT32C64, and the dial switch unit SW is selected to be of a type DIP-3;
when the speed measurement is sent, the integrated test code generator generates high-quality data flow with the maximum speed of 8Gbps, the parameters of the signals can be written in advance by matched software or regulated by software, the data is sent out through a PCIE interface, the speed measurement circuit measures the sending speed in real time, and the measured value can be directly read out through a card-mounted nixie tube or displayed in real time on a software interface; when the speed measurement is received, the matched software is matched with a speed measurement card, and the measurement result is displayed on a software interface; high-speed serial data up to 28Gbps can also be supported by subsequent upgrades.
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| TW200841169A (en) * | 2007-04-10 | 2008-10-16 | Hon Hai Prec Ind Co Ltd | PCIE test card |
| CN103176118A (en) * | 2011-12-24 | 2013-06-26 | 鸿富锦精密工业（深圳）有限公司 | Peripheral Component Interconnect Express (PCI-E) signal testing device |
| CN104216809B (en) * | 2013-05-30 | 2016-12-28 | 中祥电子商务股份有限公司 | Signal-testing apparatus |
| CN105095035A (en) * | 2015-08-26 | 2015-11-25 | 浪潮电子信息产业股份有限公司 | PCIE test card for large-scale production test of computer mainboard |
| KR101884070B1 (en) * | 2016-08-31 | 2018-08-02 | 사단법인 엑시콘산학공동연구소 | PCIe test apparatus |
| CN207424192U (en) * | 2017-11-27 | 2018-05-29 | 郑州云海信息技术有限公司 | A kind of PCIE shock-testings card |
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