CN110244589A

CN110244589A - Multifunctional timer

Info

Publication number: CN110244589A
Application number: CN201810195579.XA
Authority: CN
Inventors: 魏寿强
Original assignee: Huada Semiconductor Co Ltd
Current assignee: Huada Semiconductor Co Ltd
Priority date: 2018-03-09
Filing date: 2018-03-09
Publication date: 2019-09-17

Abstract

The present invention relates to a kind of Multifunctional timers, for motor control, including counter and the PWM trigger being connected with counter, which includes that at least one pwm compares generation module, it is characterized in that, it includes: the comparison controller being connected with counter that pwm, which compares generation module,；By the output of comparison controller filtering clock generator as input, reference value register, compare output module and counter register；By the output digital filter as input of the filtering clock generator and the relatively output module；By the output Dead band controller as input of the relatively output module and the digital filter；And by it is described relatively output module and the Dead band controller output multiplexer as input.

Description

Multifunctional timer

Technical field

The present invention relates to Multifunctional timer (MFT), are mainly used for three-phase motor high-accuracy stable control module.Especially relate to And Multifunctional timer, by combining A/D converter (ADC) module, it is possible to provide the motor control schemes of various different applications. It can be used for occurring in emergency circumstances to stop motor driven in addition, the motor control of Multifunctional timer promptly inputs (EMI), by This realizes the protection to motor, such as overcurrent protection.

Background technique

Currently, the function of the timer of mainstream is more single on the market, for example, the work of existing timer having a single function To count with timing or for generating pulse-width signal (pwm signal).Present inventor is by improving timer Structure, so that timer has multi-functional.Moreover, by increase digital filter, burr signal is filtered out, so that into The PWM for entering Dead band controller is more stable, more accurate, to improve the stability and precision of PWM output.Of the invention is multi-functional In counter, by additional ADC module and digital filter, it can be achieved that following technical effect: 1) output of PWM it is more stable and Precision is higher；2) emergency brake signal stabilization and serious forgiveness is minimized.

Summary of the invention

Exemplary embodiment of the present invention aim to overcome that it is in the prior art above-mentioned and/or other the problem of. So that the PWM into Dead band controller is more stable, more accurate, and a variety of function of timer can be also achieved in simple structure Energy.

According to an aspect of the present invention, a kind of Multifunctional timer is provided, be used for motor control, including counter and with meter The PWM trigger that number device is connected, which includes that at least one pwm compares generation module, which is characterized in that pwm ratio It include: the comparison controller being connected with counter compared with module occurs；By the output of comparison controller filter as input Wave clock generator, compares output module and counter register at reference value register；By the filtering clock generator With the output digital filter as input of the relatively output module；By relatively output module and the digital filtering The output of device Dead band controller as input；And using the output of relatively output module and the Dead band controller as The multiplexer of input.

According to another aspect of the present invention, a kind of method for generating PWM output is provided, in the method by counter The count value of generation is exported to PWM trigger, which includes that at least one pwm compares generation module, by the pwm ratio It is proceeded as follows compared with module occurs: the output of counter is input to comparison controller；The output of comparison controller is inputted To filtering clock generator, reference value register, compare output module and counter register；The filtering clock is sent out The output of raw device and the relatively output module is input to digital filter；By relatively output module and the digital filtering The output of device is input to Dead band controller；And the output of relatively output module and the Dead band controller is input to more Path multiplexer.

Detailed description of the invention

Fig. 1 is the schematic block diagram of the Multifunctional timer of one embodiment of the present invention.

Fig. 2 is that the pwm of one embodiment of the present invention compares the schematic block diagram that module occurs.

Fig. 3 is the schematic diagram of the sawtooth wave count mode of one embodiment of the present invention.

Fig. 4 is the schematic diagram of the triangular wave count mode of one embodiment of the present invention.

Fig. 5 is the operation of the interruption masking counter of one embodiment of the present invention.

Fig. 6 is the operation of the interruption masking counter of another embodiment of the present invention.

Fig. 7 is the schematic block diagram of the comparison output module of one embodiment of the present invention.

Fig. 8 shows the output waveform under the PWM direct mode operation of one embodiment of the present invention.

Fig. 9 shows the dead zone Timer modes waveform of one embodiment of the present invention.

Figure 10 shows the dead zone Timer modes waveform of another embodiment of the present invention.

Figure 11 shows the dead zone timer filter patterns waveform of one embodiment of the present invention.

Figure 12 shows the dead zone timer filter patterns waveform of another embodiment of the present invention.

Specific embodiment

A specific embodiment of the invention explained below, it should be pointed out that in the specific descriptions of these embodiments In the process, in order to carry out brief and concise description, this specification can not all features to actual embodiment make in detail Most description.It is to be understood that during the actual implementation of any one embodiment, as in any one work During journey project or design object, in order to realize the objectives of developer, in order to meet, system is relevant or quotient The relevant limitation of industry can usually make various specific decisions, and this can also be implemented from a kind of embodiment to another kind It changes between mode.Moreover, it is to be understood that although effort made in this development process may be complicated And it is interminable, however for those skilled in the art relevant to present disclosure, in the disclosure The some designs carried out on the basis of the technology contents of exposure, the changes such as manufacture or production are conventional technology, no It should be understood as that content of this disclosure is insufficient.

Unless otherwise defined, technical term or scientific term used in claims and specification should be this hair The ordinary meaning that personage in bright technical field with general technical ability is understood.Present patent application specification and power " first ", " second " used in sharp claim and similar word are not offered as any sequence, quantity or importance, and It is used only to distinguish different component parts.The similar word such as "one" or " one " is not offered as quantity limitation, but indicates There are at least one.The similar word such as " comprising " or "comprising" means to appear in the element before " comprising " or "comprising" Either object covers the element for appearing in " comprising " or "comprising" presented hereinafter or object and its equivalent element, it is not excluded that Other elements or object." connection " either the similar word such as " connected " is not limited to physics or mechanical connection, It is also not necessarily limited to direct or indirect connection.

In the schematic block diagram of timer shown in Fig. 1, timer 1 include a public counters 13 and with this A connected PWM trigger 11 of public counters.Further, which includes that 3 pwm compare generation module, It is expressed as the first pwm and compares module 111, the 2nd pwm occurs to compare module 112 to occur and the 3rd pwm compares generation module 113.First pwm compares generation module 111, the 2nd pwm compares generation module 112 and the 3rd pwm compares generation module 113 respectively Export 2 signals, respectively PWM0, PWM1, PWM2, PWM3, PWM4, PWM5.Generally speaking, the output signal of PWM trigger It is PWM0~PWM5 6 road pwm signal in total.

Generally, the unit that Multifunctional timer includes has counters (Counter), compares output module (Output Compare&Output) and motor control promptly input (Emergency stop input).Counter is referred to as CNT, the movement reference count unit of the functional module as timer output MFT4.1 three-phase motor control unit includes 1 A counter unit.Compare output module (Output Compare&Output) and be referred to as OCO, is the count value with counter On the basis of, the functional module of output pwm signal is generated, the signal that output is compared generates the signal waveform of motor control.1 Three-phase motor control unit includes 3 comparison output units.Motor control promptly inputs (Emergency stop input) letter Referred to as EMI, for occurring in emergency circumstances to stop motor driven.

Next, discussing that pwm compares the structure that module occurs.Fig. 2 illustrates that the first pwm compares the block diagram that module occurs, It shows pwm and compares each component for occurring to include in module and its connection relationship.The block diagram that first pwm compares generator is shown In, include comparison controller, reference value register, counter register, compare output module, filtering clock generator, Digital filter, Dead band controller and multiplexer (Mux).In this block diagram, a first pwm ratio is schematicallyed depict Compared with generator, it is configured with a digital filter, but correspondingly, the 2nd pwm compares generator, the 3rd pwm compares generator Structure generator compared with the first pwm structure it is similar, also may be configured with digital filter.According to the present invention, pass through increasing Add digital filter, may filter that burr signal, so that the PWM into Dead band controller is more stable, more accurate, to improve The stability and precision of PWM output.

Specifically, compare in the first pwm and occur in module, comparison controller is connected with bus, and input has Cntdata0, the cntdata are the output of public counters.In addition, when the output of comparison controller is sent to filtering respectively Clock generator, compares output module, counter register at reference value register.Further, compare in output module not only Input has the direct output-pcr of comparison controller: WMD, also inputs output and the count register for having reference value register The output of device.

Next, the output OP (0) and OP (1) that compare output module (OCO) are separately input into digital filter, dead zone control Device and multiplexer processed.The output filter_pwm0 and filter_pwm1 of digital filter are input to Dead band controller, and The output Dpwm0 and Dpwm1 of Dead band controller are input to multiplexer.In addition, in addition to comparing output mould in digital filter Other than the output OP (0) and OP (1) of block, also input has the output filter_clk for filtering clock generator.

Finally, the first pwm, which compares, occurs the signal that can be output to the outside of module and has: the output reloat_ of digital filter Int, multiplexer output pwm0, pwm1 and compare the output compare_int of output module.

According to the present embodiment, digital filter relatively is being added between output module and Dead band controller, so as to Filter out burr signal so that the PWM into Dead band controller is more stable, more accurate, thus improve the stability of PWM output with And precision.

Also, by multiplexer (Mux), so that pwm is exported, i.e. the more of timer are realized in pwm0, pwm1 diversification Kind function.

Compare generation module, it can be achieved that various counting mode, includes at least dead by the way that pwm is arranged as in the present embodiment Area's control timer filter patterns, dead zone Timer modes and direct mode operation.Can be as needed, switch between each mode, and And without complicated circuit structure.Multi-functional can be realized with better simply structure.

By and large, the present invention filters out burr signal, so that into Dead band controller by increasing digital filter PWM is more stable, more accurate, to improve the stability and precision of PWM output.

1) comparison controller, which can control, compares output module (PWM control&output, abbreviation OCO) respectively for production Raw pwm signal (including OP (0) and OP (1)) is provided respectively to digital filter (filter cnt), Dead band controller (Dead Zone register) or multichannel recombiner (MUX)；

2) in the filtering mode, the PWM letter of output module generation is compared in the output signal PCR:WMD control of comparison controller Number (including OP (0) and OP (1)) gives digital filter (filtercnt), and digital filter (filter cnt) is to the PWM of input Signal is filtered, and obtains filtering signal filter_pwm0 and filtering signal filter_pwm1.Filtering signal filter_pwm0 It exports with filtering signal filter_pwm1 to Dead band controller (Dead zone register), through Dead band controller (Dead Zone register) obtain dead zone function signal Dpwm0, Dpwm1, multichannel recombiner MUX select dead zone function signal Dpwm0, Dpwm1 is as pwm0 and pwm1.It can be found in Figure 11-12 and instructions book about " the dead zone function timer filter patterns " Partial detailed description；

3) preferably, output unit can be compared by comparing controller (comparator control) selection PWM The pwm signal of (PWM control&output), which does not export, gives digital filter (filter cnt), and is directly output to dead zone Controller (Dead zone register) obtains dead zone function signal through Dead band controller (Dead zone register) Dpwm0, Dpwm1, multichannel recombiner Mux select dead zone function signal Dpwm0, Dpwm1 as pwm0 and pwm1；At this point, digital Filter (filter cnt) is used as counter, and exports count signal (reload_int), can export to CPU etc. its Its module increases the diversity and flexibility of system.It can be found in Fig. 9 and its specification portion about " the dead zone Timer modes " Point；

It 4), can be defeated by comparing controller (comparator control) preferably, when not needing dead zone function Signal PCR:WMD control out compares the pwm signal (including OP (0) and OP (1)) of output module generation to multichannel recombiner Mux, Multichannel recombiner mux selects pwm signal (including OP (0) and OP (1)) as pwm0 and pwm1.It can join about " direct mode operation " See Fig. 8 and its instructions book part.

Then, the operation of Multifunctional timer is discussed.As described above, the main modular of Multifunctional timer is roughly divided into meter Number device and pwm compare generation module, therefore the operation of Multifunctional timer is divided into the operation of counter, compares output module Operation, in order to understand the present invention.

1. the operation of counter

Firstly, discussing the operation of counter.In general, including counter control register in counter.

Counter initialization (frequency dividing ratio, count mode) need to be configured when counter stops, and can start counting later Device operates (CNR.STOP=0).

The count value and count status of counter are inputted as output module (OCO) is compared.The operation of OCO and counter are same Step, such as register buffers operation.The operation of OCO is hereinafter described in detail.

When the count value of counter is 0x0000, zero passage detection mark (CNR.IRQZF) position set；Work as counter counts When counting to peak value when (=PSR), peak detection mark (CNR.ICLR) position set.It can set and whether lead to the interrupt signal Know and gives central processing unit (CPU).Can by configure interruption masking counter will wish export interruption (CNR.IRQZF) and (CNR.ICLR) conventional number is reduced.

Following table introduces the function and setting timing of counter control register:

1 counter control register of table

Next, the count mode to counter is illustrated.Approximately, the count mode of counter can be divided into sawtooth Wave mode and triangle wave mode.Under represent the different count modes of counter.

The count mode of 2 counter of table

Illustrate above-mentioned 2 kinds of count modes, that is, (successively decrease meter for sawtooth wave (incremental count) mode or triangular wave Number) mode.

1) sawtooth wave (incremental count) mode

Operation in the case where Fig. 3 shows sawtooth wave pattern.

Sawtooth wave counting operation and control flow are as follows:

Setting pattern CNR.CNTMD=0.

Counts peaks PSR register is set.

CNR.STOP=0 and CNR.CLEAR=1 is written, counter (CIR) is initialized to 0x0000 and starts Counting operation.

Counter Value is started counting up from 0x0000, and when reaching peak value (=PSR), count value returns 0x0000, successively weighs This multiple operation.

Count period=(PSR+1) × counted clock cycle.

In counting process, count value can be initialised to 0x0000 simultaneously by write-in CNR.STOP=0 and CNR.CLEAR=1 Continue counting operation.

Count value can be initialised to 0x0000 and stop counting behaviour by write-in CNR.STOP=1 and CNR.CLEAR=1 Make.

2) triangular wave (incremental countdown) mode

The operation under triangle wave mode is shown in Fig. 4.

Triangular wave counting operation and control flow are as follows:

Setting pattern CNR.CNTMD=1.

Counts peaks PSR register is set.

Counter Value does incremental count counting since 0x0000, does incremental count before reaching counts peaks；When reaching When to peak value (=PSR), counter starts to do countdown, until count value returns 0x0000；Incremental count is re-started later Operation, is repeated in this operation.

Count period=(PSR) × 2 × counted clock cycle.

In counting process, count value can be initialised to 0x0000 simultaneously by write-in CNR.STOP=0 and CNR.CLEAR=1 Incremental count operation is re-started, later repeatedly aforesaid operations.

On the basis of discussing the sawtooth wave count mode and triangular wave count mode of counter, the meter of counter is discussed Number state.Counter values and count status can be with continued reference to Fig. 3 and Fig. 4.Count status and count value will compare as output The input of module (OCO).OCO operation (output signal variation, buffer value load and other operations etc.) is according to the counting of counter State setting.

Count status is defined as follows:

Counter is 0x0000: crossing nought state

Counter is PSR: peak state

Counter does incremental count: propradation

Counter does countdown: decline state.

Followed by discussion interruption masking counter operation.In the counter of present embodiment, screen can be interrupted by configuring Cover counter, it would be desirable to which the interruption (CNR.IRQZF) of output and (CNR.ICLR) conventional number are reduced.

Zero passage detection interruption masking counter is set to precedence for reducing (cover) zero passage detection flag bit (IRQZF) Number.Zero passage detection guarding counter ZIC [3:0] is used as decrement counter operation, is loaded into set by ZIM [3:0] when starting Value, when ZIC [3:0]=" 0 ", zero passage detection flag bit (CNR:IRQZF) is set to " 1 ".

Table 3

ZIM setting value	Explanation
		0	IRQZF is set when every 1 generation count value is " 0x0000 ".(unshielded)
1	IRQZF is set when every 2 generation count values are " 0x0000 ".(shielding 1 time)
		2	IRQZF is set when every 3 generation count values are " 0x0000 ".(shielding 2 times)
...	...
		15	IRQZF is set when every 16 generation count values are " 0x0000 ".(shielding 15 times)

Peak detection interruption masking counter is set number for reducing (cover) peak detection flag bit (ICLR). Peak detection guarding counter (PIC [3:0] is used as decrement counter operation, and value set by PIM [3:0] is loaded into when starting, When PIC [3:0]=" 0 ", peak detection flag bit (CNR:IRQZF) is set to " 1 ".

Table 4

PIM setting value	Explanation
		0	ICLR is set when every 1 generation count value is PSR.(unshielded)
1	ICLR is set when every 2 generation count values are PSR.(shielding 1 time)
		2	ICLR is set when every 3 generation count values are PSR.(shielding 2 times)
...	...
		15	ICLR is set when every 16 generation count values are PSR.(shielding 15 times)

Then, referring to the timing diagram of Fig. 5, the operation of zero passage detection guarding counter is illustrated.Fig. 5

In be exemplarily illustrated the operation of zero passage detection guarding counter.

In Fig. 5, it is followed successively by ZIM [3:0]=0,1 and 2 from top to bottom；Interrupt flag bit under PIM [3:0]=0,1 and 2 Set example (the set moment of ▲ expression flag bit IRQZF and ICLR).

When 1 counter of ▼ stops (STOP=1), ZIM and PIM initialization is written, initial value is immediately reflected at count internal Device (ZIC, PIC).

▼ 2 is initialized and is started counter (STOP=0 and CLEAR=1), and counter is at the beginning of bus reset or from software Start from scratch after beginningization CLEAR=1 and carry out incremental count, this moment IRQZF mark will not set immediately, later whenever interruption masking When the count value of counter is 0x0000 and the count value of counter is 0x0000 and PSR, mark ▲ it is the position IRQZF or ICLR At the time of position.

In counter operation (STOP=0), be written ZIM and PIM, the setting value will not immediate response to interruption masking meter In number device (ZIC and PIC).If be written warm reset (CLEAR=1), ZIM the and PIM value of write-in will be loaded as interrupting screen immediately Cover the initial value of counter.

Another embodiment of interruption masking counter operation is shown in FIG. 6.

For the interrupt flag bit set example under ZIM [3:0]=1 and 2, (▲ expression flag bit IRQZF's is set in Fig. 6 The position moment).

In counter operation (STOP=0), moment ▼ 1 rewrites ZIM 1 → 2.The new value of ZIM is loaded into moment ▼ 2 Reload counter.Interrupt identification IRQZF moment ▼ 3 after change is generated.It is operated in 4 counter O reset CLEAR=1 of moment ▼. ZIM value is re-loaded to ZIM counter, and interrupt identification IRQZF is generated in moment ▼ 5 next time.The moment ▼ 4 in figure, write-in Counter O reset CLEAR=1 operation, counter do incremental count from 0x0000 to 0x0001 again.IRQZF mark will not this moment Set immediately.

When using zero passage detection interruption masking and peak detection interruption masking function at the same time, ZIM and PIM need to be paid special attention to Configuration setting, both is likely to be out of synchronization.

In addition, OCO and A/D converter (ADCT) execute buffer register load operation, converter starting and other behaviour Make the operation with counter interruption masking counter to be consistent.

Next, another important module of the invention is discussed in detail, that is, compare the operation of output.

2. comparing the operation of output

The comparison of another main component as timer exports, and compares the input of output (OCO) and the output of counter It is connected, next, the operation for comparing output module is described in detail, Fig. 7 is the block diagram for comparing output module referring to Fig. 7.

It is observed that Fig. 7 is compared to the more detailed schematic diagram of Fig. 2, Fig. 7 is shown in detail on the basis of Fig. 2 Each control signal.Those of ordinary skill in the art are readily appreciated that the structure of Fig. 7 on the basis of Fig. 2, therefore, omit it specifically It is bright.

Comparing output module includes to compare output module control register.

Comparing output module initialization need to be configured when relatively output module stops (OCE1=OCE0=0), later It can start and compare output module.

The operation of OCO is synchronous with the counting operation of counter (CNT), if register buffers operate, exports M signal OP0/OP1 and output interrupt identification OCF1/OCF0 etc. when the value of counter is matched with the value of output comparator.

The control register functions and setting timing of output module (OCO) are compared in following table introduction:

Table 5 compares output control register

Then, discuss that exporting the channel for comparing Ch.0, Ch.1 is independently arranged condition.The output signal of channel C h.0 be OP0, The output signal of channel C h.1 is OP1.Following table 6 and 7 is the configuration contrast table of example 1-8.

Ch.0 configuration example table is compared in the output of table 6

Then, discuss that output compares the channel Ch.1 and is independently arranged condition.

Identical 12 place value is written to the bit [31:20] and bit [15:4] of (1) register OMR, while by OMR (1) " 0x0000 " is written in [19:16], at this time the change condition of channel C OP1 signal h.1 and OCF1 configuration is upper and OCR (0) and OCR (1) is consistent.Therefore it is unrelated with OCR (0) configuration to may be regarded as the operation of channel C h.1, this mode is called channel independent operation Mode ----channel C h (0) is determined that channel C h (1) determines configuration by OCR (1) by OCR (0).If not being able to satisfy the condition, lead to The variation of road Ch.1 will be related to OCR (0), call it as channel link operation mode.

Ch.1 configuration example table is compared in the output of table 7

Further, channel link operation mode is discussed.

Under linked operation mode, two fiducial value OCR (0) and OCR (1) are defeated for controlling the internal signal OP1 of Ch.1 Out.The OP0 control that Ch.0 is read under linked operation mode is invalid.

Channel C can be respectively set h.0 with the buffer register transmission time of Ch.1, for example count value can be set and be OCR (0) value of Ch.0 is transmitted when 0x0000, and OCR (1) value of Ch.1 is transmitted when counter is peak value (=PSR).

When OCR (0) is matched with Counter Value, the OCF1 interrupt identification of Ch.1 will not be generated.If you need to generate OCR (0) with Counter Value matches the OPF0 interrupt identification of lower Ch.0, and it is enabled mode of operation (OCE0=1) that channel C, which need to be arranged, h.0.If only The output for needing to generate OP1, without OP0 and OCF0, then channel C need not be arranged h.0 is enabled mode of operation (OCE0= 1)。

Ch.0 and Ch.1 linked operation pattern configurations sample table is compared in the output of table 8

Below, direct mode operation is discussed, that is, directly export the mode of OP (0) and OP (1).Under direct mode operation, pwm signal (including OP (0) and OP (1)) is directly passed to source node A or B).

It is as described below that PWM exports direct mode operation (PCR:WMD [1:0]=00) operation:

Under direct mode operation, OP (0) is by the way that outside PWM0 pin output chip, OP (1) is output to outside piece by PWM1 pin.

Fig. 8 shows output waveform of the PWM under direct mode operation.In Fig. 8, OP0 and OP1 believe respectively as output is relatively more internal It number is directly output to outside chip without processing.

Next dead zone Timer modes are discussed, i.e., without the mode of filtering, digital filter is as just counter It uses.Fig. 9 is the dead zone Timer modes waveform example 1 of output channel Ch10.The dead zone timing that Figure 10 is output channel Ch10 Device mode waveform example 2.

It is as described below that PWM exports dead zone Timer modes (PCR:WMD [1:0]=01) operation:

Under the Timer modes of dead zone, dead time is set separately according to prime OP (1) signal and by register PDA and PDB, Generate not overlapping PWM (1) and PWM (0) output signal.

It is high internal signal OP (1) that Timer modes agreement in dead zone, which compares output to generate significant level,.Under this mode, if Set PFR register and OP (0) invalidating signal.

When setting mode as dead zone Timer modes by rewriting PCR:WMD [1:0] register, output signal PWM (0) Polarity it is identical as OP1, the polarity of output signal PWM (1) is opposite with OP1.

If detecting signal OP (1) rising edge, PWM (1) output becomes low level；Dead zone counter loads PDB deposit The setting value of device simultaneously starts countdown, and when count value becomes 0x0000, counter stops and PWM (0) is made to export high level.

If detecting signal OP (1) failing edge, PWM (0) output becomes low level；Dead zone counter loads PDA deposit The setting value of device simultaneously starts countdown, and when count value becomes 0x0000, counter stops and PWM (1) is made to export high level.

By the way that dead time register PDA and PDB is arranged, the dead time of output raising and lowering variation can accordingly be set It is fixed.

Fig. 9 is the dead zone Timer modes waveform example 1 of output channel Ch10.The dead zone that Figure 10 is output channel Ch10 is fixed When device mode waveform example 2.

When the high-level pulse width of signal OP1 is less than the dead time of PDB setting, only PWM (1) output becomes low electricity It is flat.PWM (1) output level become high condition be pass through after OP1 failing edge PDA register setting dead time it Afterwards.In the case, output PWM (0) will remain continuously low level.

When the low level pulse width of signal OP1 is less than the dead time of PDA setting, only PWM (0) output becomes low electricity It is flat.PWM (0) output level become high condition be pass through after OP1 rising edge PDB register setting dead time it Afterwards.In the case, output PWM (1) will remain continuously low level.

Next, being illustrated to dead zone timer filter patterns.It may be simply referred to as filter patterns, digital filter is to PWM The mode being filtered.Figure 11 is output dead zone timer filter patterns waveform example 1.Figure 12 is output dead zone timer filtering Mode waveform example 2.

It is as described below that PWM exports dead zone timer filter patterns (PCR:WMD [1:0]=10) operation:

First with digital filter, which is less than filtered width for pulse width and (is set by register PFR (making it not influences last PWM output) is fallen in OP (1) signal phagocytosis calmly).

When the pulse width of OP1 is greater than the time of register PFR setting, digital filter sets OP1 signal postponement PFR It is exported after the fixed time, then goes to generate PWM (1) and PWM (0) output by mode described in the Timer modes of front dead zone. It is high internal signal OP (1) that this mode agreement, which compares output to generate significant level,.

If detecting signal OP (1) rising edge, digital filter load PFR register value simultaneously starts metering signal OP1 High level width, when the high-level pulse width of OP1 be greater than register PFR setting time when, by fixing time set by PFR Later, PWM (1) output becomes low level；The setting value of dead zone counter load PDB register simultaneously starts countdown, works as meter When numerical value becomes 0x0000, counter stops and PWM (0) is made to export high level.

If detecting signal OP (1) failing edge, digital filter load PFR register value simultaneously starts metering signal OP1 Low level width, when the low level pulse width of OP1 be greater than register PFR setting time when, by fixing time set by PFR Later, PWM (0) output becomes low level；The setting value of dead zone counter load PDA register simultaneously starts countdown, works as meter When numerical value becomes 0x0000, counter stops and PWM (1) is made to export high level.

When the level pulse widths of OP1 are less than the time of register PFR setting, exporting PWM (0) and PWM (1) will be kept It is constant.

Figure 11 is output dead zone timer filter patterns waveform example 1.Figure 12 is output dead zone timer filter patterns wave Shape example 2.

When the pulse width of OP1 be less than PFR setting time when, OP1 signal is filtered, output signal PWM (0) and PWM (1) does not change.When meeting condition PFR10 >=PDA10 and PFR10 >=PDB10, output signal PWM (0) and PWM (1) can change according to shown in Figure 12.

Then, the overturning of output polarity is discussed.

The polarity that PCR.LVLS [1:0] exports for changing PWM0/PWM1.

When the polarity of PCR.LVLS [1:0]=00, PWM0 and PWM1 is constant；

When the polarity of PCR.LVLS [1:0]=01, PWM0 and PWM1 is all overturn

When PCR.LVLS [1:0]=10, PWM0 polarity upset, the polarity of PWM1 is constant.

When PCR.LVLS [1:0]=11, PWM1 polarity upset, the polarity of PWM0 is constant.

By applying Multifunctional timer of the invention, not only the output of PWM can be made more stable, PWM also can be improved Precision, and realize emergency brake signal stabilization reduce serious forgiveness.The present invention cannot be only used for the control of three-phase motor, not do In the case where material alteration, it is possibly used for the motor control of other modes, is not necessarily limited to three-phase motor.

Some exemplary embodiments are described above.It should be understood, however, that various modifications may be made.Example Such as, if described technology is executed in different order and/or if in described system, framework, equipment or circuit Component is combined and/or substituted or supplemented by other component or its equivalent in different ways, then may be implemented suitably to tie Fruit.Correspondingly, other embodiments are also fallen into scope of protection of the claims.

Claims

It, should including counter and the PWM trigger being connected with counter 1. a kind of Multifunctional timer is used for motor control PWM trigger includes that at least one pwm compares generation module, which is characterized in that

Pwm compares generation module

The comparison controller being connected with counter；

By the output of comparison controller filtering clock generator as input, reference value register, compare output Module and counter register；

By the output digital filter as input of the filtering clock generator and the relatively output module；

By the output Dead band controller as input of the relatively output module and the digital filter；And

By the output multiplexer as input of the relatively output module and the Dead band controller.
2. Multifunctional timer as described in claim 1, which is characterized in that by the output signal of the comparison controller, The timer switches between multiple modes.
3. Multifunctional timer as claimed in claim 2, which is characterized in that the multiple mode is filtered comprising dead zone timer At least one of mode, dead zone Timer modes and direct mode operation.
4. Multifunctional timer as claimed in claim 3, which is characterized in that described relatively to control under the filter patterns The output signal of device exports the pwm signal that output module generates described relatively to the digital filter, in the number filter Wave device exports after being filtered to the Dead band controller；Under the dead zone Timer modes, the comparison controller it is defeated Signal does not export the signal that output module generates described relatively to the digital filter out, but is directly output to described Dead band controller；Under the direct mode operation, the signal that the comparison controller generates the relatively output module is directly defeated Out to the multiplexer, without exporting to the digital filter and the Dead band controller.
5. Multifunctional timer as claimed in claim 4, which is characterized in that under the dead zone Timer modes, the number Word filter is used as counter, output count signal to CPU.
6. a kind of method for generating PWM output, the count value that counter generates is exported to PWM trigger in the method Device, the PWM trigger include that at least one pwm compares generation module, compare generation module by the pwm and proceed as follows:

The output of counter is input to comparison controller；

By the output of comparison controller be input to filtering clock generator, reference value register, compare output module and Counter register；

The output of the filtering clock generator and the relatively output module is input to digital filter；

The output of the relatively output module and the digital filter is input to Dead band controller；And

The output of the relatively output module and the Dead band controller is input to multiplexer.
7. the method as claimed in claim 6 for generating PWM output, which is characterized in that pass through the comparison controller Output, the timer switch between multiple modes.
8. the method as claimed in claim 7 for generating PWM output, which is characterized in that the multiple mode includes dead zone At least one of timer filter patterns, dead zone Timer modes and direct mode operation；Under the filter patterns, the ratio The pwm signal that output module generates described relatively is exported to the digital filter, described compared with the output signal of controller Digital filter exports after being filtered to the Dead band controller；It is described relatively to control under the dead zone Timer modes The output signal of device does not export the signal that output module generates described relatively to the digital filter, but directly exports To the Dead band controller；Under the direct mode operation, the comparison controller by it is described relatively output module generate signal It is directly output to the multiplexer, without exporting to the digital filter and the Dead band controller.
9. as claimed in claim 8 for generating the method device of PWM output, which is characterized in that in the dead zone timer mould Under formula, the digital filter is used as counter, output count signal to CPU.
10. a kind of storage medium is stored with and is executed on the computing device to realize described in any one of claim 6-9 The instruction of method.