CN110224028B - VDMOS device with L-type dielectric layer and low EMI - Google Patents
VDMOS device with L-type dielectric layer and low EMI Download PDFInfo
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- CN110224028B CN110224028B CN201910410173.3A CN201910410173A CN110224028B CN 110224028 B CN110224028 B CN 110224028B CN 201910410173 A CN201910410173 A CN 201910410173A CN 110224028 B CN110224028 B CN 110224028B
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- 238000010521 absorption reaction Methods 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 208000032365 Electromagnetic interference Diseases 0.000 description 12
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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Abstract
The invention provides a VDMOS device with an L-shaped dielectric layer and low EMI, which comprises a VDMOS primitive cell structure, wherein the VDMOS primitive cell structure comprises a drain end metal electrode and a source electrode metal electrode, RC absorption circuits are arranged on two sides of the VDMOS primitive cell structure and comprise resistors and capacitors which are connected in series, one end of each RC absorption circuit is coupled with the source electrode metal electrode, and the other end of each RC absorption circuit is coupled with the drain end metal electrode. The invention effectively reduces the switching loss and electromagnetic interference of the VDMOS device and improves the integration level of the applied circuit on the basis of ensuring the original basic electrical performance of the VDMOS.
Description
Technical Field
The invention relates to a VDMOS (vertical double-diffused metal oxide semiconductor) device with an L-shaped dielectric layer and low EMI (electro-magnetic interference), in particular to a low-EMIVDMOS device with an internal integrated RC (resistance-capacitance) absorption circuit, and belongs to the technical field of electronics.
Background
In a switching power supply topology including a transformer, when a switching tube is turned off, loss caused by overlapping of voltage and current is a main part of the loss of the switching power supply, and meanwhile, due to the existence of stray inductance and stray capacitance in a circuit, when a power device is turned off, overshoot voltage occurs in the circuit and oscillation is generated, so that serious Electromagnetic Interference (EMI) is caused to the outside. If the peak voltage is too high, the power device may be damaged. At the same time, the presence of oscillations also increases the output ripple. In order to reduce turn-off loss and spike voltage, it is necessary to connect an absorption circuit in parallel across the power device to improve the performance of the circuit.
The RC snubber circuit is a classic snubber circuit used to reduce the voltage spikes caused by the inductance in the circuit when the power device is switched. In the prior art, no scheme for integrating an RC absorption circuit into a VDMOS device exists.
Disclosure of Invention
The invention aims to solve the technical problem of how to reduce the switching loss and electromagnetic interference of a VDMOS device and realize a high-integration switching power supply, so that the invention provides the VDMOS device with an L-shaped dielectric layer and low EMI.
The invention provides a VDMOS device with an L-shaped dielectric layer and low EMI (electro-magnetic interference), which comprises a VDMOS primitive cell structure, wherein the VDMOS primitive cell structure comprises a drain end metal electrode and a source electrode metal electrode, RC absorption circuits are arranged on two sides of the VDMOS primitive cell structure and comprise resistors and capacitors which are connected in series, one end of each RC absorption circuit is coupled with the source electrode metal electrode, and the other end of each RC absorption circuit is coupled with the drain end metal electrode.
As a further technical solution of the present invention, the RC absorption circuit includes an L-shaped dielectric layer, the L-shaped dielectric layer and the source metal electrode form a semi-surrounding region with an opening deviating from the VDMOS cell structure, and the resistor is disposed in the semi-surrounding region.
Furthermore, the resistor comprises a first N-type heavily doped region, an N-type lightly doped region and a second N-type heavily doped region which are sequentially arranged.
Furthermore, the VDMOS primitive cell structure further comprises a drain end N-type heavily doped active region and an N-type lightly doped drift region, wherein the drain end N-type heavily doped active region is arranged above the drain end metal electrode, and the N-type lightly doped drift region is arranged above the drain end N-type heavily doped active region.
Further, the N-type lightly doped drift region forms a lower polar plate of the capacitor, the first N-type heavily doped region forms an upper polar plate of the capacitor, and the horizontal edge of the L-type dielectric layer is arranged between the N-type lightly doped drift region and the first N-type heavily doped region.
Furthermore, a third N-type heavily doped region is further arranged in the N-type lightly doped drift region, the third N-type heavily doped region is arranged below the horizontal edge of the L-type dielectric layer, and the third N-type heavily doped region and the N-type lightly doped drift region jointly form a lower plate of the capacitor.
Furthermore, the VDMOS cell structure further includes two source well regions symmetrically disposed on two sides of the upper end of the N-type lightly doped drift region, the source well region is P-type lightly doped, and a fourth N-type heavily doped region and a P-type heavily doped region are disposed above the source well region.
Furthermore, the side surfaces of the first N-type heavily doped region, the N-type lightly doped region and the second N-type heavily doped region are isolated from the source well region and the P heavily doped region through the L-type dielectric layer.
Furthermore, grid silicon dioxide covers the upper end face of the N-type lightly doped drift region, and a grid polycrystalline silicon electrode is arranged on the grid silicon dioxide.
Furthermore, the L-shaped dielectric layer is made of silicon dioxide, and the lower boundary of the L-shaped dielectric layer is flush with the lower boundary of the source well region.
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
1. the invention obviously reduces EMI on the basis of basically not damaging the electrical characteristics of the VDMOS, has simple structure and is beneficial to the realization of the prior art.
2. The RC absorption circuit is integrated in the device, so that the complexity of a peripheral circuit is reduced, the integration level of a switching power supply circuit is improved, and the circuit volume is reduced;
3. the specific parameter values of the internal integrated RC absorption circuit used by the invention can be directly adjusted through the area size and the doping concentration, so that different target scenes can be conveniently and independently designed;
4. the third N-type heavily doped region is added to form a capacitor lower polar plate, and the resistance value of the capacitor lower polar plate is lower, so that a fluctuation signal of a drain end can be more easily guided to the capacitor lower polar plate, the capacitance can be increased, and the effect of enhancing the coupling strength is achieved.
5. The characteristics of the internal integrated RC absorption circuit used by the invention, such as process, temperature and the like, change together with the power transistor, the RC absorption circuit has the capability of self-adapting to the change of electrical parameters of the VDMOS to a certain extent, and meanwhile, the influence of package parasitic parameters on the performance of the absorption circuit is reduced.
Drawings
FIG. 1: a schematic diagram of a conventional VDMOS structure in the prior art;
FIG. 2: the structure of the embodiment of the invention is shown schematically;
FIG. 3: an equivalent circuit diagram of an embodiment of the invention.
Wherein: 101. a drain terminal metal electrode; 102. a drain end N-type heavily doped active region; 103. n-type lightly doped drift region: 104. a source well region; 105. silicon dioxide of grid electrode; 106. a fourth N-type heavily doped region; 107. a P-type heavily doped region; 108. a source metal electrode; 109. a gate polysilicon electrode; 110. a third N-type heavily doped region; 111. an L-shaped dielectric layer; 112. a first N-type heavily doped region; 113. an N-type lightly doped region; 114. and a second N-type heavily doped region.
Detailed Description
The technical scheme of the invention is further explained in detail by combining the attached drawings:
in the prior art, a VDMOS primitive cell structure generally includes a drain metal electrode 101, a drain N-type heavily doped active region 102 is disposed above the drain metal electrode 101, an N-type lightly doped drift region 103 is disposed above the drain N-type heavily doped active region 102, two source well regions 104 are symmetrically distributed on the left and right of the upper end of the N-type lightly doped drift region, a gate silicon dioxide 105 covers the upper end surface of the drift region, the whole source well region 104 is lightly doped P-type, a fourth N-type heavily doped region 106 and a P-type heavily doped region 107 are disposed above the source well regions, a part of a region above the source well region 104 is covered with the gate silicon dioxide 105, a source metal electrode 108 and a gate silicon dioxide 105 cover the fourth N-type heavily doped region 106, a source metal electrode 108 covers the P-type heavily doped region, and a gate polysilicon electrode 109 is disposed above the gate silicon dioxide, as shown in fig. 1.
The RC absorption circuits are respectively arranged on the left side and the right side of the structure, the RC absorption circuits are connected to the source and the drain of the VDMOS in parallel, at the moment of switching the VDMOS, the capacitor in the RC absorption circuits can be regarded as a short circuit, the resistor is connected to the two sides of an LC resonant cavity formed by the Cds capacitor of the VDMOS and the load leakage inductance L in parallel, and the resistor can remarkably reduce the Q value of the LC resonant cavity, so that the resonance between the LCs is effectively inhibited; after the resonance is over, the capacitor can be regarded as an open circuit, no current flows through the RC absorption circuit, and the RC circuit is equivalently closed. The integrated RC absorption circuit can only act when the VDMOS is switched on and off, and the RC absorption circuit is automatically closed under the conduction state of the VDMOS, so that other electrical characteristics of the VDMOS are not influenced.
Specifically, the RC absorption circuit includes a resistor and a capacitor connected in series, the capacitor is formed by the third heavily doped N-type region 110, the heavily doped N-type region 112, and the L-type dielectric layer 111, and in this embodiment, the material of the L-type dielectric layer 111 is silicon dioxide. The third N-type heavily doped region 110 is added to form a capacitor lower plate, so that the resistance value is low, the fluctuation signal of the drain end can be more easily guided to the capacitor lower plate, the capacitance can be increased, the signal can flow through more easily, and the effect of enhancing the coupling strength is achieved. It should be noted that the area of the third heavily N-doped region 110 cannot be too large and too close to the source well region 104, which would cause a reduction in breakdown voltage.
The resistor is formed by connecting a first N-type heavily doped region 112, an N-type lightly doped region 113 and a second N-type heavily doped region 114 in series, the lower boundary of an L-type dielectric layer 111 covered above a third N-type heavily doped region 110 is flush with the lower boundary of a source well region 104, the first N-type heavily doped region 112 is arranged above the L-type dielectric layer 111, the N-type lightly doped region 113 is arranged above the N-type heavily doped region 112, the second N-type heavily doped region 114 is arranged above the N-type lightly doped region 113, source metal 108 is covered above the second N-type heavily doped region 114, and the side faces of the first N-type heavily doped region 112, the N-type lightly doped region 113 and the second N-type heavily doped region 114 are isolated from the source well region 104 and a P-type heavily doped region 107 above the source well region through the L-type dielectric layer 111.
Compared with the conventional VDMOS device, the invention has the innovation points that: the conventional VDMOS structure is additionally integrated with a coupling path, wherein the coupling path is a drain metal electrode 101 → a drain N-type heavily doped active region 102 → an N-type lightly doped drift region 103 → a third N-type heavily doped region 110 → an L-type dielectric layer 111 → a first N-type heavily doped region 112 → an N-type lightly doped region 113 → a second N-type heavily doped region 114 → a source metal 108, and the coupling path is mainly used for coupling the voltage jitter of the drain 101 to the source 108, so that the voltage jitter of the drain 101 is reduced, and the EMI generated by the device is reduced. The equivalent circuit diagram of the coupling path is shown in fig. 3.
The VDMOS device with the L-shaped dielectric layer and low EMI is characterized in that an RC absorption circuit is integrated in the VDMOS device, the EMI is reduced under the condition that basic electrical characteristics are almost unchanged, and only a small part of parasitic capacitance is increased, so that high integration, low switching loss and low EMI are realized.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein, and any reference signs in the claims are not intended to be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can understand that the modifications or substitutions within the technical scope of the present invention are included in the scope of the present invention, and therefore, the scope of the present invention should be subject to the protection scope of the claims.
Claims (6)
1. A VDMOS device with L-shaped dielectric layer and low EMI comprises a VDMOS cell structure, wherein the VDMOS cell structure comprises a drain metal electrode (101) and a source metal electrode (108), and is characterized in that: RC absorption circuits are arranged on two sides of the VDMOS primitive cell structure and comprise resistors and capacitors which are connected in series, one end of each RC absorption circuit is coupled with the source electrode metal electrode (108), and the other end of each RC absorption circuit is coupled with the drain electrode metal electrode (101);
the RC absorption circuit comprises an L-shaped dielectric layer (111), a semi-surrounding area with an opening deviating from the VDMOS primitive cell structure is formed by the L-shaped dielectric layer (111) and the source metal electrode (108), and the resistor is arranged in the semi-surrounding area;
the resistor comprises a first N-type heavily doped region (112), an N-type lightly doped region (113) and a second N-type heavily doped region (114) which are sequentially arranged;
the VDMOS primitive cell structure further comprises a drain end N-type heavily doped active region (102) and an N-type lightly doped drift region (103), wherein the drain end N-type heavily doped active region (102) is arranged above the drain end metal electrode (101), and the N-type lightly doped drift region (103) is arranged above the drain end N-type heavily doped active region (102);
the N-type lightly doped drift region (103) forms a lower polar plate of the capacitor, the first N-type heavily doped region (112) forms an upper polar plate of the capacitor, and the horizontal edge of the L-type dielectric layer (111) is arranged between the N-type lightly doped drift region (103) and the first N-type heavily doped region (112).
2. The VDMOS device with L-type dielectric layer and low EMI as claimed in claim 1, wherein: the N-type lightly doped drift region is also internally provided with a third N-type heavily doped region (110), the third N-type heavily doped region (110) is arranged below the horizontal edge of the L-type dielectric layer (111), and the third N-type heavily doped region (110) and the N-type lightly doped drift region (103) jointly form a lower polar plate of the capacitor.
3. The VDMOS device with L-type dielectric layer and low EMI as claimed in claim 2, wherein: the VDMOS primary cell structure further comprises two source electrode well regions (104), the two source electrode well regions (104) are symmetrically arranged on two sides of the upper end of the N-type light doping drift region (103), the source electrode well regions (104) are in P-type light doping, and a fourth N-type heavy doping region (106) and a P-type heavy doping region (107) are arranged above the source electrode well regions (104).
4. The VDMOS device with L-type dielectric layer and low EMI as claimed in claim 3, wherein: the side surfaces of the first N-type heavily doped region (112), the N-type lightly doped region (113) and the second N-type heavily doped region (114) are isolated from the source well region (104) and the P-type heavily doped region (107) through the L-type dielectric layer (111).
5. The VDMOS device with L-type dielectric layer and low EMI as claimed in claim 4, wherein: the upper end face of the N-type lightly doped drift region (103) is covered with grid silicon dioxide (105), and a grid polycrystalline silicon electrode (109) is arranged on the grid silicon dioxide (105).
6. The VDMOS device with L-shaped dielectric layer and low EMI as claimed in claim 5, wherein: the L-shaped dielectric layer (111) is made of silicon dioxide, and the lower boundary of the L-shaped dielectric layer (111) is flush with the lower boundary of the source well region (104).
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| CN201910410173.3A CN110224028B (en) | 2019-05-17 | 2019-05-17 | VDMOS device with L-type dielectric layer and low EMI |
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| CN201910410173.3A CN110224028B (en) | 2019-05-17 | 2019-05-17 | VDMOS device with L-type dielectric layer and low EMI |
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| CN110224028B true CN110224028B (en) | 2022-06-17 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111244153B (en) * | 2020-01-16 | 2021-02-12 | 电子科技大学 | anti-EMI super junction device |
| CN111244179B (en) * | 2020-01-16 | 2021-02-12 | 电子科技大学 | anti-EMI super-junction VDMOS device |
| CN111244180B (en) * | 2020-01-16 | 2021-01-22 | 电子科技大学 | Super-junction VDMOS device with improved dynamic characteristics |
| CN112002686A (en) * | 2020-09-30 | 2020-11-27 | 深圳市威兆半导体有限公司 | anti-EMI SGT device |
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| CN101582426A (en) * | 2009-06-02 | 2009-11-18 | 北京大学 | Capless DRAM unit and preparation method thereof |
| CN107275402A (en) * | 2017-03-31 | 2017-10-20 | 成都芯源系统有限公司 | Semiconductor device and method for manufacturing the same |
| CN108831927A (en) * | 2018-06-12 | 2018-11-16 | 北京世港晟华科技有限公司 | Super-junction metal oxide semiconductor field effect transistor and its manufacturing method |
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|---|---|---|---|---|
| CN101582426A (en) * | 2009-06-02 | 2009-11-18 | 北京大学 | Capless DRAM unit and preparation method thereof |
| CN107275402A (en) * | 2017-03-31 | 2017-10-20 | 成都芯源系统有限公司 | Semiconductor device and method for manufacturing the same |
| CN108831927A (en) * | 2018-06-12 | 2018-11-16 | 北京世港晟华科技有限公司 | Super-junction metal oxide semiconductor field effect transistor and its manufacturing method |
Non-Patent Citations (1)
| Title |
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| Design Optimal Built-in Snubber in Trench Field Plate Power MOSFET for Superior EMI and Efficiency Performance;Jingjing Chen;《SISPAD》;20150911;第460页左栏第1-3段及图1 * |
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