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CN110164879A - Array substrate, display device - Google Patents

Array substrate, display device Download PDF

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Publication number
CN110164879A
CN110164879A CN201910596078.7A CN201910596078A CN110164879A CN 110164879 A CN110164879 A CN 110164879A CN 201910596078 A CN201910596078 A CN 201910596078A CN 110164879 A CN110164879 A CN 110164879A
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CN
China
Prior art keywords
binding portion
substrate
insulating layer
array substrate
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910596078.7A
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Chinese (zh)
Other versions
CN110164879B (en
Inventor
孙世成
郭钟旭
张伟
王培�
司晓文
李存智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chongqing Jingdong Display Technology Co Ltd
BOE Technology Group Co Ltd
Original Assignee
Chongqing Jingdong Display Technology Co Ltd
BOE Technology Group Co Ltd
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Filing date
Publication date
Application filed by Chongqing Jingdong Display Technology Co Ltd, BOE Technology Group Co Ltd filed Critical Chongqing Jingdong Display Technology Co Ltd
Priority to CN201910596078.7A priority Critical patent/CN110164879B/en
Publication of CN110164879A publication Critical patent/CN110164879A/en
Application granted granted Critical
Publication of CN110164879B publication Critical patent/CN110164879B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The present invention provides a kind of array substrate, display device, is related to field of display technology, for solving the problems, such as that driving chip and the overlap resistance in binding portion are larger.Array substrate includes: substrate；At least one signal lead, signal lead is arranged on substrate, and is located at least in signal transmission range；First insulating layer is arranged in signal line leads far from one side of substrate；At least one first via hole is provided on first insulating layer；At least one binding portion is arranged in the first insulating layer far from one side of substrate, and each binding portion is electrically connected by the first via hole with a signal line lead；Binding portion is located at least in signal converting area；Surface of the binding portion far from substrate is arranged in second insulating layer, and the orthographic projection of second insulating layer on substrate is located in the orthographic projection of binding portion on substrate, and the part being electrically connected in second insulating layer covering binding portion with signal lead.

Description

Array substrate, display device
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrates, display device.
Background technique
Array substrate is the indispensable a part of display device, and array substrate generally includes viewing area and is set to display The binding area of area side.
Viewing area is used to be arranged the pixel circuit of multiple array arrangements, binds area for realizing the pixel electricity in array substrate Binding between road and driving chip, to realize that the signal between driving chip and pixel circuit transmits.
Binding area includes signal transmission range and signal converting area, and signal transmission range is provided with signal lead, signal converting Area is provided with binding portion, and signal lead is correspondingly connected with binding portion, is realized between array substrate and driving chip based on binding portion Binding.
Wherein, the connection effect in driving chip and binding portion will have a direct impact on the yield of binding, if driving chip with tie up The overlap resistance for determining portion is excessive, is easy to appear and shows bad problem.
Summary of the invention
The embodiment of the present invention provides a kind of array substrate, display device, for solving taking for driving chip and binding portion The larger problem of connecting resistance.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
In a first aspect, a kind of array substrate is provided, it is described including viewing area and positioned at the binding area of the viewing area side Binding area includes signal converting area and the signal transmission range positioned at the signal converting area at least side；The array substrate packet It includes: substrate；At least one signal lead, the signal lead setting over the substrate, and are located at least in the signal transmission Area；First insulating layer is arranged in the signal line leads far from the one side of substrate；It is provided at least on first insulating layer One the first via hole；At least one binding portion is arranged in first insulating layer far from the one side of substrate, and each described ties up Determine portion and is electrically connected by first via hole with the signal line leads；The binding portion is located at least in the signal converting Area；Second insulating layer, be arranged in the surface of the binding portion far from the substrate, and the second insulating layer is over the substrate Orthographic projection is located in the orthographic projection of the binding portion over the substrate, and the second insulating layer cover in the binding portion with The part of the signal lead electrical connection.
Optionally, the second insulating layer only covers the part being electrically connected in the binding portion with the signal lead.
Optionally, the array substrate further includes that the auxiliary on surface of the second insulating layer far from the substrate is arranged in Conductive layer；The orthographic projection of the second insulating layer over the substrate is located at the positive throwing of the auxiliary conductive layer over the substrate In shadow.
Optionally, the array substrate further includes the electrode layer positioned at the viewing area；The auxiliary conductive layer with it is described The same material of electrode layer same layer.
Optionally, the aperture of first via hole is 2~4um.
Optionally, the binding portion extends to the signal transmission range, and first via hole is located at the signal transmission range； The second insulating layer covers the part for being located at the signal transmission range in the binding portion.
Optionally, the aperture of first via hole is greater than the half of size of the signal transmission range along first direction；Its In, the first direction is the direction of routing of the signal lead.
Optionally, the array substrate further includes the thin film transistor (TFT) of setting over the substrate；The thin film transistor (TFT) Including source-drain electrode layer and the interlayer insulating film of the source-drain electrode layer far from the one side of substrate is set；Second insulation Layer and the same material of interlayer insulating film same layer.
Optionally, in the case where first via hole is located at the signal transmission range, the second insulating layer with it is described Interlayer insulating film is structure as a whole.
Optionally, the array substrate further includes the first signal wire and second signal line, and the second signal line setting exists First signal wire is far from the one side of substrate；The signal lead and the same material of the first signal wire same layer, it is described to tie up Determine portion and the same material of second signal line same layer；First signal wire and the second signal line grid line and data each other Line.
Second aspect provides a kind of display device, including driving chip and the described in any item array substrates of first aspect； The driving chip is electrically connected with the binding portion in the array substrate.
Array substrate that the embodiment of the present invention provides, display device, by binding portion far from one side of substrate setting the Two insulating layers, and second insulating layer is made to cover clinch, it can play a protective role to clinch.It avoids in subsequent preparation process Damage is generated to clinch, causes resistance excessive.Further, since positioned at the part not quilt completely in signal converting area in binding portion Second insulating layer covering.Therefore, driving chip is not influenced and binding portion is bound.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with It obtains other drawings based on these drawings.
Fig. 1 is a kind of block schematic illustration of display device provided by the embodiments of the present application；
Fig. 2 is a kind of pixel map of display screen provided by the embodiments of the present application；
Fig. 3 a is a kind of structural schematic diagram of display module provided by the embodiments of the present application；
Fig. 3 b is the structural schematic diagram of another display module provided by the embodiments of the present application；
Fig. 3 c is the structural schematic diagram of pixel circuit in a kind of array substrate provided by the embodiments of the present application；
Fig. 3 d is a kind of structural schematic diagram of display screen provided by the embodiments of the present application；
Fig. 4 a is the structural schematic diagram of another display module provided by the embodiments of the present application；
Fig. 4 b is the structural schematic diagram of another display module provided by the embodiments of the present application；
Fig. 4 c is the structural schematic diagram of pixel circuit in a kind of array substrate provided by the embodiments of the present application；
Fig. 4 d is the structural schematic diagram of another display screen provided by the embodiments of the present application；
Fig. 5 a is a kind of schematic top plan view of display device provided by the embodiments of the present application；
Fig. 5 b is the structural schematic diagram of a kind of driving circuit provided by the embodiments of the present application and array substrate binding；
Fig. 5 c is the structural schematic diagram of another driving circuit and array substrate binding provided by the embodiments of the present application；
Fig. 6 a is the schematic top plan view of another display device provided by the embodiments of the present application；
Fig. 6 b is the schematic top plan view of another display device provided by the embodiments of the present application；
Fig. 7 a is a kind of structural schematic diagram for binding area provided by the embodiments of the present application；
Fig. 7 b is the structural schematic diagram in another binding area provided by the embodiments of the present application；
Fig. 8 a is a kind of schematic top plan view for binding area provided by the embodiments of the present application；
Fig. 8 b is the schematic top plan view in another binding area provided by the embodiments of the present application；
Fig. 9 is the structural schematic diagram in another binding area provided by the embodiments of the present application；
Figure 10 is the structural schematic diagram in another binding area provided by the embodiments of the present application；
Figure 11 is the structural schematic diagram in another binding area provided by the embodiments of the present application；
Figure 12 is the structural schematic diagram in another binding area provided by the embodiments of the present application；
Figure 13 is the structural schematic diagram in another binding area provided by the embodiments of the present application；
Figure 14 is the structural schematic diagram in another binding area provided by the embodiments of the present application；
Figure 15 is the structural schematic diagram in binding portion provided by the embodiments of the present application and driving chip binding；
Figure 16 is the structural schematic diagram in another binding area provided by the embodiments of the present application.
Appended drawing reference:
01- display device；10- display module；101- display screen；107- grid；108- gate insulation layer；109- active layer； 110- source-drain electrode layer；1010- sub-pixel；1011- array substrate；10111- pixel circuit；10112- signal wire；10113- picture Plain electrode；10114- public electrode；10115- interlayer insulating film；1012- counter substrate；10121- chromatic filter layer；1013- liquid Crystal layer；1014- sealant；1016- luminescent device；1017- encapsulated layer；The first polarization layer of 102-；The second polarization layer of 103-；104- Backlight module；105- third polarization layer；106- driving chip；11- center；12- shell；13- cover board；20- substrate；21- signal Lead；The first insulating layer of 22-；The first via hole of 221-；222- groups of vias；23- binding portion；231- clinch；24- second insulate Layer；25- buffer layer.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.
Term " first " used in present specification and claims, " second " and similar word are not It indicates any sequence, quantity or importance, and is used only to distinguish different component parts.Define as a result, " first ", The feature of " second " can explicitly or implicitly include one or more of the features.In the description of the embodiment of the present application In, unless otherwise indicated, the meaning of " plurality " is two or more.
The directional terminologies such as "left", "right", "upper" and "lower" are the sides placed relative to the display device signal in attached drawing Position defines, it should be understood that, these directional terminologies are opposite concepts, they be used for relative to description and clarification, The variation in its orientation that can be placed according to the display device and correspondingly change.
The embodiment of the present application provides a kind of display device 01 as shown in Figure 1.The display device 01 includes such as mobile phone, puts down Plate computer, personal digital assistant (personal digital assistant, PDA), vehicle-mounted computer etc..The embodiment of the present application pair The concrete form of above-mentioned display device 01 does not do specifically limited.It below for convenience of explanation, is to be for mobile phone with display device 01 The explanation that example carries out.
Above-mentioned display device 01, as shown in Figure 1, mainly include display module 10, center 11, shell 12 and cover board 13, Display module 10 and center 11 are set in shell 12.
Wherein, above-mentioned center 11 is between display module 10 and shell 12, surface of the center 11 far from display module 10 For installing the internal elements such as mainboard, mainboard can be for example printed wiring board (printed circuit board, abbreviation PCB)。
Above-mentioned display device 01 further include be set on PCB central processing unit (Central Processing Unit, CPU)。
Cover board 13 is located at display module 10 far from 11 side of center, and cover board 13 for example can be cover-plate glass (cover Glass, CG), which can have certain toughness.
Display module 10 has it can be seen that the light emission side of display picture and the back side being oppositely arranged with above-mentioned light emission side, show Show the back side of mould group 10 close to center 11, the light emission side of display module 10 is arranged in cover board 13.
Above-mentioned display module 10, including display screen (display panel, DP).
As shown in Fig. 2, display screen 101 includes multiple pixels (pixel), each pixel includes multiple sub-pixel (sub Pixel) 1010, multiple sub-pixel 1010 includes the first color sub-pixels, the second color sub-pixels and third color sub-pixels.
Exemplary, the first color is red, and the second color is green, and third color is blue.
The region that sub-pixel 1010 surrounds constitutes the viewing area A of display device 01, the region conduct positioned at the periphery viewing area A The peripheral region B of display device 01.
It is only a kind of signal to the division of viewing area A and peripheral region B in Fig. 2, does not do any restriction.
In some embodiments of the present application, as shown in Figure 3a, above-mentioned display screen 101 can be liquid crystal display (liquid Crystal display, LCD) screen.
In the case, display module 10 further include: close close to the first polarization layer 102 of 101 light emission side of display screen Second polarization layer 103 at 101 back side of display screen, for providing backlight module (the back light of light source to the liquid crystal display Unit, BLU) 104.
As shown in Figure 3b, liquid crystal display includes array substrate 1011, counter substrate 1012, liquid crystal layer 1013.Liquid crystal layer 1013 are set between array substrate 1011 and counter substrate 1012.Array substrate 1011 and counter substrate 1012 pass through sealant 1014 pairs are combined, so that liquid crystal layer 1013 is limited to array substrate 1011, counter substrate 1012 and sealant 1014 In the liquid crystal cell surrounded.
As shown in Figure 3c, array substrate 1011 includes the pixel circuit 10111 of multiple array arrangements, each sub-pixel 1010 In be provided with a pixel circuit 10111, pixel circuit 10111 for changing liquid crystal molecule in each sub-pixel 1010 polarised light Direction.
Illustrated so that pixel circuit 10111 includes thin film transistor (TFT) M1 as an example in Fig. 3 c, does not do any restriction, but pixel It necessarily include at least one thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) in circuit 10111.
L in pixel circuit 10111 refers to the liquid surrounded by array substrate 1011, liquid crystal layer 1013, counter substrate 1012 Part in brilliant box, in sub-pixel 1010 corresponding with the pixel circuit 10111.
It is exemplary, as shown in Figure 3d, each pixel circuit 10111 and a pixel electrode in array substrate 1011 10113 electrical connections, array substrate 1011 further include public electrode 10114 and are arranged in pixel circuit 10113 and public electrode Interlayer insulating film 10115 between 10114 and the layer insulation being arranged between public electrode 10114 and pixel electrode 10113 Layer 10115.Public electrode 10114 and pixel electrode 10113 are for driving the liquid crystal molecule in liquid crystal layer 1013 to rotate.
Illustrated by taking a TFT in pixel circuit 10111 as an example in Fig. 3 d.TFT includes the grid being cascading Pole 107, gate insulation layer 108, active layer 109 and source-drain electrode layer 110.Source-drain electrode layer 110 is electrically connected with pixel electrode 10113 It connects.
Wherein, in order to enable liquid crystal display can be realized colored display, the liquid crystal display is as shown in Figure 3b, further includes Chromatic filter layer 10121.The chromatic filter layer 10121 can be set in counter substrate 1012, and counter substrate 1012 can at this time With referred to as color membrane substrates.The color filter patterns that chromatic filter layer 10121 includes and is each located in each sub-pixel 1010.
As shown in Figure 3a, the first polarization layer 102 in liquid crystal display can be the polarizing film made (polarizer).In this case, it is possible to polarizing film is attached on the surface of the light emission side of display screen 101.
Alternatively, as shown in Figure 3b, the first polarization layer 102 can be wire grid polarization layer (grid polarizer, GP).Example , in the preparation process of counter substrate 1012, wire grid polarization layer can be collected using modes such as sputtering, nano impression, photoetching At in counter substrate 1012.
The material for constituting wire grid polarization layer can be metal.Exemplary, the material for constituting wire grid polarization layer includes but unlimited In aluminium (Al), copper (Cu), silver (Ag), gold (Au) and chromium (Cr) etc..
In addition, as shown in Figure 3a, the second polarization layer 103 can be the polaroid made.In the case, the second polarization Layer 103 is arranged on the surface at 101 back side of display screen.
Alternatively, as shown in Figure 3b, the second polarization layer 103 can be to be integrated in the manufacturing process of array substrate 1011 Wire grid polarization layer in array substrate 1011.
The displaying principle of display device 01 including liquid crystal display are as follows: backlight module 104 issues white light, partially by second Vibration layer 103 is formed with the white polarised light of particular polarization, injects array substrate 1011, then passes through liquid crystal layer 1013 and right It sets the chromatic filter layer on substrate 1012 and filters the polarised light to form red-green-blue.
When the polarization direction of the polarised light is vertical with the polarization direction of the first polarization layer 102, polarised light cannot pass through One polarization layer 102, dull thread is emitted at this time.
When the polarization direction of the polarised light is parallel with the polarization direction of the first polarization layer 102, polarised light can pass through the One polarization layer 102, the light intensity of emergent light is most strong at this time.
Since the liquid crystal molecule in liquid crystal layer 1013 has optically-active characteristic to polarised light, specific molecular arrangement direction can make this The polarization direction of polarised light changes, and changes each sub-pixel 1010 by the pixel circuit 10111 in array substrate 1011 The direction of polarized light of middle liquid crystal molecule, can control the angle of polarised light and the first polarization layer 102, to control each sub-pixel In 1010 from the first polarization layer 102 be emitted number, to show different gray scale images.
Therefore, the display device 01 including liquid crystal display is in the first polarization layer 102, the second polarization layer 103, liquid crystal layer Under the collective effect of 1013 threes, the amount that the light that control backlight module 104 issues is emitted from the first polarization layer 102 is aobvious to complete Show.
Alternatively, as shown in fig. 4 a, above-mentioned display screen 101 is organic light-emitting diodes in other embodiments of the application Manage (organic light emitting diode, OLED) display screen.In the case, the display module 10 further include: the Three polarization layers 105.OLED display screen can be realized self-luminous, therefore, no setting is required in display module 10 above-mentioned BLU.
As shown in Figure 4 b, OLED display screen include: array substrate 1011, be arranged in array substrate 1011 it is multiple shine Encapsulated layer 1017 of the luminescent device 1016 far from 1011 side of array substrate is arranged in device 1016.
As shown in fig. 4 a, third polarization layer 105 can be polaroid.In the case, the setting of third polarization layer 105 is aobvious On the surface of 101 light emission side of display screen.
Alternatively, as shown in Figure 4 b, third polarization layer 105 can be wire grid polarization layer, wire grid polarization layer is integrated in display screen In 101.In the case, in order to ensure wire grid polarization layer can play the reflective effect that filters out, the setting of wire grid polarization layer is being sent out Optical device 1016 is far from 1011 side of array substrate.
As illustrated in fig. 4 c, array substrate 1011 includes multiple pixel circuits 10111, is provided with one in each sub-pixel 1010 Pixel circuit 10111.Pixel circuit 10111 is electrically connected with the luminescent device 1016 in the sub-pixel 1010, is used for photophore 1016 transmission telecommunications number of part.
Pixel circuit 10111 as illustrated in fig. 4 c includes two thin film transistor (TFT)s (M1 and M2), and only a kind of signal is not done Any restriction, but necessarily include at least two thin film transistor (TFT)s in each pixel circuit 10111.
It is exemplary, as shown in figure 4d, each pixel circuit 10111 and a luminescent device 1016 in array substrate 1011 Electrical connection.
Luminescent device 1016 includes anode (Anode, abbreviation a), hole injection layer (hole being cascading Inject layer, HIL), hole transmission layer (hole transport layer, HTL), electroluminescence layer (emitting Material layer, EML), electron transfer layer (electron transport layer, ETL), electron injecting layer (electron inject layer, EIL) and cathode (Cathode, abbreviation c).
Illustrated by taking a TFT in pixel circuit 10111 as an example in Fig. 4 d.TFT includes the grid being cascading Pole 107, gate insulation layer 108, active layer 109 and source-drain electrode layer 110.Interlayer is provided between TFT and luminescent device 1016 Insulating layer 10115, the via hole between anode a is passed through on insulating layer 10115 are electrically connected with source-drain electrode layer 110.
It should be noted that above-mentioned OLED display screen can be flexible display screen.It may be hard display screen.
The principle of luminosity of display device 01 including OLED display screen are as follows: pixel circuit 10111 is defeated to luminescent device 1016 The electric signal entered, luminescent device 1016 shine under the driving of pixel circuit 10111.By controlling pixel circuit 10111 to hair The size for the electric signal that optical device 1016 inputs, can control the light emission luminance of each luminescent device 1016.
In addition, the reflective layer (such as anode) in OLED display screen, can to the environment light entered in OLED display screen into Row reflection, reflected light are passed through third polarization layer 105, can be filtered out, and are clearly indicated with realizing.
Based on above-mentioned it is found that no matter display screen 101 is LCD screen or OLED display screen, pixel circuit 10111 is to promote to show The component of the luminous core of display screen 101.And the driving signal in pixel circuit 10111 is transmitted by above-mentioned PCB.
Hereinafter, the connection relationship to pixel circuit 10111 in PCB is illustrated.
As shown in Figure 5 a, the peripheral region B of display device 01 includes binding area C, and driving chip 106 is located in binding area C, drives Dynamic chip 106 is completed to bind in binding area C with array substrate 1011.Driving chip 106 is used for the driving signal transmitted to PCB After being handled, it is transmitted to pixel circuit 10111.
Wherein, the signal wire 10112 being electrically connected with pixel circuit 10111, for transmitting telecommunications to pixel circuit 10111 Number.Therefore, driving chip 106 is electrically connected in binding area C with signal wire 10112, is as realized and is electrically connected with pixel circuit 10111 It connects.
It is understood that signal wire 10112 for example can be data line, mentioned for the TFT into pixel circuit 10111 For data voltage.Signal wire 10112 for example can also be operating voltage line, for providing supply voltage etc..
About the binding mode of driving chip 106 and array substrate 1011, in some embodiments of the present application, such as Fig. 5 b It is shown, a kind of design generallyd use be driving chip 106 be directly bound in array substrate 1011 (chip on glass, Abbreviation COG).
In this case, driving chip 106 is directly bound with array substrate 1011.
Since driving chip 106 is fed to the driving signal that pixel circuit 10111 transmits by PCB, PCB is located at above-mentioned center On 11.Therefore, as shown in Figure 5 b, driving chip 106 passes through flexible circuit board (flexible printed circuit, abbreviation FPC it) is electrically connected with PCB.
It is that driving chip 106 is fixed on film using a kind of design as shown in Figure 5 c in some embodiments of the present application (chip on film, abbreviation COF), to realize that the signal between PCB and pixel circuit 10111 transmits.
That is, as shown in Figure 5 c, driving chip 106 is fixed on FPC, and is electrically connected with FPC.FPC respectively with PCB It is electrically connected with array substrate 1011.
In this case, FPC and array substrate 1011 are bound.
Which kind of either above-mentioned situation, the structure and binding quality of the binding area C of array substrate 1011 are closely bound up.In order to Convenient for explanation, it is illustrated so that driving chip 106 is directly bound with array substrate 1011 as an example below.
In the following, the structure of the binding area C of array substrate 1011 is illustrated.
As shown in Figure 6 a, array substrate 1011 includes viewing area A and peripheral region B, the viewing area of array substrate 1011 and aobvious The viewing area of showing device 01 is overlapped, and the peripheral region of array substrate 1011 and the peripheral region of display device 01 are overlapped.Binding area C is located at In the B of peripheral region, by taking viewing area A is polygon as an example, binding area C is located at the side of viewing area A.
Binding area C includes the signal converting area C1 and signal transmission range C2 positioned at at least side signal converting area C1.
Signal, as shown in Figure 6 a, signal converting area C1 is provided with signal transmission range C2 close to the side of viewing area.
Signal, as shown in Figure 6 b, signal converting area C1 is provided with a signal transmission range C2 close to the side of viewing area, Signal converting area C1 is also equipped with a signal transmission range C2 far from the side of viewing area.That is, binding area C includes opposite Two signal transmission range C2 being arranged.
Under normal circumstances, positioned at signal converting area C1 close to the signal transmission range C2 of the side of viewing area, for that will drive Signal on chip 106106 is transmitted to signal wire 10112.The signal of side positioned at signal converting area C1 far from viewing area passes Defeated area C2 is transmitted to signal wire 10112 for detecting signal.
It whether can be that good product detects to display device 01 before the factory of display device 01.Above-mentioned detection signal, Refer to whether detection display device 01 meets the signal transmitted when factory requires.
In the case where binding area C includes two signal transmission range C2 being oppositely arranged, the knot of two signal transmission range C2 Structure may be the same or different.
As shown in Figure 7a, array substrate 1011 includes: substrate 20.
As shown in Figure 6 b, array substrate 1011 further includes at least one signal lead 21.
As shown in Figure 7a, signal lead 21 is arranged on substrate 20, and is located at least in signal transmission range C2.
That is, signal lead 21 may also extend to signal converting area C1 according to design requirement.
Wherein, signal lead 21 can be arranged directly on substrate 20.As shown in Figure 7a, signal lead 21 and substrate 20 it Between buffer layer 25 also can be set.
In order to simplify preparation process, signal lead 21 can in the above-mentioned pixel circuit 10111 positioned in the A of viewing area, The same material of 107 same layer of grid of TFT.The material of signal lead 21 for example can be molybdenum (Mo).
In addition, as shown in Figure 8 a, along the direction of routing of signal lead 21, that is, first direction X, the width of signal lead 21 Degree is not necessarily identical.
Array substrate 1011 further includes the first insulating layer 22.First insulating layer 22 is arranged in signal line leads far from substrate 20 Side；At least one first via hole 221 is provided on first insulating layer 22 (there are two being arranged on the first insulating layer 22 in Fig. 7 a Illustrated for first via hole 221).
It is understood that other film layers can be set between the first insulating layer 22 and signal lead 21, can not also set Set other film layers.
In the case that other film layers are set between the first insulating layer 22 and signal lead 21, in film layer with the first via hole It should be provided with connection via hole at 221 corresponding positions, and connect via hole and the connection of the first via hole 221, so that the first via hole 221 reveals Signal lead 21 out.
It should be noted that the first via hole 221 is for being electrically connected binding portion 23 and signal lead 21.Therefore, often 21 corresponding position of bars lead should be provided at least one first via hole 221.
About the arrangement mode of the first via hole 221, in some embodiments, as shown in Figure 8 a, every bars lead 21 is right A groups of vias 222 to be answered, includes multiple first via holes 221 in each groups of vias 222, multiple first via holes 221 are arranged into two rows, It often ranked first via hole 221 to be intervally arranged along first direction X.
In some embodiments, as shown in Figure 8 b, the corresponding groups of vias 222 of every bars lead 21, each groups of vias It include multiple first via holes 221 in 222, multiple first via holes 221 are intervally arranged in a row along first direction X.
As shown in Figure 7a, array substrate 1011 further includes at least one binding portion 23.The setting of binding portion 23 is in the first insulation Layer 22 is far from 20 side of substrate, and each binding portion 23 is electrically connected by the first via hole 221 with a signal line lead；Binding portion 23 are located at least in signal converting area C1.
It is understood that binding portion 23 is electrically connected with signal lead 21, the material in binding portion 23 is necessarily conductive material.
In order to simplify preparation process, binding portion 23 can in the above-mentioned pixel circuit 10111 positioned in the A of viewing area, TFT The same material of 110 same layer of source-drain electrode layer.The material in binding portion 23 for example can be titanium (Ti)/aluminium (Al)/Ti stepped construction.
It should be noted that as shown in Figure 7a, in the case where the first via hole 221 is located at signal converting area C1, binding portion 23 are electrically connected in signal converting area C1 with signal lead 21.In such cases, binding portion 23 can be only located at signal converting area C1.
Certainly, as shown in Figure 7b, binding portion 23 can also extend to signal transmission range C2.In the case, binding portion 23 In can also be covered by second insulating layer 24 positioned at the part of signal transmission range C2.
As shown in figure 9, binding portion 23 is in signal transmission range in the case where the first via hole 221 is located at signal transmission range C2 C2 is electrically connected with signal lead 21.In such cases, binding portion 23 necessarily extends to signal transmission range C2.
As shown in Figure 7a, array substrate 1011 further includes second insulating layer 24.Second insulating layer 24 is arranged in binding portion 23 Surface far from substrate 20, second insulating layer 24 are located at orthographic projection of the binding portion 23 on substrate 20 in the orthographic projection on substrate 20 It is interior, and second insulating layer 24 covers the part being electrically connected in binding portion 23 with signal lead 21.
As shown in Fig. 7 a and Fig. 9, position in the part being electrically connected in binding portion 23 with signal lead 21, that is, binding portion 23 Part in the first via hole 221.Below for ease of description, the part being electrically connected in binding portion 23 with signal wire is known as taking Socket part 231.
Second insulating layer 24 necessarily covers clinch 231, that is to say, that orthographic projection position of the clinch 231 on substrate 20 In second insulating layer 24 in the orthographic projection on substrate 20.
But second insulating layer 24 not fully covers binding portion 23, and the part of signal converting area C1 is located in binding portion 23, It is inevitable some do not covered by second insulating layer 24, to complete to be electrically connected with driving chip 106.
That is, driving chip 106 is bound by binding portion 23 with array substrate 1011.
If array substrate 1011 is not provided with above-mentioned second insulating layer 24 in binding area C, the binding area C's of array substrate 1011 Structure is as shown in Figure 10, clinch 231 directly it is exposed outside.In the preparation process of array substrate 1011, binding portion is prepared After 23, it is also necessary to prepare other film layers.Such as need to prepare luminescent device 1016 in above-mentioned OLED display screen.Preparing other When film layer (including resin layer and conductive layer), need to pattern film layer.It as shown in figure 11, can be right during patterned Binding block, which generated, to be influenced at quarter etc..And clinch 231 is located in the first via hole 221, corrosion damage is even more serious.Cause to drive When chip 106 and binding portion 23 are bound, overlap resistance is excessive.
The embodiment of the present application makes the second insulation by the way that second insulating layer 24 is arranged far from 20 side of substrate in binding portion 23 Layer 24 covers clinch 231, can play a protective role to clinch 231.It avoids producing clinch 231 in subsequent preparation process Raw damage, causes resistance excessive.Further, since the part for being located at signal converting area C1 in binding portion 23 is not completely exhausted by second Edge layer 24 covers.Therefore, driving chip 106 is not influenced and binding portion 23 is bound.
Hereinafter, being illustrated with structure of several examples to array substrate 1011 provided by the present application.
Example one
Fewer, the binding portion 23 that part due to being located at signal converting area C1 in 24 pairs of binding portions 23 of second insulating layer covers Bigger with the area of driving circuit binding, binding resistance is fewer.
Array substrate 1011 includes at least one signal lead 21, and signal lead 21 is arranged on substrate 20, and at least position In signal transmission range C2.
First insulating layer 22 is arranged in signal line leads far from 20 side of substrate；It is provided at least on first insulating layer 22 One the first via hole 221.
At least one binding portion 23 is arranged in the first insulating layer 22 far from 20 side of substrate, and each binding portion 23 passes through First via hole 221 is electrically connected with a signal line lead；Binding portion 23 is located at least in signal converting area C1.
Surface of the binding portion 23 far from substrate 20 is arranged in second insulating layer 24, and second insulating layer 24 is on substrate 20 Orthographic projection is located at the part in binding portion 23 positioned at signal converting area C1 in the orthographic projection on substrate 20.
And as shown in Figure 7a, second insulating layer 24 only covers the part being electrically connected in binding portion 23 with signal lead 21.
That is, second insulating layer 24 only covers the clinch 231 in binding portion 23.
In some embodiments, 10115 same layer of above-mentioned interlayer insulating film in second insulating layer 24 and array substrate 1011 Same material.
The interlayer that interlayer insulating film 10115 can be between the public electrode 10114 in Fig. 3 d and pixel electrode 10113 is exhausted Edge layer 10115 is also possible to the public electrode 10114 in Fig. 3 d and the interlayer insulating film between TFT 10115.
Interlayer insulating film 10115 can also be the luminescent device 1016 in Fig. 4 d and the interlayer insulating film between TFT 10115。
It can be by the pattern of change mask plate, so that second insulating layer 24 and the same material of 10115 same layer of insulating layer.
Since driving circuit and the bond impedance in binding portion 23 are larger, binding portion 23 is not suitable for by second insulating layer 24 excessive coverings.If 24 area coverage of second insulating layer exceeds clinch 231, will affect driving circuit and binding portion 23 it Between impedance, lose more than gain.So 24 covering clinch 231 of second insulating layer in application, increase driving circuit and binding portion 23 contact area, to evade the big problem of binding impedance.
In some embodiments, as shown in figure 12, array substrate 1011 further includes setting in the separate lining of second insulating layer 24 The auxiliary conductive layer on the surface at bottom 20.
Second insulating layer 24 is located at auxiliary conductive layer in the orthographic projection on substrate 20 in the orthographic projection on substrate 20.
That is, auxiliary conductive layer covers second insulating layer 24.
Although only covering the clinch 231 in binding portion 23 due to second insulating layer 24, the other positions in binding portion 23 It remains to bind with driving circuit.But the presence of second insulating layer 24 can reduce contact of the binding portion 23 with driving circuit always Area.Therefore, by covering auxiliary conductive layer on 24 surface of second insulating layer, it is possible to increase contact of the binding portion 23 with driving circuit Area reduces binding impedance.
In addition, can reduce by covering auxiliary conductive layer on 24 surface of second insulating layer and prepare work to second insulating layer 24 The requirement of skill, to reduce preparation cost.
In some embodiments, the above-mentioned same material of electrode layer same layer on auxiliary electrode layer and array substrate 1011.
Wherein, electrode layer can be public electrode 10114 or pixel electrode 10113 in Fig. 3 d.
Electrode layer is also possible to anode a or cathode c in Fig. 4 d.
It can be by the pattern of change mask plate, so that auxiliary electrode layer and the same material of electrode layer same layer.
In some embodiments, the aperture of the first via hole 221 is 2~4um.
For example, the aperture of the first via hole 221 is 2.5um, 3.0um, 3.5um.
In binding procedure, driving circuit is bound by soldered ball and binding portion 23, and the diameter of soldered ball is generally in 5um or so. In order to avoid in the welding process, soldered ball directly falls into the sunk area of the first via hole 221 formation, without being electrically connected with driving circuit It connects.The aperture setting of the first via hole 221 can be fallen into the formation of the first via hole 221 in 2~4um to avoid soldered ball in the application In sunk area, guarantee the stability of binding.
Example two
As shown in figure 13, array substrate 1011 includes at least one signal lead 21, and signal lead 21 is arranged in substrate 20 On, and it is located at least in signal transmission range C2.
First insulating layer 22 is arranged in signal line leads far from 20 side of substrate；It is provided at least on first insulating layer 22 One the first via hole 221, the first via hole 221 are located at signal transmission range C2.
At least one binding portion 23 is arranged in the first insulating layer 22 far from 20 side of substrate, and each binding portion 23 passes through First via hole 221 is electrically connected with a signal line lead；Binding portion 23 is located at signal converting area C1 and extends to signal transmission range C2。
Second insulating layer 24, is arranged in surface of the binding portion 23 far from substrate 20, and second insulating layer 24 covers binding portion 23 In be located at signal transmission range C2 part.
That is, second insulating layer 24 covers the part for being located at signal transmission range C2 in binding portion 23, expose binding portion It is located at the part of signal converting area C1 in 23.
When in signal converting area, C1 opposite two sides are provided with signal transmission range C2, array substrate 1011 binds area C's Structure is as shown in figure 14.
Wherein, the first via hole 221 can be only located in one in two signal transmission range C2.
In some embodiments, as shown in figure 14, the first via hole 221 is provided in two signal transmission range C2.
Due to the quantity of the first via hole 221, the contact resistance between binding portion 23 and signal lead 21, the first via hole are determined 221 quantity are about more, and the contact area between binding portion 23 and signal lead 21 is bigger, and contact resistance is smaller.Therefore, the first via hole 221 should be arranged the first via hole 221 of fair amount.
It is exemplary, it is assumed that diameter d=2.0~2.5um of the first via hole 221, corresponding first mistake of a bars lead 21 Quantity N=60~70 in hole 221.
188~343um of contact area S=π (d/2) 2*N ≈ between binding portion 23 and signal lead 212。
In the case, the part that two signal transmission range C2 have binding portion 23 to contact with signal lead 21, two parts The sum of meet above-mentioned contact area S.
So, on the basis of guaranteeing the contact area in binding portion 23 and signal lead 21, it is possible to reduce close to aobvious Show the quantity of the first via hole 221 in the signal transmission range C2 of area A, to reduce the face of the signal transmission range C2 close to viewing area A Product, to reduce the screen accounting of non-display area B.
Due to being damaged due to the clinch 231 being located in the first via hole 221 is easy and carves because crossing, by the first via hole in this example 221 are transferred in signal transmission range C2, and second insulating layer 24 is made to cover clinch 231, can avoid clinch 231 and spend quarter.
In addition, the first via hole 221 is transferred to signal transmission range C2, the part of signal converting area C1 is located in binding portion 23 In the same plane.As shown in figure 15, when binding portion 23 and driving chip 106 are bound, binding portion 23 is plane, is had certain Support improves the effect for protecting binding portion 23 and the connection of driving chip 106.
Furthermore since the sunk area of the first via hole 221 formation is not in signal converting area C1, it is therefore not necessary to consider to drive When chip 106 and binding portion 23 are bound, the problem of soldered ball can fall into the sunk area of the first via hole 221 formation.It can be as far as possible The aperture of the first via hole of increase 221 advantageously reduce signal to reduce the contact resistance in binding portion 23 and signal lead 21 and decline Subtract.
Based on this, in some embodiments, the aperture of the first via hole 221 is greater than signal transmission range C2 along first direction X's The half of size.
So, the contacts contact face product of binding portion 23 and signal lead 21 can be increased, as far as possible to reduce binding portion 23 and signal lead 21 contact resistance.
Exemplary, as shown in figure 16, binding portion 23 and signal lead 21 are contacted in a manner of overlapping channel, so that binding portion 23 and signal lead 21 contact area it is big as far as possible.
Equally, meeting 188~343um of above-mentioned contact area S ≈2In the case where, it is assumed that the width W=of signal lead 21 6um。
The length that binding portion 23 and signal lead 21 need to overlap: L=S/W ≈ (188~343)/6=31.3~ 57.16um。
It in this case, can be on the basis for meeting above-mentioned overlapping length L in the size of modelled signal transmission range C2 On, reduce the area of signal transmission range C2, as far as possible to realize the narrow frame of display device 01.
In order to simplify preparation process, in some embodiments, the above-mentioned layer in second insulating layer 24 and array substrate 1011 Between the same material of 10115 same layer of insulating layer.
The interlayer that interlayer insulating film 10115 can be between the public electrode 10114 in Fig. 3 d and pixel electrode 10113 is exhausted Edge layer 10115 is also possible to the public electrode 10114 in Fig. 3 d and the interlayer insulating film between TFT 10115.
Interlayer insulating film 10115 can also be the luminescent device 1016 in Fig. 4 d and the interlayer insulating film between TFT 10115。
It can be by the pattern of change mask plate, so that second insulating layer 24 and the same material of 10115 same layer of insulating layer.
In order to be further simplified preparation process, second insulating layer 24 is structure as a whole with above-mentioned interlayer insulating film 10115.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.

Claims (10)

1. a kind of array substrate, including viewing area and positioned at the binding area of the viewing area side, the binding area includes signal Translation field and signal transmission range positioned at the signal converting area at least side；It is characterized in that, the array substrate includes:
Substrate；
At least one signal lead, the signal lead setting over the substrate, and are located at least in the signal transmission range；
First insulating layer is arranged in the signal line leads far from the one side of substrate；Be provided on first insulating layer to Few first via hole；
At least one binding portion is arranged in first insulating layer far from the one side of substrate, and each binding portion passes through First via hole is electrically connected with the signal line leads；The binding portion is located at least in the signal converting area；
The surface of the binding portion far from the substrate is arranged in second insulating layer, and the second insulating layer is over the substrate Orthographic projection be located in the orthographic projection of the binding portion over the substrate, and the second insulating layer covers in the binding portion The part being electrically connected with the signal lead.
2. array substrate according to claim 1, which is characterized in that the second insulating layer only covers in the binding portion The part being electrically connected with the signal lead.
3. array substrate according to claim 1 or 2, which is characterized in that the array substrate further includes being arranged described The auxiliary conductive layer on surface of the second insulating layer far from the substrate；
The orthographic projection of the second insulating layer over the substrate is located at the orthographic projection of the auxiliary conductive layer over the substrate It is interior.
4. array substrate according to claim 3, which is characterized in that the array substrate further includes being located at the viewing area Electrode layer；
The auxiliary conductive layer and the same material of electrode layer same layer.
5. array substrate according to claim 1 or 2, which is characterized in that the aperture of first via hole is 2~4um.
6. array substrate according to claim 1, which is characterized in that the binding portion extends to the signal transmission range, First via hole is located at the signal transmission range；
The second insulating layer covers the part for being located at the signal transmission range in the binding portion.
7. array substrate according to claim 1 or 6, which is characterized in that the aperture of first via hole is greater than the letter The half of number transmission range along the size of first direction；
Wherein, the first direction is the direction of routing of the signal lead.
8. array substrate described according to claim 1 or 2 or 6, which is characterized in that the array substrate further includes being arranged in institute State the thin film transistor (TFT) on substrate；
The thin film transistor (TFT) includes source-drain electrode layer and the interlayer of the source-drain electrode layer far from the one side of substrate is arranged in Insulating layer；
The second insulating layer and the same material of interlayer insulating film same layer.
9. array substrate according to claim 8, which is characterized in that be located at the signal transmission range in first via hole In the case where, the second insulating layer is structure as a whole with the interlayer insulating film.
10. a kind of display device, which is characterized in that including driving chip and the described in any item array substrates of claim 1-9；
The driving chip is electrically connected with the binding portion in the array substrate.
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