CN110121774B

CN110121774B - Method of forming a gate structure of a three-dimensional memory device

Info

Publication number: CN110121774B
Application number: CN201880005286.9A
Authority: CN
Inventors: 徐强; 夏志良; 邵明; 霍宗亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2017-08-23
Filing date: 2018-06-04
Publication date: 2020-03-27
Anticipated expiration: 2038-06-04
Also published as: CN111180449A; TW201913977A; WO2019037509A1; TWI699877B; CN110121774A; CN107731823A; CN111180449B

Abstract

The present disclosure provides a method for forming a gate structure of a 3D memory device. The method comprises the following steps: forming alternating insulator stack layers on a substrate; forming a plurality of slits, each slit passing vertically through the alternating insulator stack layers and extending in a horizontal direction; removing the plurality of sacrificial layers in the alternating insulator stack layers through the plurality of slits to form a plurality of trenches; forming a conductor layer in each trench; forming a first isolation layer on the side wall of the slit to cover the conductor layer and prevent the conductor layer from being oxidized; forming a second isolation layer on a surface of the first isolation layer, the second isolation layer being of a different material from the first isolation layer; and depositing a conductive material into the slots to form a plurality of conductive walls, the conductive walls being insulated from the conductor layer.

Description

Method of forming a gate structure of a three-dimensional memory device

Cross Reference to Related Applications

This application claims priority to chinese patent application No.201710729505.5 filed on 23.8.2017, the entire contents of which are incorporated herein by reference.

Technical Field

Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of fabricating the same.

Background

By improving process technology, circuit design, programming algorithms and manufacturing methods, planar memory cells can be scaled to smaller dimensions. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the storage density of the planar memory cell approaches the upper limit.

The 3D memory architecture can address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral components for controlling signals to and from the memory array.

Disclosure of Invention

Embodiments of methods for forming a gate structure of a 3D memory device are disclosed herein.

A method of forming a three-dimensional (3D) NAND memory device disclosed below, comprising: forming an alternating insulator stack layer comprising a plurality of dielectric layer pairs on a substrate, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a plurality of slits, each slit passing vertically through the alternating insulator stack layers and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating insulator stack layer through a plurality of slits to form a plurality of trenches; forming a conductor layer in each of the plurality of trenches; forming a first isolation layer on sidewalls of the plurality of slits to cover the conductor layer to prevent the conductor layer from being oxidized; forming a second isolation layer on a surface of the first isolation layer, the second isolation layer being of a different material than the first isolation layer; and depositing a conductive material into the slots to form a plurality of conductive walls, wherein the plurality of conductive walls are insulated from the conductor layer.

In some embodiments, each of the plurality of dielectric layer pairs is formed of a silicon oxide layer having a thickness in a range of about 10nm to about 150nm and a silicon nitride layer having a thickness in a range of about 10nm to about 150 nm.

In some embodiments, the method further comprises: forming a plurality of channel structures, each channel structure passing vertically through the alternating insulator stack layers; wherein each slit of the plurality of slits extends horizontally between the plurality of channel structures.

In some embodiments, the method further comprises: after forming the plurality of slits, a plurality of doped regions are formed in the substrate below the slits such that each conductive wall is in contact with a respective doped region.

In some embodiments, the method further comprises: forming a film comprising silicon, silicon nitride, silicon oxynitride, or aluminum oxide as the first spacer layer, the film having a thickness in a range of about 0.1nm to about 10 nm.

In some embodiments, the method further comprises: forming a silicon film as the first isolation layer; forming a silicon oxide film as the second isolation layer; and oxidizing at least a part of the silicon film to silicon oxide in the process of forming the second isolation layer.

In some embodiments, forming the plurality of channel structures comprises: forming a channel hole extending vertically through the alternating insulator stack layers; forming a functional layer on sidewalls of the channel hole; and forming a channel layer overlying the functional layer sidewalls.

In some embodiments, forming the functional layer comprises: forming a blocking layer on a sidewall of the channel hole for blocking outflow of charges; forming a storage layer on a surface of the blocking layer for storing charges during operation of the 3D memory device; and forming a tunnel layer on a surface of the storage layer for tunneling charges.

In some embodiments, the method further comprises: forming an insulating layer in the plurality of trenches before forming the conductor layer in the plurality of trenches.

In some embodiments, forming the insulating layer comprises: forming a first insulating sub-layer covering top and bottom surfaces of the plurality of first dielectric layers and outer sidewall portions of the functional layer exposed by the plurality of trenches; and forming a second insulating sub-layer having a thickness in a range of about 1nm to about 10nm to cover the first insulating sub-layer.

In some embodiments, the first insulating sub-layer is formed by depositing a first material comprising aluminum oxide; and forming the second insulating sub-layer by depositing a second material comprising titanium nitride.

In some embodiments, the method further comprises: performing a phosphoric acid rinsing process to clean the plurality of trenches before forming the insulating layer, wherein a rinsing temperature of the phosphoric acid rinsing process is in a range of about 100 ℃ to about 200 ℃, and a rinsing time of the phosphoric acid rinsing process is about 10 minutes to about 100 minutes.

In some embodiments, forming the conductor layer comprises: filling the plurality of trenches with a conductive material; and removing portions of the conductive material to form a plurality of separate gates, each of the plurality of separate gates being located in a respective trench.

In some embodiments, forming the first isolation layer comprises: performing a multi-atomic layer chemical vapor deposition process or an atomic layer deposition process to form the first isolation layer.

In some embodiments, forming the first isolation layer comprises: forming the first isolation layer to cover sidewalls of the plurality of slits, exposed surfaces of the insulating layer, and exposed surfaces of the conductor layer.

In some embodiments, forming the first isolation layer comprises: forming the first isolation layer having a plurality of recesses, each recess corresponding to a separate gate.

In some embodiments, forming the alternating insulator stack layers comprises: forming the alternating insulator stack layers in a vertical direction to a thickness greater than 1000 nm.

In some embodiments, forming the plurality of conductive walls comprises: depositing a material comprising tungsten into the plurality of slots to form the plurality of conductive walls.

Another aspect of the present disclosure provides a three-dimensional (3D) NAND memory device, including: an alternating insulator/conductor stack comprising a plurality of insulator/conductor layer pairs on a substrate, each of the plurality of insulator/conductor layer pairs comprising a dielectric layer and a conductor layer; a plurality of slots, each slot passing vertically through the alternating insulator/conductor stack and extending in a horizontal direction; a first isolation layer on sidewalls of the plurality of slits to cover the conductor layer to prevent the conductor layer from being oxidized; a second isolation layer on the surface of the first isolation layer, the material of the second isolation layer being different from the material of the first isolation layer; and a conductive wall sandwiched by the second spacer layer in each of the slots, wherein the conductive wall is insulated from the conductor layers of the alternating insulator/conductor stack.

In some embodiments, each of the dielectric layers is a silicon oxide layer having a thickness in a range from about 10nm to about 150 nm; each of the conductor layers is a tungsten layer having a thickness in a range of about 10nm to about 150 nm; and the conductive wall comprises tungsten.

In some embodiments, the assembly further comprises: a plurality of channel structures, each channel structure passing vertically through the alternating insulator/conductor stack; wherein each slit of the plurality of slits extends horizontally between the plurality of channel structures.

In some embodiments, the assembly further comprises: a plurality of doped regions in the substrate below the slots, wherein the conductive wall is in contact with a corresponding doped region in each slot.

In some embodiments, the first isolation layer is a film comprising silicon, silicon nitride, silicon oxynitride, or aluminum oxide; and the second isolation layer is a silicon oxide film.

In some embodiments, the first spacer layer has a thickness in a range from about 0.1nm to about 10 nm.

In some embodiments, each of the plurality of channel structures comprises: a channel hole extending vertically through the alternating insulator/conductor stack; a functional layer on a sidewall of the channel hole; and a channel layer covering a sidewall of the functional layer.

In some embodiments, the functional layer comprises: the blocking layer is positioned on the side wall of the channel hole and used for blocking the outflow of charges; a storage layer on a surface of the blocking layer to store charge during operation of the 3D memory device; and a tunneling layer on a surface of the storage layer for tunneling charges.

In some embodiments, the assembly further comprises: an insulating layer between each of the dielectric layers and each of the conductor layers.

In some embodiments, the insulating layer is located between the conductor layer and the functional layer.

In some embodiments, the insulating layer comprises: a first insulating sublayer covering top and bottom surfaces of the plurality of dielectric layers and an outer sidewall portion of the functional layer; and a second insulating sublayer covering the first insulating sublayer and having a thickness ranging from about 1nm to about 10 nm.

In some embodiments, the first insulating sublayer comprises aluminum oxide; and the second insulating sublayer comprises titanium nitride.

In some embodiments, the first isolation layer has a plurality of recesses, each recess corresponding to a conductor layer sandwiched between two dielectric layers.

In some embodiments, the alternating insulator/conductor stack has at least 64 insulator/conductor layer pairs and has a thickness greater than 1000nm in the vertical direction.

Other aspects of the disclosure will become apparent to those skilled in the art from consideration of the specification, claims and drawings.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments disclosed in the present disclosure and, together with the detailed description, further serve to explain the principles disclosed in the present disclosure sufficiently to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1 illustrates a cross-sectional schematic view of an exemplary 3D memory device according to some fabrication methods.

Fig. 2 illustrates a flow diagram of an exemplary method for forming a gate structure of a 3D memory device, according to some embodiments of the present disclosure.

Fig. 3A-3G illustrate cross-sectional schematic views of an exemplary 3D memory device at certain stages of manufacture of the method illustrated in fig. 2, according to some embodiments of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this is done for exemplary purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure may also be used in a variety of other applications.

Various embodiments according to the present disclosure provide a gate last process for forming a gate structure of a 3D memory device. In the disclosed method, after forming the multi-layered gate structure and before forming the spacers (e.g., silicon oxide layer) on the sidewalls of the slits, additional spacers (e.g., silicon film) may be formed to cover the exposed surface of the multi-layered gate structure, preventing the exposed surface of the multi-layered gate structure from being oxidized during deposition of the silicon oxide layer. Thus, the leakage between the multi-layer gate structure and the conductive wall in the slit can be eliminated.

It is noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood at least in part from the context in which they are used. For example, the term "one or more" as used herein may be used to describe a feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may be understood to convey a singular use or to convey a plural use, depending at least in part on the context.

It should be readily understood that the meaning of "on …," "over …," and "over …" in this disclosure should be read in the broadest manner such that "on …" means not only "directly on" but also includes the meaning of "on" something with intervening features or layers therebetween, and "over …" or "over …" means not only "over" or "over" something, but may also include the meaning of "over" or "over" something with no intervening features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one component or feature's relationship to another component or feature or features, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations in use or operation of the device in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material to which a subsequent material is added or otherwise "disposed. The substrate itself may be patterned. The material disposed on the substrate (e.g., the top) may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Further, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any horizontal pair of surfaces at the top and bottom surfaces or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, above, and/or below. The layer may include a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnects, and/or vias are formed) and one or more dielectric layers.

As used herein, the term "nominal" refers to a desired or target value, and a range of values above and/or below the desired value, for a characteristic or parameter of a component or process operation that is set during a design time of the production or process. The range of values may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" refers to a value of a given amount that may vary based on the particular technology node associated with the subject semiconductor component. The term "about" can indicate a value of a given quantity that varies, for example, within 10% -30% of the value (e.g., ± 10%, ± 20% or ± 30% of the value), based on the particular technology node.

As used herein, the term "3D storage device" refers to a semiconductor component having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of a substrate.

Fig. 1 illustrates a cross-sectional schematic view of an exemplary 3D memory device according to some fabrication methods. In some fabrication methods, a gate-last process may include depositing a plurality of silicon nitride layers as dummy gate layers. A plurality of silicon oxide layers are formed to isolate the plurality of dummy gate layers. A plurality of slits are formed through an etching process. A plurality of horizontal trenches are formed by etching the plurality of silicon nitride layers to remove the dummy gate layer. A multi-layer gate structure is formed by a metal deposition process. A further etching process is performed to separate the plurality of metal gates. A silicon oxide layer is formed on sidewalls of the plurality of slits. And a metal wall is provided in each slit as an array shared source (ACS), and a metal contact is formed.

In some manufacturing methods, the metal gate is easily oxidized to generate metal whiskers during a subsequent deposition process for forming a silicon oxide layer. As shown in fig. 1, the resulting metal whiskers may grow close to the silicon oxide layer on the ACS sidewall, or even through the silicon oxide layer on the ACS sidewall, causing leakage between the metal gate and the metal wall in the slit. That is, existing manufacturing methods may result in product failure.

Accordingly, the present disclosure provides a gate-last process for forming a gate structure of a 3D memory device. In the disclosed gate last process, a silicon film with a moderate thickness can be formed between the metal gate and the silicon oxide layer on the sidewall of the slit. The silicon film can be used as a protective layer to effectively prevent the metal gate from being oxidized into whiskers to be directly contacted with the metal wall in the slit, thereby ensuring the normal function of the product.

Fig. 2 illustrates a flow diagram of an exemplary method for forming a gate structure of a 3D memory device, according to some embodiments of the present disclosure. Fig. 3A-3G illustrate cross-sectional schematic views of an exemplary 3D memory device at certain stages of manufacture of the method illustrated in fig. 2, according to some embodiments of the present disclosure.

As shown in fig. 2, the method begins with step S2, where alternating insulator stack layers are formed on a substrate. In some embodiments, the substrate may be any suitable semiconductor substrate having any suitable structure, such as a single crystal single layer substrate, a polycrystalline silicon (polysilicon) single layer substrate, a polycrystalline silicon and metal multilayer substrate, and the like.

As shown in fig. 3A, alternating insulator stack layers 200 comprising a plurality of dielectric layer pairs may be formed on a substrate 100. Each dielectric layer pair of alternating insulator stack 200 may include an alternating stack of first dielectric layers 210 and second dielectric layers 220, where the second dielectric layers 220 are different from the first dielectric layers 210. In some embodiments, the first dielectric layer 210 may serve as an insulating layer and the second dielectric layer 220 may serve as a sacrificial layer, which will be removed in a subsequent process.

The plurality of first dielectric layers 210 and the second dielectric layers 220 extend in a lateral direction parallel to the surface of the substrate 100. In some embodiments, alternating insulator stack layers 200 have more layers than dielectric layers made of different materials and different thicknesses. Alternating insulator stack layers 200 can be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

In some embodiments, alternating insulator stack layer 200 may include a plurality of oxide/nitride layer pairs. Each dielectric layer pair includes a layer of silicon oxide 210 and a layer of silicon nitride 220. The plurality of oxide/nitride layer pairs are also referred to herein as "alternating oxide/nitride stacks. That is, in the alternating insulator stack layer 200, the plurality of oxide layers 210 and the plurality of nitride layers 220 alternate in the vertical direction. In other words, each of the other oxide layers 210 may be sandwiched by two adjacent nitride layers 220, and each nitride layer 220 may be sandwiched by two adjacent oxide layers 210, in addition to the top and bottom layers of a given alternating oxide/nitride stack.

The oxide layers 210 may each have the same thickness or have different thicknesses. For example, the thickness of each oxide layer may be in the range of about 10nm to about 150 nm. Similarly, the nitride layers 220 may each have the same thickness or have different thicknesses. For example, the thickness of each nitride layer may be in the range of about 10nm to about 150 nm. In some embodiments, the total thickness of alternating insulator stack layers 200 may be greater than 1000 nm.

It should be noted that in the present disclosure, oxide layer 210 and/or nitride layer 220 may include any suitable oxide material and/or nitride material. For example, elements of the oxide material and/or the nitride material may include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. In some embodiments, the oxide layer may be a silicon oxide layer and the nitride layer may be a silicon nitride layer.

Alternating insulator stack layers 200 may include any suitable number of oxide layers 210 and nitride layers 220. In some embodiments, the total number of oxide layers 210 and nitride layers 220 in alternating insulator stack layers 200 is equal to or greater than 64. That is, the number of oxide/nitride layer pairs may be equal to or greater than 32. In some embodiments, the alternating oxide/nitride stack includes more oxide or nitride layers than oxide/nitride layer pairs and of different materials and/or thicknesses. For example, the bottom and top layers in alternating insulator stack layers 200 can be oxide layers 210.

As shown in fig. 2, the method proceeds to step S4, where a plurality of channel structures may be formed in the alternating insulator stack layers. Each channel structure may include a channel hole 300 extending vertically through alternating insulator stack layers 200, a functional layer 310 on sidewalls of the channel hole 300, and a channel layer 320 between the functional layer and a fill structure 330. The multi-channel structure may be arranged in an array in alternating insulator stack layers 200. For example, the number of the plurality of channel structures may be 1, 22, 32, (1+ n)2, where n is an integer greater than 1.

In some embodiments, the fabrication process to form the channel structure includes forming a channel hole 300 that extends vertically through alternating insulator stack layers 200. The channel hole 300 may have a high aspect ratio and may be formed by etching the alternating insulator stack layer 200 and a subsequent cleaning process. The etching process to form the channel hole 300 may be wet etching, dry etching, or a combination thereof.

In some embodiments, the functional layer 310 is formed on the sidewalls of the trench hole 300. The functional layer may be a composite dielectric layer, for example, a combination of barrier layer 312, storage layer 314, and tunnel layer 316. The functional layer 310, including the barrier layer 312, the storage layer 314, and the tunnel layer 316, may be formed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

As shown in fig. 3B, a barrier layer 312 may be formed between the memory layer 314 and the sidewalls of the channel hole 300. The blocking layer 312 may be used to block the outflow of charge. In some embodiments, the barrier layer 312 may be a silicon oxide layer or a combination of silicon oxide/silicon nitride/silicon oxide (ONO) layers. In some embodiments, barrier layer 312 comprises a high dielectric constant (high-k) dielectric (e.g., alumina). In some embodiments, the thickness of the barrier layer 312 may be in the range of about 3nm to about 20 nm.

The storage layer 314 may be formed between the tunnel layer 316 and the barrier layer 312. Electrons or holes from the channel layer may tunnel through the tunnel layer 316 to the storage layer 314. The storage layer 314 may store charges (electrons or holes) for a memory operation. The storage or removal of charge in the storage layer 314 may affect the on/off state and/or conduction of the semiconductor channel. The memory layer 314 may include one or more films of materials, including, but not limited to, silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. In some embodiments, the storage layer 314 may comprise a nitride layer formed by using one or more deposition processes. In some embodiments, the thickness of the storage layer 314 may be in a range of about 3nm to about 20 nm.

A tunnel layer 316 may be formed on sidewalls of the storage layer 314. The tunnel layer 316 may be used to tunnel charges (electrons or holes). Tunnel layer 316 may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the tunnel layer 130 may be an oxide layer formed by using a deposition process. In some embodiments, the thickness of the tunnel layer 316 may be in the range of about 3nm to about 20 nm.

In some embodiments, the fabrication process of forming the channel structure further includes forming the channel layer 320 covering sidewalls of the functional layer 310. In some embodiments, the channel layer 320 may be an amorphous silicon layer or a polysilicon layer formed by a thin film deposition process, such as ALD, CVD, PVD, or any other suitable process. In some embodiments, the thickness of the channel layer 320 may be in the range of about 5nm to 20 nm.

In some embodiments, the manufacturing process of forming the channel structure further includes forming a filling structure 330 to cover the channel layer 320 and fill the channel hole 310. In some embodiments, the fill structure 330 may be an oxide layer formed by using any suitable deposition, e.g., ALD, CVD, PVD, etc. In some embodiments, the fill structure 330 may include one or more air gaps.

As shown in fig. 2, the method proceeds to step S6, where a plurality of slits may be formed in the alternating insulator stack layers. As shown in fig. 3C, each slit 400 may extend vertically through alternating insulator stack layers 200 and extend in a substantially straight line between the two arrays of channel structures. The plurality of slits 400 may be formed by forming a shield layer over alternating insulator stack layer 200 and patterning the shield layer using, for example, photolithography to form openings in the patterned shield layer corresponding to the plurality of slits. A suitable etching process, such as a dry etch and/or a wet etch, is then performed to remove the portions of alternating insulator stack layers 200 exposed by the openings until the plurality of slits reveal substrate 100. The shielding layer may be removed after the plurality of slits are formed.

As shown in fig. 2, the method proceeds to step S8, where second dielectric layer 220 in alternating insulator stack layer 200 may be removed to form a plurality of trenches 410. The plurality of trenches 410 may extend in a horizontal direction and may be used as a space for a multi-layered gate structure formed in a subsequent process. It should be noted that the term "horizontal" as used herein means nominally parallel to the substrate lateral surface.

As described above, second dielectric layer 220 in alternating insulator stack layer 200 serves as a sacrificial layer and is removed using any suitable etching process (e.g., isotropic dry or wet etch). The etching process may have a sufficiently high etch selectivity on the material of the second dielectric layer 220 to the material of the first dielectric layer 210 such that the impact of the etching process on the first dielectric layer 210 is minimized. The isotropic dry and/or wet etch may remove the second dielectric layer 220 in various directions to expose the top and bottom surfaces of each first dielectric layer 210. Thus, a plurality of horizontal trenches 410 may be formed between the first dielectric layers 210.

In some embodiments, the second dielectric layer 220 comprises silicon nitride, and the etchant of the isotropic dry etch comprises CF₄、CHF₃、C₄F₈、C₄F₆And CH₂F₂One or more of (a). The isotropic dry etch may have a Radio Frequency (RF) power of less than about 100W and a bias voltage of less than about 10V. In some embodiments, the second dielectric layer 220 comprises silicon nitride and the etchant of the wet etch comprises phosphoric acid.

After removing the second dielectric layer 220, the plurality of slits 400 and the plurality of trenches 410 may be cleaned by using any suitable cleaning process. For example, a phosphoric acid rinsing process may be performed to remove impurities on the inner wall of the trench 410. In some embodiments, the rinse temperature may be in the range of about 100 ℃ to about 200 ℃, and the rinse time may be in the range of about 10 minutes to about 100 minutes. After the cleaning process, the top surface 212 and the bottom surface 214 of the first dielectric layer 210 and the outer sidewall portions of the functional layer 310, which are initially surrounded by the second dielectric layer 220, may be exposed through the plurality of trenches 410.

As shown in fig. 2, the method proceeds to step S10, where an insulating layer may be formed in each trench 410. The insulating layer may serve as a gate dielectric layer for insulating a corresponding word line (i.e., gate) formed by a subsequent process from the adjacent first dielectric layer 210.

In some embodiments, the insulating layer may be formed by filling the horizontal trenches 410 with one or more suitable insulating materials, as shown in fig. 3C. For example, one or more insulating materials may be deposited into horizontal trenches 410 using one or more suitable deposition processes, such as CVD, PVD, and/or ALD. In some embodiments, a recess etch and/or Chemical Mechanical Planarization (CMP) may be used to remove excess insulating material outside of the plurality of trenches 410.

The one or more insulating materials may comprise any suitable material that provides an electrical insulating function. For example, the one or more insulating materials may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium nitride, and the like, and/or any suitable combination thereof. In some embodiments, the plurality of insulating layers may have different insulating materials.

In some embodiments, the insulating layer may have a laminated structure. For example, as shown in fig. 3D, the insulating layer may include a first insulating sublayer 510 covering the top surface 212 and the bottom surface 214 of the first dielectric layer 210 and the outer sidewall portions of the functional layer 310 exposed by the plurality of trenches 410. The insulating layer may further include a second insulating sublayer 520 covering a surface of the first insulating sublayer 510. In some embodiments, the first insulating sublayer 510 may comprise a high dielectric constant (high-k) dielectric (e.g., alumina) and the second insulating sublayer 520 may comprise titanium nitride as a glue layer to prevent subsequent gate layer delamination.

In some other embodiments, the insulating layer may be a single film structure. For example, the insulating layer may include a single high-k dielectric layer (e.g., a titanium nitride film) covering the top surface 212 and the bottom surface 214 of the first dielectric layer 210 and the outer sidewall portions of the functional layer 310 exposed by the plurality of trenches 410. The titanium nitride film may have a thickness in the range of about 1nm to about 10 nm.

As shown in fig. 2, the method proceeds to step S12, wherein a multi-layered gate structure may be formed in each trench 410. A multi-layered gate structure may be formed by filling the horizontal trenches 410 with a suitable gate metal material. As shown in fig. 3D, a gate metal material may fill each horizontal trench 410 to form a conductor layer 530 covering the insulating layer. The conductor layer 530 may provide a base material for subsequently formed word lines (i.e., gates).

The gate metal material may comprise any suitable conductive material, such as tungsten, aluminum, copper, cobalt, or any combination thereof, for forming a word line (i.e., gate). The gate material may be deposited into the horizontal trenches 230 using a suitable deposition method such as CVD, Physical Vapor Deposition (PVD), plasma enhanced CVD (pecvd), sputtering, Metal Organic Chemical Vapor Deposition (MOCVD), and/or ALD. In some embodiments, the conductor layer 530 comprises tungsten formed by CVD.

In some embodiments, after forming the plurality of conductor layers 530, portions of the plurality of conductor layers 530 may be removed. In some embodiments, in order to ensure insulation between the plurality of gates, recess etching may be performed to remove the plurality of conductor layers 530 at portions outside the plurality of trenches 410 and near the plurality of slits 400. As such, a recess of the conductor layer 530 may be formed in each trench 410, as shown in fig. 3E. The remaining portions of the plurality of conductor layers 530 may form a multi-layer gate structure that includes a plurality of gates 540, each gate 540 being sandwiched by an insulating layer.

As shown in fig. 2, the method proceeds to step S14, where a first isolation layer may be formed on sidewalls of the plurality of slits 400. As shown in fig. 3F, the first isolation layer 600 may cover sidewalls of the slit 400, exposed surfaces of the insulating layer, and exposed surfaces of the plurality of gates 540. The first isolation layer 600 may serve to prevent the plurality of gates 540 from being oxidized in a subsequent process. In some embodiments, the thickness of the first isolation layer 600 may be in the range of about 0.1nm to about 10 nm.

The first isolation layer 600 may be formed by depositing a material including, but not limited to, silicon (e.g., polysilicon, single crystal silicon, or amorphous silicon), silicon nitride, silicon oxynitride, aluminum oxide, and/or any combination thereof. The deposition process may be CVD, sputtering, PVD, MOCVD, Low Pressure Chemical Vapor Deposition (LPCVD), Polyatomic Layer Chemical Vapor Deposition (PLCVD), and/or ALD. Since the first isolation layer 600 is formed after the recess etching process of the plurality of conductor layers and has a relatively small thickness, the first isolation layer 600 further includes a plurality of grooves corresponding to the plurality of gate electrodes 540, as shown in fig. 3F.

As shown in fig. 2, the method proceeds to step S16, where a second spacer may be formed on sidewalls of the plurality of slits 400. As shown in fig. 3G, the second isolation layer 700 may cover the first isolation layer 600. The second spacer 700 may be used to provide electrical insulation between the plurality of gates 540 and the conductive walls 800 formed in a subsequent process. The second isolation layer 700 may be formed by a suitable deposition process and a subsequent etching process. For example, a deposition process such as sputtering, PVD, MOCVD, Low Pressure Chemical Vapor Deposition (LPCVD), and/or ALD, etc. may be performed to form the second isolation layer 700. The material 700 of the second isolation layer may comprise any suitable insulating material different from the material of the first isolation layer 600, such as silicon oxide or the like.

It should be noted that in one embodiment, first isolation layer 600 is a silicon film and second isolation layer 700 is a silicon oxide film. In this case, during the deposition process to form the silicon oxide film, part or all of the silicon film may be oxidized to silicon oxide. Accordingly, a part or the whole of the first isolation layer 600 may be converted into the second isolation layer 700. That is, a silicon oxide layer may be formed to cover the sidewalls of each slit 400, the surface of the insulating layer, and the metal gate in each trench 410.

After the first and second isolation layers 600 and 700 are formed, an etching process may be performed to remove portions of the first and second isolation layers 600 and 700 at the bottom of each slit 400 to expose the substrate 100. As such, the second isolation layer 700 may be formed on the sidewalls of the plurality of slits 400.

As shown in fig. 2, the method proceeds to step S18, where conductive walls may be formed in each slit 400. As shown in fig. 3G, the conductive wall 800 may be sandwiched between the second isolation layers 700 in each slot 400. In some embodiments, the conductive walls 800 may be formed by depositing any suitable conductive material, such as a metallic material, including tungsten, aluminum, copper, polysilicon, a metal silicide, and/or any combination thereof. The conductive material may be deposited into the slots 400 using a suitable deposition method such as CVD, Physical Vapor Deposition (PVD), plasma enhanced CVD (pecvd), sputtering, Metal Organic Chemical Vapor Deposition (MOCVD), and/or ALD. In some embodiments, the conductive walls 800 comprise tungsten formed by CVD.

In some embodiments, a doped region (not shown) may be formed in the substrate 100 below each slit 400, for example, by ion implantation and/or thermal diffusion through the slit 400, prior to forming the conductive walls 800. After forming the plurality of conductive walls 800, a lower end of each conductive wall 800 may be in contact with a corresponding doped region. It should be appreciated that, according to some embodiments, the doped regions may be formed in an earlier manufacturing stage, for example, prior to forming the multi-layer gate structure.

Accordingly, methods for forming gate structures of 3D memory devices are provided in some embodiments according to the present disclosure. In the disclosed method, after forming the multi-layered gate structure and before forming the silicon oxide layer on the sidewalls of the slits, a silicon film may be formed to cover the exposed surfaces of the multi-layered gate structure to prevent the exposed surfaces of the multi-layered gate structure from being oxidized during deposition of the silicon oxide layer. Therefore, electric leakage between the multi-layer gate structure and the conductive wall in the slit can be eliminated, and the product yield of the 3D storage device can be improved.

The method for forming a gate structure of a 3D memory device may include: forming an alternating insulator stack layer comprising a plurality of dielectric layer pairs on a substrate, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a plurality of slits, each slit passing vertically through the alternating insulator stack layers and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating insulator stack layer through a plurality of slits to form a plurality of trenches; forming a conductor layer in each of the plurality of trenches; forming a first isolation layer on sidewalls of the plurality of slits to cover the conductor layer to prevent the conductor layer from being oxidized; forming a second isolation layer on a surface of the first isolation layer, the second isolation layer being of a different material from the first isolation layer; and depositing a conductive material into the slots to form a plurality of conductive walls, wherein the plurality of conductive walls are insulated from the conductor layer.

In some embodiments, the first insulating sub-layer is formed by depositing a first material comprising aluminum oxide; and forming a second insulating sub-layer by depositing a second material comprising titanium nitride.

The foregoing description of the specific embodiments will so fully reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. Boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The summary and abstract sections may set forth one or more, but not necessarily all exemplary embodiments of the present disclosure as contemplated by the inventors, and are, therefore, not intended to limit the disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method of forming a three-dimensional (3D) NAND memory device, comprising:

forming an alternating insulator stack comprising a plurality of dielectric layer pairs on a substrate, each dielectric layer pair of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer;

forming a plurality of slits, each slit passing vertically through the alternating insulator stack and extending in a horizontal direction;

removing the plurality of second dielectric layers in the alternating insulator stack layers through the plurality of slits to form a plurality of trenches;

forming a conductor layer in each of the plurality of trenches;

forming a first isolation layer on sidewalls of the plurality of slits to cover the conductor layer to prevent the conductor layer from being oxidized, wherein the first isolation layer has a plurality of grooves;

forming a second isolation layer on a surface of the first isolation layer, the second isolation layer being of a different material than the first isolation layer; and

depositing a conductive material into the slots to form a plurality of conductive walls, wherein the plurality of conductive walls are insulated from the conductor layer.

2. The method of claim 1, wherein each dielectric layer pair of the plurality of dielectric layer pairs is formed from a silicon oxide layer having a thickness in a range of about 10nm to about 150nm and a silicon nitride layer having a thickness in a range of about 10nm to about 150 nm.

3. The method of claim 1, further comprising:

forming a plurality of channel structures, each channel structure passing vertically through the alternating insulator stack layers;

wherein each slit of the plurality of slits extends horizontally between the plurality of channel structures.

4. The method of claim 1, further comprising:

after forming the plurality of slits, forming a plurality of doped regions in the substrate below the slits such that each conductive wall is in contact with a respective doped region.

5. The method of claim 1, further comprising:

forming a film comprising silicon, silicon nitride, silicon oxynitride, or aluminum oxide as the first spacer layer, the film having a thickness in a range from about 0.1nm to about 10 nm.

6. The method of claim 1, further comprising:

forming a silicon film as the first isolation layer;

forming a silicon oxide film as the second isolation layer; and

in the process of forming the second isolation layer, at least a part of the silicon film is oxidized to silicon oxide.

7. The method of claim 3, wherein forming the plurality of channel structures comprises:

forming a channel hole extending vertically through the alternating insulator stack layers;

forming a functional layer on sidewalls of the channel hole; and

and forming a channel layer covering the side wall of the functional layer.

8. The method of claim 7, wherein forming the functional layer comprises:

forming a blocking layer on the sidewall of the channel hole for blocking outflow of charges;

forming a storage layer on a surface of the blocking layer for storing charges during operation of the 3D memory device; and

a tunneling layer is formed on a surface of the storage layer for tunneling charges.

9. The method of claim 1, further comprising:

forming an insulating layer in the plurality of trenches before forming the conductor layer in the plurality of trenches.

10. The method of claim 9, wherein forming the insulating layer comprises:

forming a first insulating sub-layer covering top and bottom surfaces of the plurality of first dielectric layers and outer sidewall portions of the functional layer exposed by the plurality of trenches; and

forming a second insulating sub-layer having a thickness in a range of about 1nm to about 10nm to cover the first insulating sub-layer.

11. The method of claim 10, wherein:

the first insulating sub-layer is formed by depositing a first material comprising aluminum oxide; and

the second insulating sub-layer is formed by depositing a second material comprising titanium nitride.

12. The method of claim 9, further comprising:

performing a phosphoric acid rinsing process to clean the plurality of trenches before forming the insulating layer, wherein a rinsing temperature of the phosphoric acid rinsing process is in a range of about 100 ℃ to about 200 ℃, and a rinsing time of the phosphoric acid rinsing process is in a range of about 10 minutes to about 100 minutes.

13. The method of claim 1, wherein forming the conductor layer comprises:

filling the plurality of trenches with a conductive material; and

removing portions of the conductive material to form a plurality of separate gates, each gate of the plurality of separate gates being located in a respective trench.

14. The method of claim 1, wherein forming the first isolation layer comprises:

performing a multi-atomic layer chemical vapor deposition process or an atomic layer deposition process to form the first isolation layer.

15. The method of claim 13, wherein forming the first isolation layer comprises:

forming the first isolation layer to cover the sidewalls of the plurality of slits, exposed surfaces of the insulating layer, and exposed surfaces of the conductor layer.

16. The method of claim 13, wherein forming the first isolation layer comprises:

forming the first isolation layer having a plurality of recesses, each recess corresponding to a separate gate.

17. The method of claim 1, wherein forming the alternating insulator stack layers comprises:

forming the alternating insulator stack layers in a vertical direction to a thickness greater than 1000 nm.

18. The method of claim 1, wherein forming the plurality of conductive walls comprises:

depositing a material comprising tungsten into the plurality of slots to form the plurality of conductive walls.

19. A three-dimensional (3D) NAND memory device, comprising:

an alternating insulator/conductor stack comprising a plurality of insulator/conductor layer pairs on a substrate, each insulator/conductor layer pair of the plurality of insulator/conductor layer pairs comprising a dielectric layer and a conductor layer;

a plurality of slots, each slot passing vertically through the alternating insulator/conductor stack and extending in a horizontal direction;

a first isolation layer on sidewalls of the plurality of slits to cover the conductor layer to prevent the conductor layer from being oxidized, wherein the first isolation layer has a plurality of grooves;

a second isolation layer on a surface of the first isolation layer, the second isolation layer being of a different material than the first isolation layer; and

a conductive wall sandwiched by the second isolation layer in each slot, wherein the conductive wall is insulated from the conductor layers of the alternating insulator/conductor stack.

20. The apparatus of claim 19, wherein:

each of the dielectric layers is a silicon oxide layer having a thickness in a range from about 10nm to about 150 nm;

each of the conductor layers is a tungsten layer having a thickness in a range of about 10nm to about 150 nm; and

the conductive wall comprises tungsten.

21. The apparatus of claim 19, further comprising:

a plurality of channel structures, each channel structure passing vertically through the alternating insulator/conductor stack;

22. The apparatus of claim 19, further comprising:

a plurality of doped regions in the substrate below the slots, wherein the conductive wall is in contact with a corresponding doped region in each slot.

23. The apparatus of claim 19, wherein:

the first isolation layer is a film including silicon, silicon nitride, silicon oxynitride, or aluminum oxide; and

the second isolation layer is a silicon oxide film.

24. The apparatus of claim 19, wherein:

the first spacer layer has a thickness in a range from about 0.1nm to about 10 nm.

25. The apparatus of claim 19, wherein each channel structure of the plurality of channel structures comprises:

a channel hole extending vertically through the alternating insulator/conductor stack;

a functional layer on sidewalls of the channel hole; and

a channel layer covering a sidewall of the functional layer.

26. The apparatus of claim 25, wherein the functional layer comprises:

a blocking layer on the sidewalls of the channel hole, the blocking layer configured to block an outflow of charges;

a storage layer on a surface of the blocking layer, the storage layer configured to store charge during operation of the 3D storage device; and

a tunneling layer on a surface of the storage layer, the tunneling layer configured to tunnel charges.

27. The apparatus of claim 25, further comprising:

an insulating layer between each of the dielectric layers and each of the conductor layers.

28. The apparatus of claim 27, wherein:

the insulating layer is located between the conductor layer and the functional layer.

29. The apparatus of claim 28, wherein the insulating layer comprises:

a first insulating sublayer covering top and bottom surfaces of the plurality of dielectric layers and an outer sidewall portion of the functional layer; and

a second insulating sublayer overlying the first insulating sublayer and having a thickness ranging from about 1nm to about 10 nm.

30. The apparatus of claim 29, wherein:

the first insulating sublayer comprises aluminum oxide; and

the second insulating sublayer comprises titanium nitride.

31. The apparatus of claim 19, wherein:

each recess corresponds to a conductor layer sandwiched between two dielectric layers.

32. The apparatus of claim 19, wherein:

the alternating insulator/conductor stack has at least 64 insulator/conductor layer pairs and has a thickness greater than 1000nm in the vertical direction.