CN110120922A - A kind of data interaction Network Management System and method based on FPGA - Google Patents
A kind of data interaction Network Management System and method based on FPGA Download PDFInfo
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- CN110120922A CN110120922A CN201910398813.3A CN201910398813A CN110120922A CN 110120922 A CN110120922 A CN 110120922A CN 201910398813 A CN201910398813 A CN 201910398813A CN 110120922 A CN110120922 A CN 110120922A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9005—Buffering arrangements using dynamic buffer space allocation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9026—Single buffer per packet
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E30/00—Energy generation of nuclear origin
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- Data Exchanges In Wide-Area Networks (AREA)
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Abstract
The invention discloses a kind of data interaction Network Management System and method based on FPGA, the present invention system include DPRAM interface unit, data handling unit, pointer resolution unit and N number of transceiver based on FPGA building, and N is the positive integer more than or equal to 1；Wherein, the DPRAM interface unit, data handling unit and pointer resolution unit communicate to connect two-by-two, and the data handling unit is connect with transceiver communications；The system carries out data interaction by DPRAM interface unit and outside DPRAM, and realizes the data interaction with external hardware by transceiver.The present invention realizes that pointer and Dynamic data exchange, buffer area and transceiver are independent, and the interactive interface between each functional module is simply clear, by the dynamic access to DPRAM and is written and read according to the state of module itself, does not depend on the control of CPU.It improves the flexibility of data transmit-receive while reducing consumption of the communication task to CPU runing time.
Description
Technical field
The present invention relates to nuclear safe level digital Control Technology fields, and in particular to a kind of data interaction net based on FPGA
Network management system and method.
Background technique
In CPU+FPGA architecture system, the data interactive mode of CPU and FPGA are most important to whole system.Due to
CPU and FPGA asynchronous operation, therefore buffering is essential.In the design of nuclear power plant's I&C system, user can be according to oneself
Demand carries out configuration, realizes that configuration has been highly developed technology in CPU, but still immature at present in FPGA,
Therefore it needs to fully consider the flexibility interacted with CPU in FPGA design.Nuclear power plant's I&C system belongs to safety level product,
CPU to communication have specific time restriction, in the data integrity of communication the considerations of to the packet length of communication carried out limitation,
It is also restricted to the packet length of communication to be limited to own resource by FPGA simultaneously.Therefore the communication data that FPGA needs to issue CPU
It is sent in batches.
For the FPGA data buffer management of CPU+FPGA architecture system.Currently, more generally using fixed length
Spend the method for transmitting-receiving.The transmitting-receiving of regular length needs FPGA firmware that can support the maximum packet length under any application scenarios, because
This is often that be difficult to realize or resource consumption is very big with a FPGA firmware version.
Summary of the invention
In order to solve above-mentioned technical problem of the existing technology, the present invention provides the one kind to solve the above problems to be based on
The data interaction Network Management System and method of FPGA；The present invention is independent using pointer and Dynamic data exchange, buffer area and transceiver
Mode interact.The present invention may be implemented to send data to the same destination address in batches in a CPU cycle of operation, delay
The data forwarding that area dynamically distributes, low CPU is occupied is rushed, to improve the flexibility of data transmit-receive while reduce communication task pair
The consumption of CPU runing time.
The present invention is achieved through the following technical solutions:
A kind of data interaction Network Management System based on FPGA, the system include the DPRAM interface based on FPGA building
Unit, data handling unit, pointer resolution unit and N number of transceiver, N are the positive integer more than or equal to 1；Wherein, the DPRAM
Interface unit, data handling unit and pointer resolution unit communicate to connect two-by-two, the data handling unit and transceiver communications
Connection；The system carries out data interaction by DPRAM interface unit and outside DPRAM, and hard with outside by transceiver realization
The data interaction of part, without direct data interaction between the system and CPU.
Preferably, the DPRAM interface unit carries out data interaction for local communication and outside DPRAM, makes standard
EMIF timing and local read-write sequence are mutually converted.
Preferably, the pointer resolution unit obtains the pointer data of each transceiver by DPRAM interface unit, according to
The destination address of pointer obtains the status information of corresponding transceiver, and the status information judgement of incorporating transceiver and pointer generates read-write
The operation of order.
Preferably, the transceiver is embedded in each channel, and transceiver provides the interactive interface with external hardware, simultaneously
It is responsible for internal data communication, data synchronization and clock recovery.
Preferably, which uses polling mechanism, when there are ready data then to be carried, when there is no be ready to
Data be then polled to next transceiver and operated.
Preferably, data buffer zone is set in the data handling unit.
Preferably, the data buffer zone can dynamically distribute, and be counted according to the pointer information that pointer resolution unit obtains
According to the mapping of buffer area and transceiver, the dynamic allocation of data buffer zone are realized, can be realized and receive buffer area and transmission buffering
The corresponding transceiver of area's free switching, multiple buffering area and a buffer area correspond to multiple transceivers.
Preferably, the external DPRAM includes pointer area and data field；The pointer area includes transceiver information, data
First address, data length and status information；The data field includes 2 data reception areas and 1 data transmission interval；CPU is only needed
Write-in and more new state in DPRAM, subsequent data forwarding carry out pointer and data between each modular unit of system
Mapping, carrying and long packet decompose.
On the other hand, the invention also provides a kind of data interaction network management based on FPGA, this method comprises:
Step 1, building such as the described in any item data interaction Network Management System based on FPGA of claim 1-8；
Step 2, the pointer resolution unit obtain the pointer data of each transceiver by DPRAM interface unit, according to
The destination address of pointer obtains the status information of corresponding transceiver, and the status information judgement of incorporating transceiver and pointer generates read-write
Command operation；
Step 3, the Read-write Catrol information that the data handling unit is provided according to pointer parsing module, is connect by DPRAM
Mouth unit accesses to external DPRAM, and carries out selection control to data flow, completes each channel transceiver and outside
Data mapping, carrying and the long packet of DPRAM decomposes.
Preferably, in this method, without direct data interaction interface between FPGA and CPU, CPU issue data no longer by
The limitation of FPGA transmission situation, it is only necessary to operate DPRAM, there is new data just directly to update data field and state area, FPGA operation
It only needs to determine whether ready data and state when some transceiver.
The present invention has the advantage that and the utility model has the advantages that
It 1, can the present invention is based on the mode that pointer and Dynamic data exchange, buffer area and the independent mode of transceiver interact
To reduce consumption of the data forwarding to CPU runing time, larger data packet length can be supported, communication delay is low, and CPU issues number
It entire issue process according to not sent situation by FPGA and limit and does not block.
2, the interactive interface between each functional module of the present invention is simply clear, according to the state of module itself by pair
The dynamic access of DPRAM is simultaneously written and read, and does not depend on the control of CPU.A CPU operation week may be implemented in this method simultaneously
In batches to the same destination address sends data, buffer area dynamically distributes in phase, so that the flexibility for improving data transmit-receive is same
When reduce consumption of the communication task to CPU runing time.
3, data buffering ability can be improved in the present invention, reduces resource overhead.It, can in the higher system of requirement of real-time
To guarantee the real-time of system communication.There are in the system of a variety of traffic capacity demands, can be led to each port of separate configurations
Believe capacity, does not need to improve whole traffic capacity requirement reduction resource overhead.Support the application method of single port multiple buffer,
That is particular port is repeatedly received and dispatched in a sending cycle.It can effectively improve nuclear safe level DCS data communication
Reliability and efficiency.
Detailed description of the invention
Attached drawing described herein is used to provide to further understand the embodiment of the present invention, constitutes one of the application
Point, do not constitute the restriction to the embodiment of the present invention.In the accompanying drawings:
Fig. 1 is system structure diagram of the invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below with reference to embodiment and attached drawing, to this
Invention is described in further detail, and exemplary embodiment of the invention and its explanation for explaining only the invention, are not made
For limitation of the invention.
Embodiment 1
The present embodiment proposes a kind of data interaction Network Management System based on FPGA, as shown in Figure 1, the system includes
DPRAM interface unit, data handling unit, pointer resolution unit and transceiver based on FPGA building.
In the present embodiment, the transceiver be it is N number of, as shown in Figure 1.Wherein, N is the positive integer more than or equal to 1.
In the present embodiment, the DPRAM interface unit, data handling unit and pointer resolution unit communicate to connect two-by-two,
The data handling unit is connect with transceiver communications；As shown in Figure 1, shown DPRAM interface unit, data handling unit and referring to
Needle resolution unit constitutes a loop network, and the loop network and N number of transceiver constitute the Star Network structure of 1 couple of N.
In the present embodiment, the DPRAM interface unit carries out data interaction with outside DPRAM for local, makes standard
EMIF timing and local read-write sequence are mutually converted.
The present embodiment separates port with buffer area, and the quantity of port, each port can be defined according to application scenarios
Buffer pool size；The present invention constructs Star Network structure, is sent using Cell round Robin, avoids the mouth of big data quantity from blocking communication and connects
Mouth causes the communication delay of whole system to increase.
In the present embodiment, the pointer resolution unit obtains the pointer data of each transceiver by DPRAM interface unit,
The status information of corresponding transceiver is obtained according to the destination address of pointer, the status information judgement of incorporating transceiver and pointer generates
The operation of read write command.
In the present embodiment, the transceiver is embedded in each channel, and transceiver provides the interactive interface with external hardware,
It is responsible for internal data communication, data synchronization and clock recovery simultaneously.
In the present embodiment, which carries out data interaction by DPRAM interface unit and outside DPRAM, and passes through transmitting-receiving
Device realizes the data interaction with external hardware, without direct data interaction between the system and CPU.
In the present embodiment, polling mechanism is used in the system, when there are ready data then to be carried, when being not present
Ready data are then polled to next transceiver and are operated.
In the present embodiment, data buffer zone is set in the data handling unit.
In the present embodiment, the data buffer zone can be dynamically distributed, according to pointer resolution unit obtain pointer information into
The dynamic allocation of data buffer zone are realized in the mapping of row data buffer zone and transceiver, be can be realized and are received buffer area and transmission
The corresponding transceiver of buffer area free switching, multiple buffering area and a buffer area correspond to multiple transceivers.
In the present embodiment, the external DPRAM includes pointer area and data field；The pointer area include transceiver information,
The configuration informations such as data first address, data length and status information；Specific configuration information is as shown in the table:
| Title | Description |
| PORT | Present communications channel type and slot position information |
| Cycle | The data reception/transmission period |
| Ptr | Data reception/transmission buffer pointer (first address) |
| Len | Data reception/transmission buffer length |
| Status | Data reception/transmission buffer state |
| FSEQN | Frame number in data receiver buffer area |
| Link_Status | Communication link state |
The data field includes 2 data reception area Bx_Buf_n_1 and Bx_Buf_n_2 and 1 data transmission interval Tx_
Buf_n；Wherein, two data reception areas equal 1 contain data field and diagnostic region, and data transmission interval contains only data field.
CPU need to only be written and more new state in DPRAM, subsequent data forwarding between each modular unit of system into
Mapping, carrying and the long packet of line pointer and data decompose.
The data interaction Network Management System based on FPGA of the present embodiment is by pointer and Dynamic data exchange, buffer area and transmitting-receiving
The method that the independent mode of device interacts includes pointer parsing, reiving/transmitting state update, data transmit-receive, transceiver selection function.
The main mapping for completing buffer area and transceiver of pointer parsing.The function is realized by pointer resolution unit.
Reiving/transmitting state updates the main update completed data and send state and data receiving state, wherein data receiving state
Update includes writing data mode, writing data completion status, read data mode and read data completion status.CPU only need to be in DPRAM
Write-in and more new state.
Data transmit-receive mainly complete data from buffer area to transceiver and transceiver to buffer area data handling work.
Transceiver selection selects the flow direction of data according to the mapping relations of buffer area and transceiver.
In the present embodiment, each functional unit is realized independently of each other, and the interaction between data is not in the period for relying on CPU, pole
Consumption of the data forwarding to the CPU cycle of operation is reduced greatly；And the forwarding of packet long for data, CPU need to only write in DPRAM
Enter and more new state, the forwarding of subsequent data only need the mapping of progress pointer and data between system modules to carry
The decomposition wrapped with length, and the mechanism of poll is used in star-shaped network structure between each channel, there are ready data to carry, nothing
It is then polled to next channel to be operated, effectively reduces communication delay.Using this star-shaped network structure FPGA and CPU it
Between without direct data interaction interface, CPU issue data not by FPGA send situation limited, only need to operate DPRAM, have
New data just directly updates data field and state area, need to only determine whether when FPGA operates this channel ready data with
State.
In the present embodiment, Network Management System realizes following operation: 1) DPRAM interface is responsible for local communication and outside
DPRAM is interacted, and converts standard EMIF timing and local read-write sequence mutually.2) pointer parsing part is connect by DPRAM
Mouth obtains the pointer data of each collocation channel, and the status information of corresponding channel is obtained according to the destination address of pointer, in conjunction with logical
The judgement of the status information of road and pointer generates the operation of read write command；3) data transfer module is provided according to pointer parsing module
Read-write Catrol information visits the data field of external DPRAM, state area, address and length information by DPRAM interface
It asks, and selection control is carried out to data flow, complete the data mapping of each channel transceiver and outside DPRAM, carry and unpack
Processing etc..4) it includes a transceiver, transceiver that transceiver module, which is built-in i.e. each operating walk way in each channel,
Interactive interface with external hardware, while the algorithm control and data synchronization, clock of interior liabilities data communication data are provided
Restore etc..
By constructing data interaction Network Management System framework as described in Figure 1, pointer and Dynamic data exchange may be implemented, delay
Rush that area and transceiver are independent, the interactive interface between each functional module is simply clear, according to the state of module itself by pair
The dynamic access of DPRAM is simultaneously written and read, and does not depend on the control of CPU.A CPU operation week may be implemented in this method simultaneously
In batches to the same destination address sends data, buffer area dynamically distributes in phase, so that the flexibility for improving data transmit-receive is same
When reduce consumption of the communication task to CPU runing time.
Embodiment 2
The present embodiment proposes a kind of data interaction network management based on FPGA, this method comprises:
Step 1 constructs the data interaction Network Management System as described in example 1 above based on FPGA；
Step 2, the pointer resolution unit obtain the pointer data of each transceiver by DPRAM interface unit, according to
The destination address of pointer obtains the status information of corresponding transceiver, and the status information judgement of incorporating transceiver and pointer generates read-write
Command operation；
Step 3, the Read-write Catrol information that the data handling unit is provided according to pointer parsing module, is connect by DPRAM
Mouth unit accesses to external DPRAM, and carries out selection control to data flow, completes each channel transceiver and outside
Data mapping, carrying and the long packet of DPRAM decomposes.
In the present embodiment, without direct data interaction interface between FPGA and CPU, CPU issues data no longer by FPGA
Send the limitation of situation, it is only necessary to operate DPRAM, there is new data just directly to update data field and state area, FPGA operation is a certain
It only needs to determine whether ready data and state when a transceiver.
The present embodiment is interacted using pointer and Dynamic data exchange, buffer area and the independent mode of transceiver, according to pointer
Information carries out the mapping of data buffer zone and transceiver, and the dynamic allocation of buffer area may be implemented, can be corresponded to multiple buffering area
One transceiver, a buffer area correspond to multiple transmitting-receivings, receive buffer area and send buffer area free switching.It may be implemented one
Turn in batches to the data that the same destination address sends data, buffer area dynamically distributes, low CPU is occupied in a CPU cycle of operation
Hair, to improve the flexibility of data transmit-receive while reduce consumption of the communication task to CPU runing time.
It should be understood by those skilled in the art that, embodiments herein can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the application
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the application, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The application is referring to method, the process of equipment (system) and computer program product according to the embodiment of the present application
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of data interaction Network Management System based on FPGA, which is characterized in that the system includes being constructed based on FPGA
DPRAM interface unit, data handling unit, pointer resolution unit and N number of transceiver, N are the positive integer more than or equal to 1；Wherein,
The DPRAM interface unit, data handling unit and pointer resolution unit communicate to connect two-by-two, the data handling unit and receipts
Send out device communication connection；The system carries out data interaction by DPRAM interface unit and outside DPRAM, and is realized by transceiver
With the data interaction of external hardware, without direct data interaction between the system and CPU.
2. a kind of data interaction Network Management System based on FPGA according to claim 1, which is characterized in that described
DPRAM interface unit carries out data interaction for local communication and outside DPRAM, makes standard EMIF timing and local read-write sequence
Mutually conversion.
3. a kind of data interaction Network Management System based on FPGA according to claim 1, which is characterized in that the finger
Needle resolution unit obtains the pointer data of each transceiver by DPRAM interface unit, according to the acquisition pair of the destination address of pointer
The status information of transceiver is answered, the status information judgement of incorporating transceiver and pointer generates the operation of read write command.
4. a kind of data interaction Network Management System based on FPGA according to claim 1, which is characterized in that the receipts
Hair device is embedded in each channel, and transceiver provides the interactive interface with external hardware, while being responsible for internal data communication, data
Synchronous and clock recovery.
5. a kind of data interaction Network Management System based on FPGA according to claim 1-4, feature exist
Polling mechanism is used in, the system, when there are ready data then to be carried, when there is no ready data then polls
It is operated to next transceiver.
6. a kind of data interaction Network Management System based on FPGA according to claim 5, which is characterized in that the number
According to data buffer zone is arranged in handling unit.
7. a kind of data interaction Network Management System based on FPGA according to claim 6, which is characterized in that the number
It can be dynamically distributed according to buffer area, according to the pointer information progress data buffer zone of pointer resolution unit acquisition and reflecting for transceiver
It penetrates, realizes the dynamic allocation of data buffer zone, can be realized and receive buffer area and transmission buffer area free switching, multiple buffering area
A corresponding transceiver and a buffer area correspond to multiple transceivers.
8. a kind of data interaction Network Management System based on FPGA according to claim 1-4, feature exist
In the external DPRAM includes pointer area and data field；The pointer area includes that transceiver information, data first address, data are long
Degree and status information；The data field includes 2 data reception areas and 1 data transmission interval；CPU need to only be written in DPRAM
More new state, subsequent data forwarding carry out mapping, carrying and the length of pointer and data between each modular unit of system
Packet decomposes.
9. a kind of data interaction network management based on FPGA, which is characterized in that this method comprises:
Step 1, building such as the described in any item data interaction Network Management System based on FPGA of claim 1-8；
Step 2, the pointer resolution unit obtains the pointer data of each transceiver by DPRAM interface unit, according to pointer
Destination address obtain the status information of corresponding transceiver, the status information judgement of incorporating transceiver and pointer generates read write command
Operation；
Step 3, the Read-write Catrol information that the data handling unit is provided according to pointer parsing module pass through DPRAM interface list
Member accesses to external DPRAM, and carries out selection control to data flow, completes each channel transceiver and outside DPRAM
Data mapping, carry and long packet decomposes.
10. a kind of data interaction network management based on FPGA according to claim 9, which is characterized in that the party
In method, without direct data interaction interface between FPGA and CPU, CPU issues data and is no longer limited by FPGA transmission situation,
It only needs to operate DPRAM, having new data, just directly update data field and state area, FPGA only need when operating some transceiver
Determine whether ready data and state.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112235163A (en) * | 2020-10-21 | 2021-01-15 | 中国核动力研究设计院 | Method, device, equipment and medium for preventing data from being blocked for FPGA (field programmable Gate array) architecture |
| CN112363975A (en) * | 2020-10-27 | 2021-02-12 | 国核自仪系统工程有限公司 | Interaction method and interaction system for configuration software and FPGA |
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