CN110096384B - High-reliability aerospace data and intermediate variable protection method - Google Patents

Abstract

The invention discloses a method for protecting high-reliability space data and intermediate variables, which mainly solves the problem that the space data and the intermediate variables are not completely protected in the prior art, and comprises the following implementation steps: 1) constructing a generating matrix and a check matrix; 2) acquiring space data or intermediate variables as original data and calculating original check data according to the generated matrix; 3) storing the original check data in a register or a memory; 4) reading the final check data from the register or memory and calculating a syndrome; 5) judging whether the final check data is in error; 6) and correcting the error bit of the final check data to obtain the recovered data equal to the original data or give an error detection mark. The invention adopts 40-bit check data to carry out error correction and detection operation on 32-bit intermediate variables and aerospace data, ensures the correctness of the data, can obtain higher code rate, improves the utilization rate of storage space, and can be used for FPGA on-chip registers, on-chip memories and external memories in aerospace environment.

Description

High-reliability aerospace data and intermediate variable protection method

Technical Field

The invention belongs to the technical field of space electronics, and further relates to a method for protecting space data and intermediate variables, which can be used for an FPGA on-chip register, an on-chip memory and an external memory in a space environment.

Background

Because a communication system in the aerospace environment mostly adopts a self-defined data frame format for data transmission, and interfaces also have a multi-purpose aerospace special data interface, standard ground network data processing equipment is difficult to adopt. The FPGA is a gate array with programmable capability, a deployed program can be repeatedly erased and programmed, and the FPGA is very suitable for an aerospace communication system. However, the intensity of various types of radiation in the aerospace environment is greater than that in the ground environment, and the single event upset SEU phenomenon is easy to occur in the storage unit of the FPGA, so that the logic state of the device is abnormally changed, and further the operation of the whole program is abnormal.

In order to solve the SEU problem, a backup method is often used to ensure the correctness of data, but the backup inevitably increases the circuit scale and the storage scale to the device scale. The spacecraft has certain limits on the volume and weight of the equipment loaded on the spacecraft, so that the SEU problem is obviously impractical to solve in a backup mode. With the continuous development of error detection and correction EDAC technology, error correction codes are adopted to find errors in data and determine and correct single event upset bit positions in the data, so that the method becomes a practical method capable of effectively solving the SEU problem. According to the detection of the SEU phenomenon by scholars at home and abroad, for a memory chip, multi-bit inversion of bytes or words is not found in a short time, so that data errors can be effectively corrected and checked by adopting an error correcting code with the capability of correcting one bit and detecting two bits.

The design and simulation of a Hamming code compiler are provided in the journal of Fujian computer (2018, 03 (3): 134-. However, most of data bit widths of internal data processing of devices such as switches in a communication system are 32 bits or higher, taking 32-bit data as an example, if (7,4) hamming codes are used for error correction and detection, 24 bits of supervision bits are needed, the code rate is too low, and storage space and system processing capacity are greatly wasted. Xuezhen et al, national defense science and technology, proposed a 32-bit data error correction circuit design (2010, 07 (2): 67-70) based on Hamming code in the journal space electronic technology, adopting (38, 32) to shorten Hamming code to carry out error correction and detection on data in a 32-bit SRAM memory on an FPGA, but not protecting intermediate variables in the program running process on the FPGA, because the intermediate variables are stored in a register, when the register has SEU phenomenon, the numerical values of the intermediate variables can also generate unpredictable errors, and the numerical value errors of the intermediate variables easily cause the problems of program blocking and even equipment stopping running, finally making a spacecraft communication system paralyzed.

Disclosure of Invention

The invention aims to provide a method for protecting space data and intermediate variables to ensure the stable operation of a spacecraft communication system and the correctness of data transmission in a communication network aiming at the defects of the prior art.

In order to achieve the above purpose, the invention is realized as follows:

(1) construction of a 32 × 40 generator matrix G ═ I₃₂ B^T]In which I₃₂Is a 32-degree identity matrix, B is a matrix of 8 rows and 32 columns, each column of which is an 8-bit binary code of an element in a set P, wherein P is a set of positive integers greater than or equal to 3, less than or equal to 255, and not equal to 4, 8, 16, 32, 64, 128, B^TIs the transpose of matrix B;

(2) construction of a check matrix H of size 8 × 40 ═ B I₈]In which I₈Is an 8 th order identity matrix;

(3) acquiring space data needing to be stored sent to an FPGA by space equipment or intermediate variables needing to be stored in the running process of a program on the FPGA as original data D;

(4) calculating original check data according to the original data D and the generating matrix G: c ═ D × G;

(5) judging the type of the original check data C: if C is an intermediate variable, executing (6), and if C is space data to be written into an on-chip or off-chip memory, executing (7);

(6) storing original check data C into a register L with the bit width of 40, and executing (9);

(7) acquiring a storage space address S to be written in by original check data C, and executing (8);

(8) outputting the address S to an address bus of the memory, simultaneously outputting the original check data C to a 40-bit data bus of the memory, and pulling up the write enable of the memory by one clock, and then executing (9);

(9) reading final check data C' in a register or a memory;

(10) calculating a syndrome according to the final check data C' and the check matrix H: j ═ H × C';

(11) judging the value of a syndrome J, if the value of the J is 0, then the final check data is correct, executing (13), if the value of the J is equal to the value of the ith column from the left in the matrix H, and i is more than or equal to 1 and less than or equal to 40, then a bit error exists in the final check data, executing (12), otherwise, executing (14);

(12) judging whether i is less than 33, if so, turning the ith bit value from the left of C' to correct errors, and executing (13), otherwise, directly executing (13);

(13) intercepting the 1 st to 32 th bits from the left of the C ', forming a numerical value with the bit width of 32 bits as recovery data D ', and outputting the recovery data D ' to other space equipment or for running an FPGA program;

(14) an error detection flag is generated indicating that uncorrectable multi-bit errors occur in the current space data or intermediate variables.

Compared with the prior art, the invention has the following advantages:

firstly, the error correction and detection operations are carried out on the intermediate variables in the on-chip register of the FPGA, the data in the on-chip RAM and the data in the off-chip memory, so that the correctness of the data is ensured, and the stability of the program running process and the correctness of the data transmitted in a communication network are further ensured.

Secondly, the error correction and detection operation is carried out on 32-bit original data by adopting 40-bit check data, a higher code rate can be obtained, the lengths of the original data and the check data are both an integer number of bytes, the complexity of a program for calculating the check data and the syndrome is reduced, and the utilization rate of a storage space is also improved.

Drawings

FIG. 1 is a flow chart of an implementation of the present invention.

Detailed Description

The present invention is described in further detail below with reference to the attached drawings.

Referring to fig. 1, the specific implementation steps of the present invention are as follows.

Step 1, constructing a generating matrix G.

The generator matrix G constructed in this step has a size of 32 × 40 and has the formula G ═ I₃₂ B^T]In which I₃₂Is a 32 th order identity matrix, expressed as:

in the formula, all diagonal elements are 1, and all the other elements except the diagonal elements are 0.

B is a matrix of 8 rows and 32 columns, each of which is an 8-bit binary code of an element in a set P, P being a set of positive integers greater than or equal to 3, less than or equal to 255, and not equal to 4, 8, 16, 32, 64, 128, B^TIs the transpose of matrix B.

The rule matrix B may have a plurality of specific expressions, one of which is as follows:

and 2, constructing a check matrix H.

The check matrix H constructed in this step has a size of 8 × 40, and has an expression of H ═ B I₈]In which I₈Is an 8 th order identity matrix, expressed as:

in the formula, all diagonal elements are 1, and all the other elements except the diagonal elements are 0.

And 3, acquiring the original data D to obtain original verification data C.

(3a) The acquired original data D in the step is the space data which is sent to the FPGA by the space equipment and needs to be stored or the intermediate variable which needs to be stored in the running process of the program on the FPGA;

(3b) obtaining original check data according to the original data D and the generating matrix G: c ═ D × G.

An example is given below to further illustrate this step:

assuming that some intermediate variable X needs to be stored, the value of the intermediate variable, i.e. the original data D, is:

01100111101000110110011110100011；

if the example matrix B in the step 1 is adopted to construct the generator matrix G, the original check data C of the intermediate variable X can be calculated as follows: 0110011110100011011001111010001101011101.

and 4, judging the type of the original check data C.

Because the original check data C may be of two types, namely, intermediate variable and space data, different operations are required to be performed on different data, so that the data type needs to be firstly distinguished:

if C is an intermediate variable, step 5 is performed.

If C is space data to be written to the on-chip or off-chip memory, step 6 is performed.

For the original check data C of X in the above-mentioned example, since its type is an intermediate variable, step 5 should be performed.

And 5, storing the original check data C into a register L with the bit width of 40, and jumping to the step 8.

And 6, acquiring the address S of the storage space to which the original verification data C is to be written, and executing the step 7.

And 7, writing the original verification data C into a memory.

And outputting the address S to an address bus of the memory, outputting the original verification data C to a 40-bit data bus of the memory, raising the write enable of the memory by one clock, and executing the step 8 after the write is finished.

And 8, reading the final verification data C' from the register or the memory to obtain a syndrome J.

Since the original check data C is stored in the register or the memory for a period of time during which the stored value may be erroneous due to the SEU phenomenon, the final check data C' may be read differently from the original check data C.

Calculating a syndrome according to the final check data C' and the check matrix H: j ═ H × C'.

In the above example, the original check data C of X is stored in the register for a period of time and then read out, and it is assumed that the final check data C' read out at this time is: 0110011110101011011001111010001101011101, the syndrome J of the final check data C' can be calculated according to the check matrix H constructed by the example matrix B in step 1 as: 11111010.

and 9, correcting the final verification data C'.

(9a) Judging the value of syndrome J: if the value of J is 0, the final check data is correct, executing step 10, if the value of J is equal to the value of the ith column from the left in the matrix H, and i is more than or equal to 1 and less than or equal to 40, the final check data has a bit error, executing step 9b, and executing step 11 under other conditions;

(9b) judging whether i is less than 33, if so, indicating that the ith bit from the left of C' needs to be turned over to correct the error, and executing the step 9C, otherwise, executing the step 10;

(9c) and judging the ith bit value from the left of C', if the value is 1, updating the bit value to be 0, otherwise, updating the bit value to be 1, and executing the step 10.

In the above calculation example, the value of the syndrome J is equal to the 13 th column from the left of the matrix B, that is, equal to the 13 th column from the left of the matrix H, so that i is equal to 13 and is less than 33, which indicates that the 13 th bit from the left of the final check data C 'is erroneous, and the final check data C' is updated after the bit is inverted: 0110011110100011011001111010001101011101.

step 10, forming recovery data D'.

Intercepting the 1 st to 32 th bits from the left of the C 'to form a numerical value with the bit width of 32 bits as recovery data D', wherein the recovery data D 'is inevitably equal to the original data D, and the recovery data D' can be output to other space equipment or used for FPGA program operation.

The recovery data D 'obtained according to the final check data C' after error correction in the above arithmetic example is:

01100111101000110110011110100011。

the restored data D' and the original data D are compared to find that the values of the two are completely equal, which indicates that the error correction operation on the intermediate variable X is successful and the values are restored to be correct.

And step 11, generating an error detection flag, wherein the error detection flag indicates that the current space data or the intermediate variable has an uncorrectable multi-bit error and cannot be used continuously, and the current space data should be discarded or the current intermediate variable should be recalculated.

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (3)

1. A method for protecting high-reliability space data and intermediate variables is characterized by comprising the following steps:

(1) construction of a 32 × 40 generator matrix G ═ I₃₂ B^T]In which I₃₂Is a 32-degree identity matrix, B is a matrix of 8 rows and 32 columns, each column of which is an 8-bit binary code of an element in a set P, wherein P is a set of positive integers greater than or equal to 3, less than or equal to 255, and not equal to 4, 8, 16, 32, 64, 128, B^TIs the transpose of matrix B;

(2) construction of a check matrix H of size 8 × 40 ═ B I₈]In which I₈Is an 8 th order identity matrix;

(3) acquiring space data needing to be stored sent to an FPGA by space equipment or intermediate variables needing to be stored in the running process of a program on the FPGA as original data D;

(4) calculating original check data according to the original data D and the generating matrix G: c ═ D × G;

(5) judging the type of the original check data C: if C is an intermediate variable, executing (6), and if C is space data to be written into an on-chip or off-chip memory, executing (7);

(6) storing original check data C into a register L with the bit width of 40, and executing (9);

(7) acquiring a storage space address S to be written in by original check data C, and executing (8);

(8) outputting the address S to an address bus of the memory, simultaneously outputting the original check data C to a 40-bit data bus of the memory, and pulling up the write enable of the memory by one clock, and then executing (9);

(9) reading final check data C' in a register or a memory;

(10) calculating a syndrome according to the final check data C' and the check matrix H: j ═ H × C';

(11) judging the value of a syndrome J, if the value of the J is 0, then the final check data is correct, executing (13), if the value of the J is equal to the value of the ith column from the left in the matrix H, and i is more than or equal to 1 and less than or equal to 40, then a bit error exists in the final check data, executing (12), otherwise, executing (14);

(12) judging whether i is less than 33, if so, turning the ith bit value from the left of C' to correct errors, and executing (13), otherwise, directly executing (13); the bit value of the ith bit from the left of C 'is turned, the bit value of the ith bit from the left of C' is judged firstly, if the bit value is 1, the bit value is updated to 0, otherwise, the bit value is updated to 1;

(13) intercepting the 1 st to 32 th bits from the left of the C ', forming a numerical value with the bit width of 32 bits as recovery data D ', and outputting the recovery data D ' to other space equipment or for running an FPGA program;

(14) an error detection flag is generated indicating that uncorrectable multi-bit errors occur in the current space data or intermediate variables.

2. The method of claim 1, wherein: (1) in 32 th order identity matrix I₃₂Expressed as:

in the formula, all diagonal elements are 1, and all the other elements except the diagonal elements are 0.

3. The method of claim 1, wherein: (1) in 8 th order identity matrix I₈Expressed as:

in the formula, all diagonal elements are 1, and all the other elements except the diagonal elements are 0.

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