Detailed Description
For ease of understanding, a description of some of the concepts related to the embodiments of the application are given by way of example for reference.
In the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or" describes an association relationship of associated objects, meaning that there may be three relationships, e.g., A and/or B may mean that A alone exists, while A and B together exist, and B alone exists, where A, B may be singular or plural. The terms "first," "second," "third," "fourth" and the like in the description and in the claims and drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
External firmware is typically stored in an external memory, such as a memory (SPI flash) that communicates based on a serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI) communication protocol. When external firmware needs to be updated, a special SPI (serial peripheral interface) burner is generally adopted to burn new firmware into the SPI flash, but when the firmware is burnt each time, a user is often required to manually connect one SPI burner with one SPI flash, so that a large amount of labor cost and time cost are consumed. In addition, in the burning process, the upper computer is required to control the burning, so that the operation load of the upper computer is increased, and the upgrading efficiency of the external firmware is low.
In order to improve the upgrading efficiency of the external firmware, the embodiment of the application provides an upgrading method, a chip, a test device and a storage medium of the external firmware, and an application scenario of the upgrading method of the external firmware is described below.
Fig. 1 is an application scenario schematic diagram of an upgrade method of external firmware provided in an embodiment of the present application. The method for upgrading the external firmware provided in the embodiment of the application is applied to the controller 101, the controller 101 may be a main control chip in the test device 10 for controlling other chips in the test device 10, wherein the other chips may be a first memory 102 and a second memory 103, the controller 101 is respectively connected with the first memory 102 and the second memory 103, and after the controller 101 is powered on (power-on operation is executed), the controller 101 reads the firmware in the first memory 102 and the second memory 103.
The test device 10 is connected with the upper computer 20, and when the test device 10 finishes upgrading, an instruction message can be sent to the upper computer 20 to instruct the upper computer 20 to remove the second memory 103.
The test apparatus 10 may include a plurality of test boards, each of which includes a controller 101, a first memory 102, and a second memory 103. A test socket (e.g., a chip slot) is provided on each test base for mounting the second memory 103, and the second memory 103 is a detachable chip. The test equipment 10 may be a test rack for performing test upgrades to the first memory 102.
The upper computer 20 may be a party that can actively initiate a command, or may be a party that receives an instruction, for example, the upper computer 20 receives instruction information sent after the controller 101 of the test device 10 is upgraded, and the upper computer 20 sends instruction information for removing the second memory 103 to a device such as a manipulator after receiving the instruction information. The host computer 20 may include, but is not limited to, a personal computer (Personal Computer, PC), a central processing unit (Central Processing Unit, CPU), etc., which is not limited to the present application.
The controller 101 may be a micro controller unit (Microcontroller Unit, MCU) chip, which is also called a single chip Microcomputer (SINGLE CHIP microcomputers) or a single chip Microcomputer, and is configured to properly reduce the frequency and specification of the cpu, integrate peripheral interfaces such as a memory, a counter, a USB, etc. on a single chip, and form a chip-level computer for different applications. The controller 101 may also be a digital signal processing technology (Digital SignalProcessing) chip, i.e., a DSP chip that can implement digital signal processing technology. The controller 101 may also be a Field programmable gate array (Field-ProgrammableGate Array) chip, which may be implemented as a semi-custom circuit in the Application Specific Integrated Circuit (ASIC) Field, which overcomes the disadvantages of custom circuits and the limited number of gates in the original programmable device.
The first memory 102 may be a serial peripheral interface memory (SPI flash).
The second Memory 103 may be a Flash Memory (Flash Memory).
In order to solve the above-mentioned problems, referring to fig. 2, fig. 2 is a flowchart of an upgrade method of external firmware provided in an embodiment of the present application, which is applied to a controller (e.g. the controller 101 of fig. 1). The order of the steps in the flowchart may be changed and some steps may be omitted according to various needs.
In step S201, in response to the power-on operation, the first firmware is read from the first memory.
In some embodiments of the present application, a trigger program may be provided within the controller that is responsive to a power-up operation, such as when the controller is powered up (is performing a power-up operation), to trigger the controller to perform a read operation that reads the first firmware within the first memory. The controller is mounted on the same test backplane as the first memory, and when the controller is powered up, the controller reads Firmware (Firmware) from the first memory, for example, reads the first Firmware from the first memory. Firmware refers to a set of programs or software that are cured in a non-volatile memory.
In step S202, when it is detected that the second firmware is stored in the second memory, the second firmware is read.
In some embodiments of the application, the test apparatus includes a plurality of test boards, each of which is provided with a first memory to be tested or upgraded, a controller, and a chip slot in which a second memory may be placed. To upgrade the first firmware, a second memory may be installed on a chip slot of a test chassis on which the first firmware is installed.
Fig. 3 is an installation schematic diagram of a second memory according to an embodiment of the present application. As shown in fig. 3, an external firmware (such as a first firmware) is disposed in the first memory, and in order to upgrade the external firmware (such as the first firmware) of the first memory by using the firmware (such as the second firmware) of the second memory, the second memory may be installed on a chip slot of the test board, and as shown in fig. 3, the test board is further installed with a controller and the first memory.
In some embodiments of the present application, as shown in fig. 3, the upper computer writes the second firmware in batches into the plurality of second memories through the Nand controller before the second memories are mounted to the chip slots of the test backplane, wherein the Nand controller and the controller on the test backplane may be the same type of chip controller. In order to burn the second firmware into the second memories in batches, a plurality of second memories can be placed on a circuit board, and the circuit board can be a circuit board built in an upper computer or a circuit board externally connected with the upper computer, so that the application is not limited. After the upper computer burns the second firmware to the second memory, the upper computer can control the manipulator to install the second memory on the test bottom plate of the test equipment, or can install the second memory on the test bottom plate in a manual mode, and the application is not limited to the above.
In some embodiments of the present application, after the controller is powered on, on the one hand, the first firmware in the first memory is read, on the other hand, whether the second memory has the first firmware, for example, the second firmware is detected, and if the controller detects that the second memory has the second firmware, the second firmware is read out, so that the upgrade operation is performed later, for example, the step S203 is further performed.
In some embodiments of the present application, after the second firmware is read from the second memory, the controller may perform a cyclic redundancy check (Cyclic Redundancy Check, CRC) on the second firmware in order to verify the integrity and correctness of the read second firmware. CRC (cyclic redundancy check) is a data transmission error detection technology, and is implemented by calculating a check code according to a preset algorithm on data at a transmitting end, attaching the obtained check code to the back of a data frame and transmitting the data frame to a receiving end together. The receiving end verifies the received data and the check code according to the same algorithm so as to judge whether the received data is correct and complete. The preset algorithm can be a polynomial division algorithm, a binary division algorithm, a Hamming code algorithm and a hash algorithm.
In an example, taking a preset algorithm as a polynomial division algorithm as an example, the polynomial division algorithm is performed on the second firmware, and a remainder is obtained as the check code. After the check code is obtained, comparing the check code with a preset check code, and if the check code is the same as the preset check code, determining that the second firmware is successfully checked, wherein the second firmware read by the controller is complete and correct. The preset check code may be a check code stored in the second memory in advance, as shown in fig. 3, before the second firmware is burned into the second memory, the Nand controller calculates the preset check code of the second firmware, and the second firmware carrying the preset check code is burned into the Nand controller. The way the check code is calculated by the Nand controller is the same as the way the check code is calculated by the controller.
In another example, taking a preset algorithm as a hash algorithm as an example, hash operation is performed on the second firmware, and data in the second firmware is mapped to an output value with a fixed length to obtain a hash value of the second firmware. After the check code is obtained, comparing the check code with a preset check code, and if the check code is the same as the preset check code, determining that the second firmware is successfully checked, wherein the second firmware read by the controller is complete and correct.
In other embodiments of the present application, the second firmware may not be burned into the second memory before the second memory is mounted to the chip slot of the test floor. After the controller is powered on, if the controller does not detect that the second memory contains the second firmware, determining that the second memory does not execute firmware burning. When the controller cannot detect the second firmware from the second memory, the read first firmware can be utilized to execute a test procedure on the second memory.
In an example, after the controller is powered up and the second memory is mounted on the test backplane, when the controller cannot read the second firmware from the second memory, the test procedure may be performed on the second memory using the first firmware read from the first memory. The test flow may include, but is not limited to, testing a write operation to the second memory, testing a read operation to the second memory, and testing an erase operation to the second memory. The specific test flow can be set according to the model of the memory or the practical application, and the application is not limited.
In step S203, if the first firmware is different from the second firmware, the second firmware is written into the first memory to upgrade the first memory.
In some embodiments of the present application, after the controller reads the first firmware and the second firmware, the controller may compare whether the first firmware and the second firmware are identical, for example, whether the version number of the first firmware is identical to the version number of the second firmware, and if the version number of the first firmware is different from the version number of the second firmware, determine that the first firmware is different from the second firmware. If the first firmware is different from the second firmware, the first firmware is old firmware, and the upgrade operation needs to be performed. The upper computer is connected with the testing equipment, if the first firmware is the same as the second firmware, the upper computer can be instructed to execute the testing process on the second memory and remove the second memory after the testing process is finished, or the upper computer is instructed to directly remove the second memory, and the application is not limited to the above.
In some embodiments of the present application, after the controller determines that the first firmware is different from the second firmware, the second firmware is written into the first memory, so that the first memory is subjected to firmware upgrade. After the second firmware is written into the first memory, in order to verify whether the written second firmware is complete and correct, the written second firmware may be read from the first memory, a check code of the second firmware read from the first memory may be calculated, and a version number of the second firmware may be obtained, so as to perform verification. If the version number of the second firmware read from the first memory is the same as the version number of the second firmware read from the second memory, and the check code calculated when the second firmware is read from the first memory is the same as the check code calculated when the second firmware is read from the second memory, it is determined that the second firmware read from the first memory is the same as the second firmware read from the second memory.
In an example, for convenience of description, a version number carried when the controller reads the second firmware from the second memory is taken as the first version number, and a version number carried when the controller reads the second firmware from the first memory is taken as the second version number. The first version number is used to check the second version number. The check code of the second firmware read by the controller from the second memory is used as a first check code, and the first check code can be a preset check code carried when the second firmware is written into the second memory, or can be a check code calculated when the controller reads the second firmware from the second memory. And taking the check code calculated when the controller reads the second firmware from the first memory as a second check code. The first check code is used for checking the second check code.
If the first version number is different from the second version number, it means that the controller may write the wrong version into the first memory, or may be the case that the firmware writing abnormality causes the version number to be disordered, etc. If the first version number is different from the second version number, the controller can send prompt information to the upper computer to prompt the upper computer to issue an upgrade instruction again, or prompt the upper computer to remove the second memory and replace other memories storing the second firmware, for example, when the upper computer receives an instruction that the upgrade is unsuccessful, the current second memory is removed by using the manipulator, a new second memory is installed, and after the installation is completed, the upgrade instruction is issued again.
If the first version number is the same as the second version number, the first check code and the second check code can be compared to be the same, if the first check code and the second check code are different, the situation that the second firmware is lost in the writing process is indicated, a new second memory can be installed through the upper computer, and the power-on operation is executed on the controller again to execute the upgrading program. If the first check code is the same as the second check code, the first memory is triggered to be upgraded by the second firmware, and the controller sends prompt information of upgrading completion to the upper computer after the upgrading is finished. The above is merely an example, and the verification code may be verified a priori to verify the version number, or the verification code and the version number may be verified simultaneously, which is not limited by the comparison of the present application.
In an example, as shown in fig. 3, the test device may be a test cabinet, and includes a plurality of test boards, for example, there are 100 test boards, which means that there are 100 first storage devices to be upgraded, and assuming that there are 10 second memories in which the second firmware has been burned, the host computer may control the manipulator to install the 10 second memories on the chip slots of the 10 test boards, and when the host computer receives the prompt information of the upgrade completion, the host computer may control the manipulator to detach the 10 second memories and install the same on the chip slots of another 10 test boards, for example, the first time of installation on the test boards A1 to a10, the second time of installation on the test boards a11 to a20, which is just an example, and the practical application is not limited thereto.
In the embodiment of the application, the controller can respond to the power-on operation, directly execute the upgrade operation without the participation of the upper computer in the upgrade process, and the upper computer can remove the second memory when receiving the indication information of the controller, so that the operation pressure of the upper computer can be reduced to a certain extent. In the embodiment, the verification work is executed in the controller, so that the calculated amount of the upper computer can be reduced. For example, in the related art, the upper computer needs to control the SPI burner one by one to upgrade the firmware of each first memory to be upgraded, so that not only is more control programs needed to be executed, but also verification calculation is needed to be considered. Assuming that 100 first storage devices need to be upgraded, such methods require the host computer to control and execute 100 times, and each time a check calculation needs to be performed. In the present embodiment, assuming that 100 first storage devices need to be upgraded, after 10 second memories are configured, the controller controls to execute 10 times, and the upper computer controls the installation/removal of the second memories 10 times. In addition, when the second firmware in the second memory is not detected, the embodiment of the application can start the test flow of the second memory, and can reduce the test cost and the test time to a certain extent.
In the embodiment of the application, the controller responds to the power-on operation of the controller, the second firmware in the second memory is utilized to upgrade the first firmware of the first memory, and an external device (such as an SPI (serial peripheral interface) burner) is not required to be controlled by an upper computer to carry out a test, so that the operation pressure of the upper computer is reduced to a certain extent, and the upgrade efficiency of the external firmware is improved.
Fig. 4 is a flowchart of an upgrade method of external firmware provided in an embodiment of the present application, as shown in fig. 4, including the following steps:
in step S401, the controller reads the first firmware from the first memory in response to the power-on operation.
In step S402, the controller detects whether there is a second firmware in the second memory.
In some embodiments of the present application, if the second firmware in the second memory cannot be detected, step S403 is performed, and if the second firmware in the second memory is detected, step S404 is performed continuously.
In step S403, the controller executes the test procedure on the second memory by using the first firmware until the test procedure is finished, and sends a prompt message of finishing the test to the upper computer.
In step S404, the controller determines whether the first firmware and the second firmware are the same.
In some embodiments of the present application, if the first firmware is the same as the second firmware, the step S403 is executed, and if the first firmware is different from the second firmware, the step S405 is executed continuously.
In step S405, the controller writes the second firmware into the first memory, and upgrades the firmware of the first memory.
In step S406, the controller determines whether the upgrade is completed.
In some embodiments of the present application, if the upgrade is not completed, step S406 may be performed continuously, and if the upgrade is completed, step S407 may be performed continuously.
In step S407, the controller sends prompt information of the upgrade completion to the upper computer.
In step S408, the upper computer controls the manipulator to remove and install the second firmware on the other test base plate until all the first memories in the test equipment are upgraded.
In some embodiments of the present application, the specific descriptions of step S401 to step S408 may refer to the embodiment shown in fig. 2, and the descriptions are not repeated here.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a controller according to an embodiment of the application. The controller 101 includes, but is not limited to, a memory 11 and a processor 12. In this embodiment, the memory 11 may be an internal memory of the controller 101, that is, a memory built in the controller 101. In other embodiments, the memory 11 may also be an external memory of the host computer 20, i.e. a memory external to the controller 101.
In some embodiments, the memory 11 is used to store program codes and various data, and to implement high-speed, automatic access to programs or data during operation of the controller 101.
The memory 11 may include random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart memory card (SMART MEDIA CARD, SMC), secure Digital (SD) card, flash memory card (FLASH CARD), at least one disk storage device, flash memory device, or other volatile solid-state storage device.
In one embodiment, the Processor 12 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL processors, DSPs), application SPECIFIC INTEGRATED Circuits (ASICs), field-Programmable gate arrays (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any other conventional processor or the like.
The program code and various data in said memory 11 may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as a separate product. Based on such understanding, the present application may implement all or part of the procedures in the methods of the embodiments, for example, the upgrading method of the external firmware, or may be implemented by instructing related hardware through a computer program, where the computer program may be stored in a computer readable storage medium, and the computer program may implement the steps of the embodiments of the methods when executed by a processor. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), or the like.
It will be appreciated that the above-described division of modules into a logical function division may be implemented in other ways. In addition, each functional module in the embodiments of the present application may be integrated in the same processing unit, or each module may exist alone physically, or two or more modules may be integrated in the same unit. The integrated modules may be implemented in hardware or in hardware plus software functional modules.
Finally, it should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present application without departing from the spirit and scope of the technical solution of the present application.