CN118983269A

CN118983269A - Stacked chip packaging method

Info

Publication number: CN118983269A
Application number: CN202411047167.3A
Authority: CN
Inventors: 陶玉娟; 朱秋昀; 杨灵
Original assignee: Tongfu Microelectronics Co Ltd
Current assignee: Tongfu Microelectronics Co Ltd
Filing date: 2024-07-31
Publication date: 2024-11-19

Abstract

The embodiment of the disclosure provides a stacked chip packaging method, which comprises the following steps: forming a plurality of chips, each chip being formed with a bump electrically connected to a pad thereof; forming a first plastic sealing layer for wrapping the chip, and forming a first interconnection circuit layer on the bump exposed by the first plastic sealing layer to form a first chip module; forming a second plastic sealing layer for wrapping the chip and forming a plurality of plastic sealing through holes on the second plastic sealing layer; forming a rewiring layer electrically connected with the plastic packaging through hole on the first surface of the second plastic packaging layer; forming a second interconnection circuit layer electrically connected with the plastic package through hole on the second surface of the second plastic package layer to form a second chip module; and stacking a plurality of second chip modules on the substrate in sequence through the second interconnection circuit layer, stacking the first chip modules to the uppermost second chip module through the first interconnection circuit layer, and realizing vertical interconnection among the chip modules through the plastic package through holes. The method can improve the storage capacity of the chip packaging structure, reduce the requirement on alignment precision, reduce the number of stacked layers and improve the structural stability.

Description

Stacked chip packaging method

Technical Field

The embodiment of the disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a stacked chip packaging method.

Background

As shown in fig. 1, a plurality of memory chips 30 are stacked on a substrate 22 through a silicon interposer 24 in a stacking manner, and vertical interconnection is realized by using through silicon vias 32, wherein a top memory chip 36 has no through silicon vias 32 structure; the greater the number of chips stacked, the greater the memory capacity. Along with the increase of the number of stacked chips, the alignment difficulty between each layer and the previous layer is obviously improved, and a severe challenge is brought to the manufacturing process, so that the increase of the number of stacked chips is limited, and the improvement of the storage capacity is influenced.

In view of the above, there is a need for a method of packaging stacked chips that is reasonably designed and efficiently solves the above problems.

Disclosure of Invention

The embodiment of the disclosure aims to at least solve one of the technical problems in the prior art and provides a stacked chip packaging method.

The embodiment of the disclosure provides a stacked chip packaging method, which comprises the following steps:

forming a plurality of chips, wherein each chip is formed with a bump electrically connected with a bonding pad thereof;

Forming a first plastic sealing layer which wraps a plurality of chips, and forming a first interconnection circuit layer on the bumps exposed by the first plastic sealing layer to form a first chip module;

forming a second plastic sealing layer for wrapping a plurality of chips, and forming a plurality of plastic sealing through holes on the second plastic sealing layer;

Forming a rewiring layer electrically connected with the plastic packaging through hole on the first surface of the second plastic packaging layer;

forming a second interconnection circuit layer electrically connected with the plastic package through hole on the second surface of the second plastic package layer so as to form a second chip module;

And stacking a plurality of second chip modules on a substrate in sequence through the second interconnection line layer, stacking the first chip modules to the uppermost layer through the first interconnection line layer, and realizing vertical interconnection among the chip modules through the plastic package through holes.

Optionally, the forming a second plastic layer that wraps the plurality of chips includes:

Fixing the front faces of a plurality of chips on a temporary carrier plate;

forming the second plastic sealing layer wrapping a plurality of chips on the temporary carrier plate;

And removing the temporary carrier plate.

Optionally, the forming a rewiring layer on the first surface of the second plastic sealing layer, where the rewiring layer is electrically connected with the plastic sealing through hole includes:

forming the rewiring layer electrically connected with the plastic packaging through hole on the first surface of the second plastic packaging layer and the back surface of the chip; or alternatively

And forming the rewiring layer electrically connected with the plastic packaging through hole on the first surface of the second plastic packaging layer.

Optionally, the forming a second interconnection circuit layer on the second surface of the second plastic sealing layer and the second surface of the chip, where the second interconnection circuit layer is electrically connected to the plastic sealing through hole includes:

and forming second welding spots on the second surface of the second plastic sealing layer and the front surface of the chip respectively, wherein the second welding spots are electrically connected with the corresponding bumps and the plastic sealing through holes respectively.

Optionally, the forming a second plastic layer that wraps a plurality of the chips further includes:

fixing the back surfaces of a plurality of chips on a temporary carrier plate;

Thinning the second plastic sealing layer to expose the bumps on the front surface of the chip;

And removing the temporary carrier plate.

Optionally, the forming a rewiring layer on the first surface of the second plastic sealing layer, where the rewiring layer is electrically connected with the plastic sealing through hole, further includes:

and forming a rewiring layer on the first surface of the second plastic sealing layer and the front surface of the chip, wherein the rewiring layer is electrically connected with the plastic sealing through hole and the bump respectively.

Optionally, a second interconnection circuit layer electrically connected to the plastic package through hole is formed on the second surface of the second plastic package layer and the second surface of the chip, and the method further includes:

forming a wiring layer on the second surface of the second plastic sealing layer and the back surface of the chip, wherein the wiring layer is electrically connected with the plastic sealing through hole;

And forming a plurality of solder balls electrically connected with the wiring layer on the wiring layer.

Optionally, the stacking the plurality of second chip modules on the substrate sequentially through the second interconnection line layer, stacking the first chip module on the uppermost layer through the first interconnection line layer, and includes:

The second interconnection line layer of the second chip module at the upper layer is electrically connected with the rewiring layer of the second chip module at the lower layer;

the first interconnection line layer of the first chip module is electrically connected with the rewiring layer of the second chip module at the uppermost layer.

Optionally, the forming a plurality of chips includes:

Providing a wafer, wherein a passivation layer and the bonding pad are sequentially arranged on the front surface of the wafer;

Forming the bump corresponding to the bonding pad and electrically connected with the bonding pad;

And cutting the wafer to form a plurality of chips, wherein the front surface of each chip is provided with the bump electrically connected with the bonding pad.

Optionally, the forming a plurality of plastic package through holes on the second plastic package layer includes:

forming a plurality of through holes which penetrate through the thickness of the second plastic sealing layer at intervals;

And filling conductive materials in the through holes to form the plastic package through holes.

According to the stacked chip packaging method, the first chip module and the second chip module which comprise the plurality of chips are transversely arranged are respectively formed, the plurality of second chip modules are sequentially stacked on the substrate through the second interconnection circuit layer, the first chip module is stacked to the second chip module at the uppermost layer through the first interconnection circuit layer, and vertical interconnection among the chip modules is achieved through the plastic package through holes. A plurality of chips are arranged in each first chip module and each second chip module, so that the storage capacity of the chip packaging structure is remarkably improved, the number of stacking layers can be reduced, and the stability of the whole chip packaging structure is improved; the vertical interconnection is realized among the chip modules by using plastic package through holes with larger diameters, the plastic package through holes can be better aligned with the rewiring layer and the bonding pads of the substrate, the alignment precision requirement is obviously reduced, and the stability of the chip packaging structure is improved.

Drawings

FIG. 1 is a schematic diagram of a multi-layer stacked chip package structure in the prior art;

FIG. 2 is a flow chart of a method for packaging stacked chips according to an embodiment of the disclosure;

FIG. 3 is a top view of a wafer according to one embodiment of the present disclosure;

FIG. 4 is a schematic view of a process for forming a plurality of chips in a first embodiment and a second embodiment of the present disclosure;

Fig. 5 is a schematic view of a process for forming a first molding layer in a first embodiment and a second embodiment in an embodiment of the disclosure;

Fig. 6 is a schematic process diagram of thinning a first plastic sealing layer in a first embodiment and a second embodiment in an embodiment of the disclosure;

fig. 7 is a schematic process diagram of forming a first interconnect line layer to form a first chip module in a first embodiment and a second embodiment of the present disclosure;

fig. 8 is a schematic view of a process for forming a second plastic layer according to the first embodiment of the present disclosure;

fig. 9 is a schematic process diagram of forming a plastic package through hole according to a first embodiment of the disclosure;

Fig. 10 is a schematic process diagram of forming a redistribution layer on a first surface of a second plastic sealing layer according to a first embodiment of the present disclosure;

Fig. 11 is a schematic process diagram of forming a second interconnection line layer on a second surface of a second plastic sealing layer to form a second chip module according to the first embodiment of the disclosure;

fig. 12 is a schematic process diagram of stacking a first chip module and a plurality of second chip modules on a substrate in sequence and forming a chip package structure according to a first embodiment of the disclosure;

Fig. 13 is a schematic diagram of a second chip module formed when the chip of the first embodiment does not expose the second plastic layer and a chip package structure formed by stacking the second chip module in the embodiment of the disclosure;

fig. 14 is a schematic view of a process for forming a second plastic layer according to a second embodiment of the present disclosure;

fig. 15 is a schematic process diagram of forming a plastic package through hole according to a second embodiment of the disclosure;

Fig. 16 is a schematic process diagram of forming a redistribution layer on a first surface of a second plastic sealing layer according to a first embodiment of the present disclosure;

Fig. 17 is a schematic process diagram of forming a second interconnection line layer on a second surface of a second plastic sealing layer to form a second chip module according to a second embodiment of the disclosure;

Fig. 18 is a schematic process diagram of stacking a first chip module and a plurality of second chip modules sequentially on a substrate to form a chip package structure according to a second embodiment of the disclosure.

Detailed Description

In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and detailed description.

As shown in fig. 2, an embodiment of the present disclosure provides a stacked chip packaging method S100, where the chip packaging method S100 includes:

S110, forming a plurality of chips, wherein each chip is formed with a bump electrically connected with a bonding pad thereof.

As shown in fig. 3 and 4, first, as shown in fig. 4a, a wafer 42 is provided, wherein a passivation layer 46 and a pad 44 are sequentially disposed on a first surface of the wafer 42. Wherein the first surface of the wafer 42 is the front surface of the wafer 42. That is, the front surface of the wafer 42 is provided with a passivation layer 46 and a pad 44 in this order.

Next, bumps 50 corresponding thereto and electrically connected thereto are formed on the pads 44.

Specifically, as shown in fig. 4b, photoresist is spin-coated on the front surface of the wafer 42 to form a first photoresist layer 48, and the first photoresist layer 48 is exposed and developed, so that the first photoresist layer 48 forms a first opening at a position corresponding to the pad 44. As shown in fig. 4c, the bump 50 is formed at the opening by an electroplating process, wherein in this embodiment, the bump 50 is a copper bump and is electrically connected to the pad 44. As shown in fig. 4d, the remaining first photoresist layer 48 is removed using an etching process or the like.

The wafer 42 is then diced to form a plurality of chips 52, wherein a first surface of each chip 52 is formed with bumps 50 electrically connected to its bond pads 44.

Specifically, as shown in fig. 4e, the wafer 42 is diced according to the packaging requirements to form a plurality of chips 52, and the pads 44 on the front surface of each chip 52 are formed with bumps 50 corresponding thereto.

In the present embodiment, the type of the chip 52 is not particularly limited, but in the present embodiment, the first surface of the chip 52 is taken as the front surface of the chip 52, the second surface of the chip 52 is taken as the back surface of the chip 52, and the type of the chip 52 is taken as the memory chip.

S120, forming a first plastic sealing layer for wrapping a plurality of chips, and forming a first interconnection circuit layer on the bumps exposed by the first plastic sealing layer to form a first chip module.

Specifically, as shown in fig. 5, the specific process of forming the first plastic layer 62 in step S120 is as follows:

As shown in fig. 5a, a temporary carrier plate 56 is provided, and a temporary bonding adhesive layer 54 is provided on the temporary carrier plate 56. The front sides of the plurality of chips 52 are secured to a temporary bond paste layer 54. As shown in fig. 5b, a first plastic layer 62 is formed over the temporary bonding glue layer 54 to encapsulate the plurality of chips 52. As shown in fig. 5c, the side of the first plastic layer 62 facing away from the temporary carrier plate 56 is thinned by grinding to expose the back surfaces of the plurality of chips 52.

It should be noted that, the plurality of chips 52 are horizontally tiled in the first plastic layer 62, and the number of chips 52 is not particularly limited in this embodiment, and may be selected according to actual needs.

As shown in fig. 6, a specific process of forming the first interconnect line layer in step S120 is as follows:

As shown in fig. 6a, a first temporary bonding layer 54 'and a first temporary carrier plate 56' are sequentially disposed on the surface of the first plastic layer 62 facing away from the temporary carrier plate 56 and the back surface of the chip 52. As shown in fig. 6b, the first plastic layer 62 is flipped over to allow the first temporary carrier plate 56' to serve as a supporting carrier plate and to remove the temporary carrier plate 56 and temporary bond ply 54.

Referring to fig. 7a, photoresist is spin coated on the surface of the first molding layer 62 facing away from the first temporary carrier plate 56' to form a second photoresist layer 68, and the second photoresist layer 68 is exposed and developed to form a second opening at a position corresponding to the bump 50 to expose the bump 50. As shown in fig. 7b, solder 70 is electroplated at the second opening. As shown in fig. 7c, the remaining second photoresist layer 68 is removed by an etching process or the like. As shown in fig. 7d, the solder 70 is reflowed to form first solder joint 72 on the bump 50, and the first solder joint 72 is electrically connected to the bump 50. That is, the first interconnect line layer is a plurality of first pads 72 electrically connected to the bumps 50. In this embodiment, the first solder joint 72 may be a solder ball.

After forming the plurality of first solder joints 72, the first temporary bonding adhesive layer 54' is separated from the first plastic layer 6 to form a first chip module a, as shown in fig. 7 e. That is, the first chip module a includes a first molding layer 62, a plurality of chips 52 enclosed in the first molding layer 62, and a first interconnect wiring layer disposed on the bumps 50 of the chips 52. Wherein, bump 50 electrically connected with pad 44 is disposed on pad 44 on the front surface of chip 52, and the surface of bump 50 is flush with the surface of first molding layer 62. The first chip module A realizes vertical interconnection with other chip modules through the first interconnection line layer.

In this embodiment, a plurality of chips are tiled in the first chip module, so that the storage capacity of the chip packaging structure is significantly improved, the number of stacked layers can be reduced, and the stability of the whole chip packaging structure is improved.

S130, forming a second plastic sealing layer for wrapping a plurality of chips, and forming a plurality of plastic sealing through holes on the second plastic sealing layer.

As shown in fig. 8, in the first embodiment, the specific process of forming the second molding layer 62' wrapping the plurality of chips 52 in step S130 is as follows:

First, as shown in fig. 8a, a temporary carrier plate 56 is provided, and a temporary bonding adhesive layer 54 is disposed on the temporary carrier plate 56. The front sides of the plurality of chips 52 are secured to a temporary bond paste layer 54 on a temporary carrier plate 56.

Next, as shown in fig. 8b, a second plastic layer 62' is formed on the temporary bonding adhesive layer 54 of the temporary carrier plate 56 by film vacuum lamination or a conventional plastic sealing process to encapsulate the plurality of chips 52.

Then, as shown in fig. 8c, after the second plastic layer 62 'is formed, the second plastic layer 62' may be thinned by grinding or the like to expose the back surface of the chip 52.

Finally, the temporary bonding adhesive layer 54 is peeled off from the second plastic layer 62' to remove the temporary carrier plate 56.

After the second plastic layer 62 'is formed, the second plastic layer 62' may not be thinned, that is, the plurality of chips 52 are completely encapsulated in the second plastic layer 62', and the surfaces of the chips 52 are not exposed on the surface of the second plastic layer 62'. Whether the surface of the chip 52 is exposed to the surface of the second molding layer 62' may be selected according to actual needs, and the present embodiment is not particularly limited.

As shown in fig. 9, in the first embodiment, the specific process of forming the plurality of molding holes 66 on the second molding layer 62' in step S130 is as follows:

As shown in fig. 9a, a plurality of through holes 64 are formed in the second molding layer 62' at intervals through the thickness thereof by drilling or the like. The plurality of through holes 64 may be equally spaced or non-equally spaced, and may be selected according to actual needs.

As shown in fig. 9b, the through-hole 64 is filled with a conductive material by an electroplating process or the like to form a plastic-sealed through-hole 66. In this embodiment, the conductive material may be metallic copper, that is, the plastic package via 66 is a copper pillar.

In this embodiment, through the plastic packaging through hole that the size is great, the vertical interconnection between each chip module that can be better realizes, the plastic packaging through hole can be better with the pad of rewiring layer and base plate counterpoint, show reduction counterpoint precision requirement, make chip packaging structure's stability high.

As shown in fig. 14, in the second embodiment, the specific process of forming the second molding layer 62' for wrapping the plurality of chips 52 in step S130 may further be as follows: .

First, as shown in fig. 14a, a temporary carrier plate 56 is provided, and a temporary bonding adhesive layer 54 is disposed on the temporary carrier plate 56. The back sides of the plurality of chips 52 are secured to the temporary bonding glue layer 54 on the temporary carrier plate 56 by means of the adhesive layer 60.

Next, a second plastic layer 62' is formed over the temporary bonding glue layer 54 of the temporary carrier plate 56 by a film vacuum lamination or a conventional plastic encapsulation process as shown in fig. 14b, which encapsulates the plurality of chips 52.

Then, the second plastic layer 62' is thinned by grinding or the like to expose the bumps 50 on the front surface of the chip 52 as shown in fig. 14 c.

As shown in fig. 15, in the first embodiment, the specific process of forming the plurality of molding holes 66 on the second molding layer 62' in step S130 is as follows:

As shown in fig. 15a, a plurality of through holes 64 are formed in the second molding layer 62' at intervals through the thickness thereof by drilling or the like. The plurality of through holes 64 may be equally spaced or non-equally spaced, and may be selected according to actual needs.

As shown in fig. 15b, the through-hole 64 is filled with a conductive material by an electroplating process or the like to form a plastic-sealed through-hole 66. In this embodiment, the conductive material may be metallic copper, that is, the plastic package via 66 is a copper pillar.

And S140, forming a rewiring layer electrically connected with the plastic packaging through hole on the first surface of the second plastic packaging layer.

As shown in fig. 10, in the first embodiment, the specific process of forming the rewiring layer 58 in step S140 may be as follows:

As shown in fig. 10a, after the second plastic layer 62 'is formed in step S130, the second plastic layer 62' is thinned by grinding or the like to expose the back surface of the chip 52. A re-routing layer 58 electrically connected to the molding vias 66 is formed on the first surface of the second molding layer 62' and the back surface of the exposed chip 52. In this embodiment, the first surface of the second plastic layer 62 'is the surface of the second plastic layer 62' facing away from the temporary carrier 56.

Specifically, a dielectric layer is formed on the first surface of the second molding layer 62' and the back surface of the exposed chip 52, the dielectric layer is patterned by a photolithography process, and an interconnection metal layer is formed on the patterned dielectric layer by a process such as electroplating or sputtering, thereby forming the re-wiring layer 58. The number of layers of the redistribution layer 58 is not particularly limited in this embodiment, and may be selected according to actual needs.

In this embodiment, signals of the chip are led to the back surface of the chip through the electrically connected rewiring layer and the plastic package via.

As shown in fig. 13a, if the second plastic layer 62' is not thinned after the second plastic layer 62' is formed in step S130, the rewiring layer 58 electrically connected to the plastic vias 55 may be directly formed on the first surface of the second plastic layer 62 '. That is, the redistribution layer 58 is not in contact with the back side of the chip 52.

As shown in fig. 16, in the second embodiment, the specific process of forming the rewiring layer 58 may also be as follows:

As shown in fig. 16a, a redistribution layer 58 is formed on the first surface of the second molding layer 62' and the front surface of the chip 52, and the redistribution layer 58 is electrically connected to the molding via 66 and the bump 50, respectively. That is, the redistribution layer 58 is electrically connected to the plastic encapsulated via 66 and the die 52, respectively. In this embodiment, the first surface of the second plastic layer 62 'is the surface of the second plastic layer 62' facing away from the temporary carrier 56.

S150, forming a second interconnection circuit layer on the second surface of the second plastic sealing layer and electrically connecting the second interconnection circuit layer with the plastic sealing through hole so as to form a second chip module.

As shown in fig. 11, in the first embodiment, a specific process of forming the second interconnect line layer may be:

Before forming the second interconnect line layer, as shown in fig. 10b, a first temporary bonding adhesive layer 54 'and a first temporary carrier plate 56' are sequentially disposed on the re-wiring layer 58. As shown in fig. 10c, the second plastic layer 62 'is turned over to make the first temporary carrier 56' as a supporting carrier, and the temporary carrier 56 and the temporary bonding adhesive layer 54 are removed, so as to expose the bumps 50 and the plastic package through holes 66 on the front surface of the chip 52.

As shown in fig. 11a, photoresist is spin coated on the second surface of the second molding layer 62' to form a second photoresist layer 68, and the second photoresist layer 68 is exposed and developed to form a second opening at a position corresponding to the bump 50 and the molding via 66 to expose the bump 50 and the molding via 66. As shown in fig. 11b, solder 70' is electroplated at the second opening. As shown in fig. 11c, the remaining second photoresist layer 68 is removed by an etching process or the like. As shown in fig. 11d, the solder 70' is reflowed to form second solder joints 72' on the bumps 50, and the second solder joints 72' are electrically connected to the bumps 50 and the plastic package vias 66, respectively. That is, in the first embodiment, the second interconnect wiring layer is a plurality of second pads 72' electrically connected with the bumps 50 and the plastic-molded via 66. In this embodiment, the second solder joint 72' may be a solder ball.

As shown in fig. 11e, the first temporary carrier plate 56 'and the first temporary bonding adhesive layer 54' are removed and inverted to form the second chip module B. That is, the second chip module B includes a second molding layer 62', a plurality of chips 52 encapsulated in the second molding layer 62', a plurality of molding vias 66 extending through the thickness of the second molding layer 62', a rewiring layer 58 disposed on a first surface of the second molding layer 62', and a plurality of second solder joints 72 'disposed on the bumps 50 and the molding vias 66 on a second surface of the second molding layer 62'. The second die set B is vertically interconnected with other die sets by a plurality of second bond pads 72'.

As shown in fig. 17, in the second embodiment, the specific process of forming the second interconnect line layer may further be:

Before forming the second interconnect line layer, as shown in fig. 16b, a first temporary bond paste layer 54 'and a first temporary carrier plate 56' are sequentially disposed on the redistribution layer 58. As shown in fig. 16c, the second plastic layer 62 'is flipped over to allow the first temporary carrier plate 56' to serve as a supporting carrier plate and to remove the temporary carrier plate 56 and temporary bond ply 54. The second surface of the second plastic layer 62' is exposed with the plastic vias 66 and the adhesive layer 60 on the die 52.

As shown in fig. 17, a wiring layer 71 is formed on the second surface of the second molding layer 62' and the back surface of the chip 52, and the wiring layer 71 is electrically connected to the molding through hole 66. In this embodiment, the second surface of the second molding layer 62 'is the surface of the second molding layer 62' facing away from the rewiring layer 58.

Specifically, as shown in fig. 17a, a dielectric layer and an interconnection metal layer are sequentially formed on the second surface of the second molding layer 62' and the adhesive layer 60 on the back surface of the chip 52, wiring is completed to form a wiring layer 71, and the wiring layer 71 is electrically connected with the molding through hole 66.

Next, a plurality of solder balls 73 electrically connected to the wiring layer 71 are formed on the wiring layer 71. Wherein the wiring layer 71 and the solder balls 73 together constitute a second interconnect wiring layer.

Specifically, as shown in fig. 17b, bump plating is performed on the wiring layer 71 to form a plurality of solder balls 73, and the plurality of solder balls 73 are provided on the interconnect metal layer of the wiring layer 71 and electrically connected to the wiring layer 71.

As shown in fig. 17c, after the wiring layer 71 and the solder balls are sequentially formed on the second surface of the second plastic layer 62 'and the back surface of the chip 52, the second plastic layer 62' is turned over, and the first temporary carrier 56 'and the first temporary bonding adhesive layer 54' are removed, so as to form the second chip module B. That is, the second chip module B includes a second molding layer 62', a plurality of chips 52 encapsulated in the second molding layer 62', a plurality of molding through holes 66 penetrating through the thickness of the second molding layer 62', a re-routing layer 58 disposed on the first surface of the second molding layer 62', a routing layer 71 disposed on the second surface of the second molding layer 62', and solder balls 73 disposed on the routing layer 71. The second chip module B realizes vertical interconnection with other chip modules through the wiring layer 71 and the solder balls 73.

In this embodiment, the second interconnection circuit layer is a wiring layer and a plurality of solder balls formed on the wiring layer, so that the front and back surfaces of each chip in each second chip module are circuit layers, and abundant solder joint outputs are provided for each chip, so as to realize efficient electrical connection.

S160, stacking a plurality of second chip modules on a substrate in sequence through the second interconnection line layer, stacking the first chip modules to the uppermost layer through the first interconnection line layer, and realizing vertical interconnection among the chip modules through the plastic package through holes.

Specifically, as shown in fig. 12 and 18, the second interconnect wiring layer of the upper second chip module B is electrically connected to the rewiring layer 58 of the lower second chip module B. The first interconnect wiring layer of the first chip module a is electrically connected to the rewiring layer 58 of the uppermost second chip module B. Vertical interconnection between the chip modules is achieved through the plastic package vias 66.

In the first embodiment, as shown in fig. 12a, a plurality of second chip modules B are stacked in sequence on a substrate 74 through second pads 72'. That is, one second chip module B is stacked on the substrate 74, and then the other second chip modules B are stacked on the lowest second chip module B in sequence. Wherein the lowermost second die set B is electrically connected to the substrate 74 via the second pads 72'. The second solder joints 72' of the upper second chip module B in the other second chip modules B are electrically connected with the rewiring layer 58 of the lower second chip module B, and the vertical interconnection between the second chip modules B is realized through the plastic package through holes 66, so that the vertical interconnection between the chips 52 in the second chip modules B is realized.

As shown in fig. 12B, in the first embodiment, after a plurality of second chip modules B are stacked on the substrate 74 in sequence, the first chip module a is stacked on the rewiring layer 58 of the uppermost second chip module B through the first solder joint 72, so as to implement interconnection between each chip 52 in the first chip module a and each chip 52 in the uppermost second chip module B.

As shown in fig. 12c, in the first embodiment, after the first chip module a and the plurality of second chip modules B are stacked in sequence on the substrate 74, an underfill layer 76 is formed between the first chip module a and the uppermost second chip module B, between two adjacent second core modules B, and between the lowermost second chip module B and the substrate 74, and the underfill layer 76 wraps the first solder joint 72 and the second solder joint 72', respectively, so as to further fix the chip modules.

In the first embodiment, after the underfilling between the chip modules and between the second chip module B and the substrate 74 is completed, a plurality of interconnect solder balls 78 are formed on the side of the substrate 74 facing away from the chip modules to form a chip package. And cutting the chip packaging body according to the packaging requirement to obtain the chip packaging structure shown in fig. 12 d. Wherein the package structure is electrically connected to the outside world through interconnect balls 78.

As shown in fig. 13, when the second chip module B shown in fig. 13a is formed when the second plastic layer 62' is not exposed from the chip 52, a plurality of second chip modules B are stacked in sequence on the substrate 74, and then the first chip module a is stacked on the uppermost second chip module B, so as to form the chip package structure shown in fig. 13B. That is, the redistribution layer 58 is not in contact with the back side of the die 52, but is in direct contact with the first surface of the second molding layer 62'. The signals of the chips 52 in the lower-layer second chip module B are led out to the rewiring layer 58 through the second welding spots 72 'and the plastic package through holes, and the rewiring layer 58 is electrically connected with the plastic package through holes 66 and the second welding spots 72' in the upper-layer second chip module B, so that vertical interconnection between the chips 52 in the upper-layer second chip module B and the lower-layer second chip module B is realized.

Referring to fig. 18a, in the second embodiment, a second chip module B is first soldered to a substrate 74 through a plurality of solder balls 73. Then, as shown in fig. 18B, the other plurality of second chip modules B are stacked in sequence on the substrate 74 through the plurality of solder balls 73. Among the second chip modules B, the second chip module B at the lowest layer is electrically connected to the substrate 74 through a plurality of solder balls 73, and among the other second chip modules B, the plurality of solder balls 73 of the second chip module B at the upper layer are electrically connected to the rewiring layer 58 of the second chip module B at the lower layer, and meanwhile, the second chip modules B are vertically interconnected through the plastic package through holes 66, so that the vertical interconnection between the chips 52 in the second chip modules B is realized.

As shown in fig. 18B, in the second embodiment, after a plurality of second chip modules B are stacked on the substrate 74 in sequence, the first chip module a is stacked on the rewiring layer 58 of the uppermost second chip module B through the first solder joint 72, so as to implement interconnection between each chip 52 in the first chip module a and each chip 52 in the uppermost second chip module B.

As shown in fig. 18c, in the second embodiment, after the first chip module a and the plurality of second chip modules B are stacked in sequence on the substrate 74, an underfill layer 76 is formed between the first chip module a and the uppermost second chip module B, between two adjacent second core modules B, and between the lowermost second chip module B and the substrate 74, and the underfill layer 76 wraps the solder balls 73 and the first solder joints 72, respectively, so as to further fix the chip modules.

In a second embodiment, after the underfilling between the chip modules and between the second chip module B and the substrate 74 is completed, a plurality of interconnect solder balls 78 are formed on the side of the substrate 74 facing away from the chip modules to form a chip package. And cutting the chip packaging body according to the packaging requirement to obtain the chip packaging structure shown in fig. 18 d. Wherein the package structure is electrically connected to the outside world through interconnect balls 78.

According to the stacked chip packaging method, the first chip module and the second chip module which comprise a plurality of chips are transversely arranged are respectively formed, the plurality of second chip modules are sequentially stacked on the substrate through the second interconnection circuit layer, the first chip module is stacked to the uppermost layer of the second chip module through the first interconnection circuit layer, and vertical interconnection among the sequentially stacked first chip module and the second chip module, among the plurality of second chip modules and among the second chip module and the substrate is realized through the plastic package through holes. A plurality of chips can be arranged in each first chip module and each second chip module, so that the storage capacity of the chip packaging structure is remarkably improved, the number of stacking layers can be reduced, and the stability of the whole chip packaging structure is improved; the vertical interconnection is realized among the chip modules by using plastic package through holes with larger diameters, the plastic package through holes can be better aligned with the rewiring layer and the bonding pads of the substrate, the alignment precision requirement is obviously reduced, and the stability of the chip packaging structure is improved.

It is to be understood that the above implementations are merely exemplary implementations employed to illustrate the principles of the disclosed embodiments, which are not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the embodiments of the disclosure, and these modifications and improvements are also considered to be within the scope of the embodiments of the disclosure.

Claims

1. A method of packaging stacked chips, the method comprising:

2. The method of claim 1, wherein forming a second molding layer that encapsulates a plurality of the chips comprises:

Fixing the front faces of a plurality of chips on a temporary carrier plate;

And removing the temporary carrier plate.

3. The method of claim 2, wherein forming a redistribution layer on the first surface of the second molding layer in electrical connection with the molding via comprises:

4. The method of claim 2, wherein forming a second interconnect line layer on the second surface of the second molding layer and the second surface of the chip to electrically connect the molding via comprises:

5. The method of claim 1, wherein forming a second molding layer that encapsulates a plurality of the chips further comprises:

fixing the back surfaces of a plurality of chips on a temporary carrier plate;

And removing the temporary carrier plate.

6. The method of claim 5, wherein forming a redistribution layer on the first surface of the second molding layer in electrical connection with the molding via further comprises:

7. The method of claim 5, wherein forming a second interconnect line layer on the second surface of the second molding layer and the second surface of the chip electrically connects the molding via, further comprises:

8. The method according to any one of claims 1 to 7, wherein the stacking the plurality of the second chip modules on the substrate sequentially through the second interconnect wiring layer, stacking the first chip module to the uppermost layer of the second chip modules through the first interconnect wiring layer, includes:

9. The method of any one of claims 1 to 7, wherein the forming a plurality of chips comprises:

10. The method of any of claims 1 to 7, wherein forming a plurality of molding vias on the second molding layer comprises: