CN118872405A - Method for manufacturing bottom electrode of phase change memory - Google Patents
Method for manufacturing bottom electrode of phase change memory Download PDFInfo
- Publication number
- CN118872405A CN118872405A CN202380024157.5A CN202380024157A CN118872405A CN 118872405 A CN118872405 A CN 118872405A CN 202380024157 A CN202380024157 A CN 202380024157A CN 118872405 A CN118872405 A CN 118872405A
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- China
- Prior art keywords
- chamber
- opening
- titanium nitride
- argon
- nitride layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims abstract description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 41
- 229910052786 argon Inorganic materials 0.000 claims description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 20
- 238000005240 physical vapour deposition Methods 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 17
- 239000010936 titanium Substances 0.000 claims description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- -1 argon ions Chemical class 0.000 claims description 6
- 238000000605 extraction Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000013077 target material Substances 0.000 claims description 3
- 238000009423 ventilation Methods 0.000 claims description 3
- 238000001816 cooling Methods 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims description 2
- 238000007599 discharging Methods 0.000 claims 2
- 230000005611 electricity Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 claims 1
- 238000005086 pumping Methods 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 6
- 229910001873 dinitrogen Inorganic materials 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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- Semiconductor Memories (AREA)
Abstract
The invention provides a manufacturing method of a lower electrode of a phase change memory, and belongs to the field of semiconductor integrated circuit manufacturing. The method of the invention comprises the following steps: a semiconductor component providing step of: providing a semiconductor assembly comprising: a substrate, a silicon oxide layer formed on the substrate, a first opening formed in the silicon oxide layer, a conductive material filled in the lower part of the first opening, and a second opening formed in the upper part of the first opening; and forming a titanium nitride layer: forming a titanium nitride layer on the upper surface of the semiconductor component by using a PVD process, wherein the titanium nitride layer is formed on the upper surface of the silicon oxide layer and is filled in the second opening; a lower electrode forming step: and removing the part of the titanium nitride layer, which is positioned on the upper surface of the silicon oxide layer, by using a CMP process, so that the part of the titanium nitride layer, which is filled in the second opening, forms a lower electrode. The method of the invention can greatly improve the manufacturing speed of the lower electrode of the phase change memory under the condition of not affecting the film thickness uniformity and the resistance uniformity of the lower electrode.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a method for fabricating a bottom electrode of a phase change memory.
Background
In the prior art, a CVD (chemical vapor deposition) process is generally used for manufacturing the lower electrode of the phase change memory. As shown in fig. 7, a TiN (titanium nitride) layer 6 is formed on the upper surface of the semiconductor element 10 by a CVD process, and the second opening 5 of the semiconductor element 10 is also filled with TiN. The TiN layer on the upper surface of the semiconductor device 10 is then removed by a CMP (chemical mechanical polishing) process, leaving only the TiN layer in the second opening 5, thereby forming the lower electrode 7.
However, the lower electrode is manufactured by the CVD process at a relatively low speed, and it takes about 15 minutes to form the TiN layer 6.
Summary of The Invention
Technical problem
The invention aims to provide a manufacturing method of a lower electrode of a phase change memory capable of improving manufacturing speed.
Technical solution
The manufacturing method of the invention comprises the following steps:
A semiconductor component providing step of: providing a semiconductor assembly, the semiconductor assembly comprising: a substrate, a silicon oxide layer formed on the substrate, wherein a first opening is formed in the silicon oxide layer, a conductive material is filled in the lower part of the first opening, and a second opening is formed in the upper part of the first opening;
And forming a titanium nitride layer: forming a titanium nitride layer on the upper surface of the semiconductor component by using a physical vapor deposition process, wherein the titanium nitride layer is formed on the upper surface of the silicon oxide layer and is filled in the second opening;
a lower electrode forming step: and removing the part of the titanium nitride layer, which is positioned on the upper surface of the silicon oxide layer, by using a chemical mechanical polishing process, so that the part of the titanium nitride layer, which is filled in the second opening, forms the lower electrode.
Advantageous effects
The manufacturing method of the invention can greatly improve the manufacturing speed of the lower electrode of the phase change memory under the condition of not affecting the film thickness uniformity and the resistance uniformity of the lower electrode.
Drawings
FIG. 1 is a flow chart of a method of fabricating a bottom electrode of a phase change memory of the present invention;
FIG. 2 is a schematic diagram of a PVD (physical vapor deposition) system used in the fabrication method of the invention;
fig. 3 is a flowchart of TiN layer forming steps in the manufacturing method of the present invention;
Fig. 4 to 6 are schematic cross-sectional views of a semiconductor device at various stages of the manufacturing method of the invention; and
Fig. 7 is a schematic cross-sectional view of a semiconductor device of a method for manufacturing a phase change memory bottom electrode according to the related art.
Symbol description
10. Semiconductor assembly
1. Substrate and method for manufacturing the same
2. Silicon oxide layer
3. A first opening
4. Conductive material
5. A second opening
6 TiN layers
7. Lower electrode
100 PVD system
11. Chamber chamber
12 Ti (titanium) target material
13. Base seat
14. Wafer with a plurality of wafers
15. Air supply device
16. DC magnetic control device
17. Air extractor
Best mode for carrying out the invention
A method of manufacturing the lower electrode of the phase change memory according to the present invention is described below with reference to fig. 1 to 6.
As shown in fig. 1, the method for manufacturing the lower electrode of the phase change memory of the present invention includes: the semiconductor device provides step S100, tiN layer forming step S200, and lower electrode forming step S300. The respective steps will be specifically described below.
The semiconductor component providing step S100 is first described with reference to fig. 4: providing a semiconductor assembly 10, the semiconductor assembly 10 comprising: a substrate 1, a silicon oxide layer 2 formed on the substrate 1, a first opening 3 formed in the silicon oxide layer 2, a conductive material 4 filled in a lower portion of the first opening 3, and a second opening 5 formed in an upper portion of the first opening 3.
The semiconductor assembly 10 may be formed using methods commonly used in the art and will not be described in detail herein. In this embodiment, the conductive material 4 may be metallic tungsten. The invention is not limited thereto but in other embodiments the conductive material 4 may be other materials.
Preferably, the aspect ratio of the second opening 5 is 1:1.5. This is more advantageous for filling in a subsequent PVD process. However, the present invention is not limited thereto, and the aspect ratio of the second opening 5 may be other values, so long as the second opening 5 may be filled by PVD process.
In addition, in the present embodiment, the depth of the second opening 5 is 450 angstroms and the width is 600 angstroms. In a later CMP process the top of the silicon oxide layer 2 will also be removed by about 50 a, so the depth of the final second opening 5 is about 400 a. The invention is not limited thereto but the depth and width of the second openings 5 may be other values.
The TiN layer forming step S200 is described below with reference to fig. 5: a TiN layer 6 is formed on the upper surface of the semiconductor device 10 using a PVD process, and the TiN layer 6 is formed on the upper surface of the silicon oxide layer 2 and filled in the second opening 5. In the present embodiment, the TiN layer 6 is formed to have a thickness of 400 angstroms. However, the present invention is not limited thereto, and the TiN layer 6 may be any thickness suitable for manufacturing the lower electrode.
The TiN layer 6 may be formed using a PVD method commonly used in the art, and in this embodiment, as shown in fig. 2, the PVD system 100 used in the PVD process includes: the vacuum chamber comprises a chamber 11, a Ti target 12 arranged at the top of the chamber 11, a base 13 arranged at the bottom of the chamber 11, a wafer 14 placed on the base 13, a gas supply device 15 for ventilating the chamber 11, a direct current magnetic control device 16 electrically connected with the Ti target 12, and a gas extraction device 17 for extracting gas from the chamber 11.
In this embodiment, the gas supply device 5 is used to introduce argon and nitrogen into the chamber 11, and control the flow rates of the argon and nitrogen. The dc magnetic control device 16 is used to discharge argon gas in the chamber 11 and ionize the argon gas into argon ions.
The DC magnetic control device 16 may also control deposition power (dep power), as well as pulsed DC duty cycle (PDC duty).
As shown in fig. 3, the PVD process of the present embodiment includes:
Ventilation step S201: argon and nitrogen are introduced into the chamber 11 through the gas supply device 15.
An ignition step S202: argon gas in the chamber 11 is discharged by the direct current magnetic control device 16 to ionize the argon gas into argon ions, and nitrogen gas nitriding the surfaces of the wafer 14 and the Ti target 12 to form a TiN film on the surface of the Ti target 12.
Deposition step S203: the argon ions bombard the Ti target 12, bombard Ti ions in the Ti target 12 and TiN molecules in the TiN film, deposit on the upper surface of the wafer 14, and form the TiN layer 6.
And a cooling step S204: the dc magnetic control device 16 stops the discharge of the argon gas into the chamber 11, and the gas supply device 15 continues to supply the argon gas and the nitrogen gas into the chamber 11, thereby lowering the temperature of the wafer 14.
Air extraction step S205: the gas supply device 15 stops the supply of argon gas and nitrogen gas to the chamber 11, and the argon gas and nitrogen gas in the chamber 11 are evacuated by the evacuation device 17, thereby returning the chamber 11 to a vacuum state.
The manufacturing speed can be improved to a great extent by the method, and experimental results show that the TiN layer 6 can be formed only by about 25 seconds by adopting the PVD process. Compared with 15 minutes adopting a CVD process in the prior art, the manufacturing speed is greatly improved. In addition, the film thickness uniformity and the resistance uniformity of the TiN layer 6 formed by PVD process were also compared with those of the TiN layer formed by CVD process. The experimental results show that the film thickness uniformity and the resistance uniformity of the TiN layer 6 formed by PVD process are not lower than those of the TiN layer formed by CVD process.
The lower electrode forming step S300 is described below with reference to fig. 6: the portion of the TiN layer 6 located on the upper surface of the silicon oxide layer 2 is removed using a CMP process, so that the portion of the TiN layer 6 filled in the second opening 5 forms the lower electrode 7. The portion of TiN layer 6 on the upper surface of silicon oxide layer 2 may be removed using a CMP process commonly used in the art, and will not be described in detail herein.
Industrial applicability
The manufacturing method of the bottom electrode of the phase change memory can greatly improve the manufacturing speed of the bottom electrode of the phase change memory under the condition that the film thickness uniformity and the resistance uniformity of the bottom electrode are not affected.
Claims (3)
1. A method of fabricating a lower electrode of a phase change memory, comprising:
The semiconductor device provides step S100: providing a semiconductor component (10), the semiconductor component (10) comprising: a substrate (1), a silicon oxide layer (2) formed on the substrate (1), wherein a first opening (3) is formed in the silicon oxide layer (2), a conductive material (4) is filled in the lower part of the first opening (3), and a second opening (5) is formed in the upper part of the first opening (3);
Titanium nitride layer forming step S200: forming a titanium nitride layer (6) on the upper surface of the semiconductor component (10) by using a physical vapor deposition process, wherein the titanium nitride layer (6) is formed on the upper surface of the silicon oxide layer (2) and is filled in the second opening (5);
Lower electrode forming step S300: and removing the part of the titanium nitride layer (6) positioned on the upper surface of the silicon oxide layer (2) by using a chemical mechanical polishing process, so that the part of the titanium nitride layer (6) filled in the second opening (5) forms the lower electrode (7).
2. The method of manufacturing a bottom electrode of a phase change memory device according to claim 1,
A physical vapor deposition system (100) for use in the physical vapor deposition process includes: the chamber (11), set up titanium target (12) at chamber (11) top, set up base (13) of chamber (11) bottom, place wafer (14) on base (13), be used for to chamber (11) ventilation's air feeder (15), with direct current magnetic control device (16) that titanium target (12) electricity is connected, be used for follow air extraction device (17) of extracting air in chamber (11), the physical vapor deposition technology includes:
ventilation step S201: argon and nitrogen are introduced into the chamber (11) through the gas supply device (15);
An ignition step S202: discharging argon into the chamber (11) through the direct current magnetic control device (16) to ionize the argon into argon ions, nitriding the surfaces of the wafer (14) and the titanium target (12) by the nitrogen, and forming a titanium nitride film on the surface of the titanium target (12);
Deposition step S203: the argon ions bombard the titanium target material (12), so that titanium ions in the titanium target material (12) and titanium nitride molecules in the titanium nitride film are bombarded out and deposited on the upper surface of the wafer (14) to form the titanium nitride layer (6);
and a cooling step S204: the direct current magnetic control device (6) stops discharging argon into the chamber (11), and the gas supply device (15) continuously supplies argon and nitrogen into the chamber (11), so that the temperature of the wafer (14) is reduced;
Air extraction step S205: the air supply device (15) stops introducing argon and nitrogen into the chamber (11), and the argon and nitrogen in the chamber (11) are pumped out through the air pumping device (17), so that the chamber (11) is restored to a vacuum state.
3. The method of manufacturing a bottom electrode of a phase change memory device according to claim 1,
The depth-to-width ratio of the second opening (5) is 1:1.5.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2023103941 | 2023-06-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118872405A true CN118872405A (en) | 2024-10-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202380024157.5A Pending CN118872405A (en) | 2023-06-29 | 2023-06-29 | Method for manufacturing bottom electrode of phase change memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118872405A (en) |
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2023
- 2023-06-29 CN CN202380024157.5A patent/CN118872405A/en active Pending
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