CN118801827A - Small signal processing circuit - Google Patents

Abstract

The present invention discloses a small signal processing circuit, which includes: a bias module, a first amplifying module, a second amplifying module and a third amplifying module; the bias module is used to provide a first bias signal; the first input end of the first amplifying module receives the first input signal, the second input end of the first amplifying module is connected to the bias module, and the output end of the first amplifying module provides the first amplified signal to the first input end of the third amplifying module; the first input end of the second amplifying module receives the first input signal, the second input end of the second amplifying module is connected to the bias module, and the output end of the second amplifying module provides the second amplified signal to the second input end of the third amplifying module; the third input end of the third amplifying module is connected to the bias module, and the third amplifying module is used to process the first amplified signal, the second amplified signal and the first bias signal to output an electrical signal associated with the first input signal. The present invention is conducive to achieving a high signal-to-noise ratio.

Description

A small signal processing circuit

Technical Field

The present invention relates to the field of information technology, and in particular to a small signal processing circuit.

Background Art

The signal-to-noise ratio refers to the ratio of signal to noise in an electronic device or electronic system, specifically the ratio of the strength of the received useful signal to the strength of the received interference signal (noise and interference), referred to as "SNR".

A high signal-to-noise ratio means a large ratio of useful signal strength to interference signal strength, which means the device has a clean signal without noise. A low signal-to-noise ratio means a small ratio of useful signal strength to interference signal strength, which means the device has a messy signal with noise.

Common types of signals in electronic devices include small analog signals. The current circuits that process small analog signals have a low overall signal-to-noise ratio, which leads to signal transmission errors.

Summary of the invention

The present invention provides a small signal processing circuit to improve the problem of low signal-to-noise ratio of the existing circuit for processing analog small signals.

According to one aspect of the present invention, there is provided a small signal processing circuit, comprising: a bias module, a first amplification module, a second amplification module and a third amplification module;

The bias module is used to provide a first bias signal;

The first input end of the first amplifying module receives a first input signal, the second input end of the first amplifying module is connected to the bias module, and the output end of the first amplifying module provides a first amplified signal to the first input end of the third amplifying module;

The first input end of the second amplifying module receives the first input signal, the second input end of the second amplifying module is connected to the bias module, and the output end of the second amplifying module provides a second amplified signal to the second input end of the third amplifying module;

The third input end of the third amplifying module is connected to the bias module, and the third amplifying module is used to process the first amplified signal, the second amplified signal and the first bias signal to output a third amplified signal associated with the first input signal, and the third amplified signal is not associated with the first bias signal.

Further, the first amplification module includes a common-phase amplifier;

The non-inverting input terminal of the common-phase amplifier receives the first input signal, the inverting input terminal of the common-phase amplifier is connected to the bias module, and the output terminal of the common-phase amplifier is connected to the first input terminal of the third amplification module.

Furthermore, the first amplification module further includes a first resistor, a second resistor and a third resistor;

The non-inverting input terminal of the common-phase amplifier receives the first input signal through the first resistor, the inverting input terminal of the common-phase amplifier is connected to the bias module through the second resistor, and the output terminal of the common-phase amplifier is connected to the first input terminal of the third amplification module through the third resistor.

Further, the first input terminal of the second amplifying module and the second input terminal of the second amplifying module are shared;

The second amplification module includes an inverting amplifier;

The inverting input terminal of the inverting amplifier receives the first input signal, the inverting input terminal of the inverting amplifier is also connected to the bias module, the non-inverting input terminal of the inverting amplifier is grounded, and the output terminal of the inverting amplifier is connected to the second input terminal of the third amplification module.

Furthermore, the second amplification module further includes a fourth resistor, a fifth resistor and a sixth resistor;

The inverting input terminal of the inverting amplifier receives the first input signal through the fourth resistor, the inverting input terminal of the inverting amplifier is also connected to the bias module through the fifth resistor, and the output terminal of the inverting amplifier is connected to the second input terminal of the third amplification module through the sixth resistor.

Further, the amplification factor of the first amplification module is equal to the amplification factor of the second amplification module.

Further, the third amplification module includes a differential amplifier;

The positive input terminal of the differential amplifier is connected to the output terminal of the first amplifying module, the negative input terminal of the differential amplifier is connected to the output terminal of the second amplifying module, and the reference terminal of the differential amplifier is connected to the bias module.

Further, the bias module includes a microcontroller and an analog-to-digital converter;

The control end of the analog-to-digital converter is connected to the microcontroller, the output end of the analog-to-digital converter is respectively connected to the first amplification module, the second amplification module and the third amplification module, and the analog-to-digital converter is used to generate the first bias signal according to the instruction of the microcontroller.

Furthermore, the small signal processing circuit also includes a primary amplification module;

The input end of the primary amplifying module receives the first input signal, and the output end of the primary amplifying module is respectively connected to the first input end of the first amplifying module and the first input end of the second amplifying module.

Furthermore, the primary amplification module includes a low noise power amplifier.

In the present invention, the first amplification module processes the first input signal and the first bias signal to provide the first amplification signal to the third amplification module; the second amplification module processes the first input signal and the first bias signal to provide the second amplification signal to the third amplification module; the third amplification module processes the first amplification signal, the second amplification signal and the first bias signal to generate a third amplification signal, the third amplification signal is associated with the first input signal, and the third amplification signal is not associated with the first bias signal. In the present invention, any one of the first amplifying module and the second amplifying module amplifies the first input signal to modulate the first input signal at a high level, thereby reducing the interference of the noise signal generated by the chip of the module itself on the first input signal, so that there is no need to reduce the effective signal-to-noise ratio due to the noise generated by the chip of the module itself being inserted into the circuit; in addition, the first amplifying module and the second amplifying module process the first input signal in parallel, which can reduce the chip bandwidth requirement of the small signal processing circuit, and expand the range of chip performance options of the small signal processing circuit, thereby improving the design success probability of the small signal processing circuit and reducing the design cycle; in addition, the third amplified signal output by the third amplifying module is only associated with the first input signal, so as to achieve amplification of the first input signal without increasing noise, so that the signal-to-noise ratio of the small signal processing circuit is improved by multiple times, meeting the signal-to-noise ratio requirements of users, and facilitating the realization of a high signal-to-noise ratio.

It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG1 is a schematic diagram of a small signal processing circuit provided by an embodiment of the present invention.

FIG. 2 is a schematic diagram of another small signal processing circuit provided by an embodiment of the present invention.

FIG. 3 is a schematic diagram of another small signal processing circuit provided by an embodiment of the present invention.

DETAILED DESCRIPTION

In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

FIG1 is a schematic diagram of a small signal processing circuit provided by an embodiment of the present invention. As shown in FIG1 , the small signal processing circuit includes: a first amplifying module 101, a second amplifying module 102, a third amplifying module 103 and a biasing module 104; the biasing module 104 is used to provide a first bias signal Va; the first input end of the first amplifying module 101 receives the first input signal Sa, the second input end of the first amplifying module 101 is connected to the biasing module 104, and the output end of the first amplifying module 101 provides the first amplified signal Sa1 to the first input end IN1 of the third amplifying module 103; the second amplifying module 102 The first input terminal receives the first input signal Sa, the second input terminal of the second amplifying module 102 is connected to the bias module 104, and the output terminal of the second amplifying module 102 provides the second amplified signal Sa2 to the second input terminal IN2 of the third amplifying module 103; the third input terminal IN3 of the third amplifying module 103 is connected to the bias module 104, and the third amplifying module 103 is used to process the first amplified signal Sa1, the second amplified signal Sa2 and the first bias signal Va to output a third amplified signal Sa3 associated with the first input signal Sa, and the third amplified signal Sa3 is not associated with the first bias signal Va.

In this embodiment, the small signal processing circuit includes a bias module 104. The bias module 104 is used to provide a first bias signal Va. It can be understood that when the application scenario or device of the small signal processing circuit is different, the bias size required by the small signal processing circuit may be different, and the bias module 104 can provide bias signals of different sizes. The bias module 104 provides a bias signal of corresponding size according to the requirements of the small signal processing circuit. Specifically, in this embodiment, the bias module 104 provides the same bias signal, i.e., the first bias signal Va, to each module in the small signal processing circuit, and does not specifically limit the size of the first bias signal Va. Of course, if required by the product, the bias module can provide bias signals of different sizes to different modules in the small signal processing circuit.

The first input signal Sa is an original electrical signal to be processed by the small signal processing circuit, and the electrical signal may be an analog signal.

The small signal processing circuit includes a first amplifying module 101, and the first amplifying module 101 includes a chip capable of performing data processing such as amplification and calculation. The first amplifying module 101 includes at least two input terminals and one output terminal, the first input terminal of the first amplifying module 101 receives the first input signal Sa, the second input terminal of the first amplifying module 101 is connected to the bias module 104 to receive the first bias signal Va, and the output terminal of the first amplifying module 101 is connected to the first input terminal IN1 of the third amplifying module 103 to provide the first amplified signal Sa1 to the first input terminal IN1 of the third amplifying module 103. Specifically, the first amplifying module 101 performs data processing such as amplification on the received first input signal Sa, and then performs data processing such as calculation with the first bias signal Va, so as to generate the first amplified signal Sa1 and output it to the first input terminal IN1 of the third amplifying module 103. It can be understood that the first amplifying module 101 performs amplification processing on the first input signal Sa, and can modulate the first input signal Sa at a high level, thereby reducing the interference of the noise signal generated by the chip of the first amplifying module 101 itself on the first input signal Sa.

The amplification factor of the first amplifying module 101 can be selected as Na, and the first amplifying module 101 generates a first amplified signal Sa1 according to the first input signal Sa and the first bias signal Va. Wherein, Sa1=Va+Na*Sa, or Sa1=Va-Na*Sa.

The small signal processing circuit includes a second amplifying module 102, and the second amplifying module 102 includes a chip capable of performing data processing such as amplification and calculation. The second amplifying module 102 includes at least two input terminals and one output terminal, the first input terminal of the second amplifying module 102 receives the first input signal Sa, the second input terminal of the second amplifying module 102 is connected to the bias module 104 to receive the first bias signal Va, and the output terminal of the second amplifying module 102 is connected to the second input terminal IN2 of the third amplifying module 103 to provide the second amplified signal Sa2 to the second input terminal IN2 of the third amplifying module 103. Specifically, the second amplifying module 102 performs data processing such as amplification on the received first input signal Sa, and then performs data processing such as calculation with the first bias signal Va, thereby generating the second amplified signal Sa2 and outputting it to the second input terminal IN2 of the third amplifying module 103. It can be understood that the second amplifying module 102 performs amplification processing on the first input signal Sa, and can modulate the first input signal Sa at a high level, thereby reducing the interference of the noise signal generated by the chip of the second amplifying module 102 itself on the first input signal Sa.

The amplification factor of the second amplifying module 102 can be Nb, and the second amplifying module 102 generates a second amplified signal Sa2 according to the first input signal Sa and the first bias signal Va. Wherein, Sa2=Va+Nb*Sa, or Sa2=Va-Nb*Sa.

As described above, for any one of the first amplifying module 101 and the second amplifying module 102, the amplifying module can modulate the first input signal Sa to a high level by amplifying the first input signal Sa, thereby reducing the interference of the noise signal generated by the chip of the amplifying module itself on the first input signal Sa. In addition, the first amplifying module 101 and the second amplifying module 102 are two parallel amplifying modules, and the first input signal Sa is processed in parallel by two paths, thereby reducing the requirements of the small signal processing circuit on the chip bandwidth. The specific small signal processing circuit can reduce the chip bandwidth requirements by at least half, and the range of selectable chip performance based on the small signal processing circuit is widened, thereby improving the probability of successful design of the small signal processing circuit.

The small signal processing circuit includes a third amplifying module 103, and the third amplifying module 103 includes a chip capable of performing data processing such as amplification and differential operations. The third amplifying module 103 includes at least three input terminals and one output terminal, and the first input terminal IN1 of the third amplifying module 103 receives the first amplified signal Sa1 provided by the first amplifying module 101, the second input terminal IN2 of the third amplifying module 103 receives the second amplified signal Sa2 provided by the second amplifying module 102, and the third input terminal IN3 of the third amplifying module 103 receives the first bias signal Va provided by the bias module 104. Specifically, the third amplifying module 103 uses the first bias signal Va as a common-mode reference voltage, performs data processing such as differential amplification on the received first amplified signal Sa1 and the second amplified signal Sa2, thereby generating a third amplified signal Sa3 and outputting it to other circuits through the output terminal OUT.

If Sa1=Va+Na*Sa, Sa2=Va+Nb*Sa, then Sa3=（Na-Nb）*Sa. Obviously, the first input signal Sa is amplified by (Na-Nb) times by the small signal processing circuit.

If Sa1=Va+Na*Sa, Sa2=Va-Nb*Sa, then Sa3=（Na+Nb）*Sa. Obviously, the first input signal Sa is amplified by (Na+Nb) times by the small signal processing circuit.

If Sa1=Va-Na*Sa, Sa2=Va+Nb*Sa, then Sa3=（-Na-Nb）*Sa. Obviously, the first input signal Sa is amplified by (-Na-Nb) times by the small signal processing circuit.

If Sa1=Va-Na*Sa, Sa2=Va-Nb*Sa, then Sa3=(Nb-Na)*Sa. Obviously, the first input signal Sa is amplified by (Nb-Na) times by the small signal processing circuit.

As described above, the third amplified signal Sa3 output by the third amplification module 103 is only associated with the first input signal Sa. The third amplification module 103 can perform differential amplification processing to achieve demodulation of the first bias signal Va, and can also simultaneously achieve amplification of the first input signal Sa without increasing noise, thereby achieving a multiple increase in the signal-to-noise ratio of the small signal processing circuit.

In the present invention, the first amplification module processes the first input signal and the first bias signal to provide the first amplification signal to the third amplification module; the second amplification module processes the first input signal and the first bias signal to provide the second amplification signal to the third amplification module; the third amplification module processes the first amplification signal, the second amplification signal and the first bias signal to generate a third amplification signal, the third amplification signal is associated with the first input signal, and the third amplification signal is not associated with the first bias signal. In the present invention, any one of the first amplifying module and the second amplifying module amplifies the first input signal to modulate the first input signal at a high level, thereby reducing the interference of the noise signal generated by the chip of the module itself on the first input signal, so that there is no need to reduce the effective signal-to-noise ratio due to the noise generated by the chip of the module itself being inserted into the circuit; in addition, the first amplifying module and the second amplifying module process the first input signal in parallel, which can reduce the chip bandwidth requirement of the small signal processing circuit, and expand the range of chip performance options of the small signal processing circuit, thereby improving the design success probability of the small signal processing circuit and reducing the design cycle; in addition, the third amplified signal output by the third amplifying module is only associated with the first input signal, so as to achieve amplification of the first input signal without increasing noise, so that the signal-to-noise ratio of the small signal processing circuit is improved by multiple times, meeting the signal-to-noise ratio requirements of users, and facilitating the realization of a high signal-to-noise ratio.

The optional small signal processing circuit also includes a primary amplification module; the input end of the primary amplification module receives the first input signal, and the output end of the primary amplification module is respectively connected to the first input end of the first amplification module and the first input end of the second amplification module.

FIG2 is a schematic diagram of another small signal processing circuit provided by an embodiment of the present invention. As shown in FIG2 , the small signal processing circuit further includes a primary amplification module 105; the input end of the primary amplification module 105 receives a first input signal Sa, and the primary amplification module 105 amplifies and processes the first input signal Sa and then outputs it. The signal output by the primary amplification module 105 is a first-stage amplified signal Sa'. The output end of the primary amplification module 105 is connected to the first input end of the first amplification module 101, so the electrical signal received by the first input end of the first amplification module 101 is the signal Sa' after the first-stage amplification processing of the first input signal Sa by the primary amplification module 105. The output end of the primary amplification module 105 is connected to the first input end of the second amplification module 102, and the electrical signal received by the first input end of the second amplification module 102 is the signal Sa' after the first input signal Sa is amplified by the primary amplification module 105.

As described above, the small signal processing circuit shown in FIG2 includes a three-stage amplifier circuit. The first-stage amplifier circuit includes a primary amplifier module 105, and the first-stage amplifier circuit performs a first-stage amplification process on the initial first input signal Sa. The second-stage amplifier circuit includes a first amplifier module 101 and a second amplifier module 102, and the second-stage amplifier circuit performs a second-stage amplification process on the output signal Sa' of the first-stage amplifier circuit. The third-stage amplifier circuit includes a third amplifier module 103, and the third-stage amplifier circuit performs a third-stage amplification process on the output signal of the second-stage amplifier circuit.

The small signal processing circuit shown in FIG1 includes a two-stage amplifier circuit. The first-stage amplifier circuit includes a first amplifier module 101 and a second amplifier module 102, and the first-stage amplifier circuit directly performs a first-stage amplification process on the initial first input signal Sa. The second-stage amplifier circuit includes a third amplifier module 103, and the second-stage amplifier circuit performs a second-stage amplification process on the output signal of the first-stage amplifier circuit.

The optional primary amplification module includes a low noise power amplifier. The low noise power (LNA) amplifier has low noise, and its low noise has little interference with the first input signal Sa, so it will not reduce the effective signal-to-noise ratio of the small signal processing circuit.

Compared with FIG. 1 , FIG. 2 adds a primary amplification module 105 , which performs a first-stage amplification process on the initial first input signal Sa and then transmits it to the first amplification module 101 and the second amplification module 102 .

Based on the small signal processing circuit shown in FIG2 , its small signal signal-to-noise ratio is improved by multiple times, which meets the signal-to-noise ratio requirements of users and is conducive to achieving a high signal-to-noise ratio. The primary amplification module itself has low noise, and its low noise has little interference with the first input signal Sa, so it will not reduce the effective signal-to-noise ratio of the small signal processing circuit, so the requirements for the LNA op amp model of the selectable primary amplification module are widened, and the requirements for the total noise performance parameters of the selectable LNA op amp model can be widened. In addition, the second-stage amplification circuit amplifies and raises the first input signal Sa after the first stage amplification, so the chip noise itself in the second-stage amplification circuit interferes less with the circuit, so the noise of the second-stage amplification circuit is inserted into the circuit and will not significantly reduce the effective signal-to-noise ratio. Based on this, the amplifier bandwidth performance parameter requirements of the first amplification module and the second amplification module can be widened, which is conducive to achieving a high signal-to-noise ratio. Under the same level of chip performance, the small signal processing circuit of this embodiment can effectively improve the minimum resolution of the system, and its small signal signal-to-noise ratio requirement is not limited to the noise size of the primary amplification module, the first amplification module, and the second amplification module, which reduces the design difficulty and cost of the small signal processing circuit and improves the design success probability of the small signal processing circuit.

FIG3 is a schematic diagram of another small signal processing circuit provided by an embodiment of the present invention. As shown in FIG3, the optional first amplification module 101 includes a common-phase amplifier 201; the non-inverting input terminal (+) of the common-phase amplifier 201 receives the first input signal Sa, the inverting input terminal (-) of the common-phase amplifier 201 is connected to the bias module 104, and the output terminal of the common-phase amplifier 201 is connected to the first input terminal IN1 of the third amplification module 103. The optional first amplification module 101 also includes a first resistor R11, a second resistor R12, and a third resistor R13; the non-inverting input terminal (+) of the common-phase amplifier 201 receives the first input signal Sa through the first resistor R11, the inverting input terminal (-) of the common-phase amplifier 201 is connected to the bias module 104 through the second resistor R12, and the output terminal of the common-phase amplifier 201 is connected to the first input terminal IN1 of the third amplification module 103 through the third resistor R13.

In this embodiment, the non-inverting input terminal (+) of the common-phase amplifier 201 receives the first input signal Sa through the first resistor R11, and the non-inverting input terminal (+) of the common-phase amplifier 201 is also connected to the ground GND through the resistor R14. The inverting input terminal (-) of the common-phase amplifier 201 is connected to the bias module 104 through the second resistor R12 to receive the first bias signal Va, and the inverting input terminal (-) of the common-phase amplifier 201 is also connected to the first power supply terminal VCC1 through the resistor R15 and the resistor R16. The inverting input terminal (-) of the common-phase amplifier 201 is also connected to the output terminal of the common-phase amplifier 201 through the resistor R15, wherein the first power supply terminal VCC1 provides a positive power supply signal, for example, the first power supply terminal VCC1 provides a +5V voltage signal. The output terminal of the common-phase amplifier 201 is connected to the first input terminal IN1 of the third amplification module 103 through the third resistor R13.

It can be understood that the port structure of the common-phase amplifier 201 shown in FIG. 3 is only part of the ports of the common-phase amplifier. In practice, the common-phase amplifier also has other ports. Only the ports related to signal transmission in the circuit are shown here.

As shown in FIG3 , the first input terminal of the optional second amplifying module 102 and the second input terminal of the second amplifying module 102 are shared; the second amplifying module 102 includes an inverting amplifier 202; the inverting input terminal (-) of the inverting amplifier 202 receives the first input signal Sa, the inverting input terminal (-) of the inverting amplifier 202 is also connected to the bias module 104, the non-inverting input terminal (+) of the inverting amplifier 202 is grounded, and the output terminal of the inverting amplifier 202 is connected to the second input terminal IN2 of the third amplifying module 103. The optional second amplifying module 102 also includes a fourth resistor R21, a fifth resistor R22, and a sixth resistor R23; the inverting input terminal (-) of the inverting amplifier 202 receives the first input signal Sa through the fourth resistor R21, the inverting input terminal (-) of the inverting amplifier 202 is also connected to the bias module 104 through the fifth resistor R22, and the output terminal of the inverting amplifier 202 is connected to the second input terminal IN3 of the third amplifying module 103 through the sixth resistor R23.

In this embodiment, the first input terminal of the second amplifying module 102 and the second input terminal of the second amplifying module 102 are the same port, so the first input terminal of the second amplifying module 102 receives the first input signal Sa and the first bias signal Va provided by the bias module 104 simultaneously.

The second amplification module 102 includes an inverting amplifier 202. The non-inverting input terminal (+) of the inverting amplifier 202 is grounded to GND through a resistor R24. The inverting input terminal (-) of the inverting amplifier 202 receives the first input signal Sa through a fourth resistor R21, and the inverting input terminal (-) of the inverting amplifier 202 is also connected to the bias module 104 through a fifth resistor R22 to receive the first bias signal Va. The inverting input terminal (-) of the inverting amplifier 202 is also connected to the first power supply terminal VCC1 through resistors R25 and R26, and the inverting input terminal (-) of the inverting amplifier 202 is also connected to the output terminal of the inverting amplifier 202 through a resistor R25, wherein the first power supply terminal VCC1 provides a positive power supply signal, for example, the first power supply terminal VCC1 provides a +5V voltage signal. The output terminal of the inverting amplifier 202 is connected to the second input terminal IN3 of the third amplification module 103 through a sixth resistor R23.

It can be understood that the port structure of the inverting amplifier 202 shown in Figure 3 is only part of the ports of the inverting amplifier. In practice, the inverting amplifier also has other ports, and only the ports related to signal transmission in the circuit are shown here. The combination of the in-phase amplifier 201 and the inverting amplifier 202 can realize the voltage bias modulation function.

Referring to Figure 3, the optional third amplification module 103 includes a differential amplifier 203; the positive input terminal (+IN) of the differential amplifier 203 is connected to the output terminal of the first amplification module 101, the negative input terminal (-IN) of the differential amplifier 203 is connected to the output terminal of the second amplification module 102, and the reference terminal (REF) of the differential amplifier 203 is connected to the bias module 104.

In this embodiment, the differential amplifier 203 can be a differential amplifier based on a fully differential input. The positive input terminal (+IN) of the differential amplifier 203 is connected to the output terminal of the in-phase amplifier 201 through a resistor R13, the negative input terminal (-IN) of the differential amplifier 203 is connected to the output terminal of the inverting amplifier 202 through a resistor R23, and the reference terminal (REF) of the differential amplifier 203 is connected to the bias module 104 to receive the first bias signal Va. It should be noted that in other embodiments, the optional differential amplifier can be a differential amplifier based on a non-fully differential input; in this case, the first bias signal provided by the bias module is transmitted to the circuit structure that controls the differential amplifier, without being directly transmitted to the differential amplifier.

The differential amplifier 203 also has a sensing terminal (SENSE), and the sensing terminal (SENSE) of the differential amplifier 203 is connected to the positive input terminal (+IN) of the differential amplifier 203 through a resistor R31. The differential amplifier 203 also has a negative power supply terminal (V-), and the negative power supply terminal (V-) of the differential amplifier 203 receives a negative voltage signal VSS1, and the negative voltage signal VSS1 can be selected to provide a -5V voltage signal. The differential amplifier 203 also has a positive power supply terminal (V+), and the positive power supply terminal (V+) of the differential amplifier 203 receives a positive voltage signal VCC1, and the positive voltage signal VCC1 can be selected to provide a +5V voltage signal. The output terminal (OUT) of the differential amplifier 203 outputs an electrical signal through a resistor R32.

It can be understood that the port structure of the differential amplifier 203 shown in FIG3 is only part of the ports of the differential amplifier. In practice, the differential amplifier also has other ports, and only the ports related to signal transmission in the circuit are shown here. The differential amplifier 203 realizes the functions of multiple amplification of useful small signals and demodulation of bias voltage.

As shown in FIG3 , the optional bias module 104 includes a microcontroller 204 and an analog-to-digital converter 205; the control end of the analog-to-digital converter 205 is connected to the microcontroller 204, and the output end of the analog-to-digital converter 205 is respectively connected to the first amplification module 101, the second amplification module 102 and the third amplification module 103, and the analog-to-digital converter 205 is used to generate a first bias signal Va according to the instruction of the microcontroller 204. ADC is the abbreviation of analog-to-digital converter.

In this embodiment, the bias module 104 includes a microcontroller 204 and an analog-to-digital converter 205. The control end of the analog-to-digital converter 205 is connected to the microcontroller 204, and the microcontroller 204 sends a control instruction to the analog-to-digital converter 205. The analog-to-digital converter 205 generates a corresponding first bias signal Va according to the control instruction of the microcontroller 204, and the first bias signal Va can be a digital signal.

For example, if the bias signal required by the small signal processing circuit is (+5V), the microcontroller 204 sends a control instruction to the analog-to-digital converter 205, and the control instruction carries the information of "providing a (+5V) bias signal". Then the analog-to-digital converter 205 generates a corresponding first bias signal Va according to the control instruction of the microcontroller 204, and the first bias signal Va is (+5V).

Alternatively, if the bias signal required by the small signal processing circuit is (-1.4V), the microcontroller 204 sends a control instruction to the analog-to-digital converter 205, and the control instruction carries the information of "providing a (-1.4V) bias signal". Then the analog-to-digital converter 205 generates a corresponding first bias signal Va according to the control instruction of the microcontroller 204, and the first bias signal Va is (-1.4V).

When the bias signal required by the small signal processing circuit changes, the microcontroller 204 instructs the analog-to-digital converter 205 to generate a bias signal of a corresponding magnitude.

The gain of the optional in-phase amplifier 201 is Na, the first input signal is Sa, the first bias signal is Va, and the output signal of the in-phase amplifier 201 is Sa1, then Sa1=Va+Na*Sa. The gain of the optional inverting amplifier 202 is Nb, the first input signal is Sa, the first bias signal is Va, and the output signal of the inverting amplifier 202 is Sa2, then Sa2=Va-Nb*Sa.

The output signal of the differential amplifier 203 is Sa3, then Sa3=(Na+Nb)*Sa. Obviously, the first input signal Sa is amplified by (Na+Nb) times by the small signal processing circuit.

The optional amplification factor of the first amplification module is equal to the amplification factor of the second amplification module. As shown in FIG3 , the optional amplification factors of the in-phase amplifier 201 and the inverting amplifier 202 are both Na, the first input signal is Sa, and the first bias signal is Va, then the output signal Sa3 of the differential amplifier 203 is, Sa3=2*Na*Sa, and it is obvious that the first input signal Sa is amplified by 2*Na times by the small signal processing circuit.

The small signal processing circuit provided in this embodiment can be used to process analog small signals, such as the front-end analog small signals used in contactless defect detectors. The circuit can achieve an overall improvement in the signal-to-noise ratio of small signals, and a small signal that meets the signal-to-noise ratio requirement can be obtained without configuring a filter, which is conducive to achieving a high signal-to-noise ratio.

It can be understood that the small signal processing circuit as described above is only the main part of the circuit structure. If the small signal processing circuit is used in instruments and equipment, it may be necessary to configure the small signal processing circuit with corresponding other components or structures, which will not be described in detail in the present invention. In addition, in the circuit structure of the small signal processing circuit as described above, the specific parameters of each component are not limited, and relevant practitioners can reasonably select suitable components according to the needs of the product, which will not be described in detail in the present invention.

The small signal processing circuit provided in this embodiment can achieve the ideal small signal signal-to-noise ratio requirement. The inherent low noise of the primary amplification module, the inherent noise of the first amplification module, and the inherent noise of the second amplification module will not seriously damage the effective signal-to-noise ratio, and is therefore not limited to the inherent low noise of the primary amplification module, the inherent noise of the first amplification module, and the inherent noise of the second amplification module. Based on this, when relevant practitioners design circuits, the selectable range of the primary amplification module, the selectable range of the first amplification module, and the selectable range of the second amplification module are broadened, the selectable range of the primary amplification module is not limited to high-performance op amps, and the selectable range of the first amplification module and the second amplification module is not limited to high amplification gain, thereby reducing the difficulty of chip selection and design cost in the small signal processing circuit.

It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A small signal processing circuit, comprising: the device comprises a bias module, a first amplifying module, a second amplifying module and a third amplifying module;

the bias module is used for providing a first bias signal;

A first input end of the first amplifying module receives a first input signal, a second input end of the first amplifying module is connected with the biasing module, and an output end of the first amplifying module provides a first amplifying signal for a first input end of the third amplifying module;

The first input end of the second amplifying module receives the first input signal, the second input end of the second amplifying module is connected with the biasing module, and the output end of the second amplifying module provides a second amplifying signal for the second input end of the third amplifying module;

the third input end of the third amplifying module is connected with the bias module, and the third amplifying module is used for processing the first amplifying signal, the second amplifying signal and the first bias signal so as to output a third amplifying signal associated with the first input signal, and the third amplifying signal is not associated with the first bias signal.

2. The small signal processing circuit as in claim 1, wherein the first amplification module comprises an in-phase amplifier;

The non-inverting input end of the in-phase amplifier receives the first input signal, the inverting input end of the in-phase amplifier is connected with the biasing module, and the output end of the in-phase amplifier is connected with the first input end of the third amplifying module.

3. The small signal processing circuit as in claim 2, wherein the first amplification module further comprises a first resistor, a second resistor, and a third resistor;

The non-inverting input end of the in-phase amplifier receives the first input signal through the first resistor, the inverting input end of the in-phase amplifier is connected with the biasing module through the second resistor, and the output end of the in-phase amplifier is connected with the first input end of the third amplifying module through the third resistor.

4. The small signal processing circuit as in claim 1, wherein the first input of the second amplification module and the second input of the second amplification module are common;

The second amplification module comprises an inverting amplifier;

The inverting input end of the inverting amplifier receives the first input signal, the inverting input end of the inverting amplifier is also connected with the biasing module, the non-inverting input end of the inverting amplifier is grounded, and the output end of the inverting amplifier is connected with the second input end of the third amplifying module.

5. The small signal processing circuit as in claim 4, wherein the second amplification module further comprises a fourth resistor, a fifth resistor, and a sixth resistor;

The inverting input end of the inverting amplifier receives the first input signal through the fourth resistor, the inverting input end of the inverting amplifier is also connected with the biasing module through the fifth resistor, and the output end of the inverting amplifier is connected with the second input end of the third amplifying module through the sixth resistor.

6. The small signal processing circuit as recited in claim 1, wherein the amplification factor of the first amplification module is equal to the amplification factor of the second amplification module.

7. The small signal processing circuit as in claim 1, wherein the third amplification module comprises a differential amplifier;

The positive input end of the differential amplifier is connected with the output end of the first amplifying module, the negative input end of the differential amplifier is connected with the output end of the second amplifying module, and the reference end of the differential amplifier is connected with the biasing module.

8. The small signal processing circuit as in claim 1, wherein the bias module comprises a microcontroller and an analog-to-digital converter;

the control end of the analog-to-digital converter is connected with the microcontroller, the output end of the analog-to-digital converter is respectively connected with the first amplifying module, the second amplifying module and the third amplifying module, and the analog-to-digital converter is used for generating the first bias signal according to the instruction of the microcontroller.

9. The small signal processing circuit as in claim 1, further comprising a primary amplification module;

the input end of the primary amplifying module receives the first input signal, and the output end of the primary amplifying module is respectively connected with the first input end of the first amplifying module and the first input end of the second amplifying module.

10. The small signal processing circuit as in claim 9, wherein the primary amplification module comprises a low noise power amplifier.