CN118801827A - Small signal processing circuit - Google Patents

Abstract

The invention discloses a small signal processing circuit, which comprises: the device comprises a bias module, a first amplifying module, a second amplifying module and a third amplifying module; the bias module is used for providing a first bias signal; the first input end of the first amplifying module receives a first input signal, the second input end of the first amplifying module is connected with the biasing module, and the output end of the first amplifying module provides a first amplified signal for the first input end of the third amplifying module; the first input end of the second amplifying module receives the first input signal, the second input end of the second amplifying module is connected with the biasing module, and the output end of the second amplifying module provides a second amplifying signal for the second input end of the third amplifying module; the third input end of the third amplifying module is connected with the biasing module, and the third amplifying module is used for processing the first amplifying signal, the second amplifying signal and the first biasing signal so as to output an electric signal associated with the first input signal. The invention is beneficial to realizing high signal-to-noise ratio.

Description

Small signal processing circuit

Technical Field

The invention relates to the technical field of information, in particular to a small signal processing circuit.

Background

The signal-to-noise ratio refers to the ratio of signal to noise in an electronic device or electronic system, specifically the ratio of the received useful signal strength to the received interference signal (noise and interference) strength, and is simply referred to as "signal-to-noise ratio".

The signal-to-noise ratio, i.e., the ratio of useful signal strength to interfering signal strength, is high, then the reaction is clean and noiseless in the device. A low signal-to-noise ratio, i.e. a small ratio of useful signal strength to interfering signal strength, then the reaction is that the signal is noisy in the device.

The common signal types in electronic devices include analog small signals, and the current circuits for processing the analog small signals have low overall signal-to-noise ratio, which leads to signal transmission errors.

Disclosure of Invention

The invention provides a small signal processing circuit which is used for solving the problem of low signal-to-noise ratio of the traditional circuit for processing the analog small signal.

According to an aspect of the present invention, there is provided a small signal processing circuit including: the device comprises a bias module, a first amplifying module, a second amplifying module and a third amplifying module;

the bias module is used for providing a first bias signal;

A first input end of the first amplifying module receives a first input signal, a second input end of the first amplifying module is connected with the biasing module, and an output end of the first amplifying module provides a first amplifying signal for a first input end of the third amplifying module;

The first input end of the second amplifying module receives the first input signal, the second input end of the second amplifying module is connected with the biasing module, and the output end of the second amplifying module provides a second amplifying signal for the second input end of the third amplifying module;

the third input end of the third amplifying module is connected with the bias module, and the third amplifying module is used for processing the first amplifying signal, the second amplifying signal and the first bias signal so as to output a third amplifying signal associated with the first input signal, and the third amplifying signal is not associated with the first bias signal.

Further, the first amplification module comprises an in-phase amplifier;

The non-inverting input end of the in-phase amplifier receives the first input signal, the inverting input end of the in-phase amplifier is connected with the biasing module, and the output end of the in-phase amplifier is connected with the first input end of the third amplifying module.

Further, the first amplifying module further comprises a first resistor, a second resistor and a third resistor;

The non-inverting input end of the in-phase amplifier receives the first input signal through the first resistor, the inverting input end of the in-phase amplifier is connected with the biasing module through the second resistor, and the output end of the in-phase amplifier is connected with the first input end of the third amplifying module through the third resistor.

Further, the first input of the second amplification module and the second input of the second amplification module are in common;

The second amplification module comprises an inverting amplifier;

The inverting input end of the inverting amplifier receives the first input signal, the inverting input end of the inverting amplifier is also connected with the biasing module, the non-inverting input end of the inverting amplifier is grounded, and the output end of the inverting amplifier is connected with the second input end of the third amplifying module.

Further, the second amplifying module further comprises a fourth resistor, a fifth resistor and a sixth resistor;

The inverting input end of the inverting amplifier receives the first input signal through the fourth resistor, the inverting input end of the inverting amplifier is also connected with the biasing module through the fifth resistor, and the output end of the inverting amplifier is connected with the second input end of the third amplifying module through the sixth resistor.

Further, the amplification factor of the first amplification module is equal to the amplification factor of the second amplification module.

Further, the third amplification module comprises a differential amplifier;

The positive input end of the differential amplifier is connected with the output end of the first amplifying module, the negative input end of the differential amplifier is connected with the output end of the second amplifying module, and the reference end of the differential amplifier is connected with the biasing module.

Further, the bias module comprises a microcontroller and an analog-to-digital converter;

the control end of the analog-to-digital converter is connected with the microcontroller, the output end of the analog-to-digital converter is respectively connected with the first amplifying module, the second amplifying module and the third amplifying module, and the analog-to-digital converter is used for generating the first bias signal according to the instruction of the microcontroller.

Further, the small signal processing circuit further comprises a primary amplifying module;

the input end of the primary amplifying module receives the first input signal, and the output end of the primary amplifying module is respectively connected with the first input end of the first amplifying module and the first input end of the second amplifying module.

Further, the primary amplification module includes a low noise power amplifier.

In the invention, a first amplifying module processes a first input signal and a first bias signal to provide a first amplifying signal to a third amplifying module; the second amplifying module processes the first input signal and the first bias signal to provide a second amplified signal to the third amplifying module; the third amplification module processes the first amplified signal, the second amplified signal, and the first bias signal to generate a third amplified signal, the third amplified signal being associated with the first input signal and the third amplified signal being uncorrelated with the first bias signal. In the invention, any one of the first amplifying module and the second amplifying module amplifies the first input signal to modulate the first input signal on a high level, thereby reducing the interference of noise signals generated by the chip of the module on the first input signal, and reducing the effective signal-to-noise ratio without inserting noise generated by the chip of the module into a circuit; in addition, the first input signal is processed in parallel through the first amplifying module and the second amplifying module, so that the requirement of the small signal processing circuit on the chip bandwidth can be reduced, the selectable range of the chip performance of the small signal processing circuit is widened, the design success probability of the small signal processing circuit can be improved, and the design period is reduced; in addition, the third amplified signal output by the third amplifying module is only associated with the first input signal, so that the amplification of the first input signal is realized under the condition of not increasing noise, the signal to noise ratio of the small signal processing circuit is improved multiple times, the signal to noise ratio requirement required by a user is met, and the high signal to noise ratio is realized.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a small signal processing circuit according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of another small signal processing circuit according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of yet another small signal processing circuit according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic diagram of a small signal processing circuit according to an embodiment of the present invention, as shown in fig. 1, the small signal processing circuit includes: a first amplification module 101, a second amplification module 102, a third amplification module 103, and a bias module 104; the bias module 104 is configured to provide a first bias signal Va; a first input end of the first amplifying module 101 receives the first input signal Sa, a second input end of the first amplifying module 101 is connected with the biasing module 104, and an output end of the first amplifying module 101 provides the first amplified signal Sa1 to a first input end IN1 of the third amplifying module 103; a first input end of the second amplifying module 102 receives the first input signal Sa, a second input end of the second amplifying module 102 is connected with the biasing module 104, and an output end of the second amplifying module 102 provides a second amplified signal Sa2 to a second input end IN2 of the third amplifying module 103; the third input terminal IN3 of the third amplifying module 103 is connected to the bias module 104, and the third amplifying module 103 is configured to process the first amplified signal Sa1, the second amplified signal Sa2, and the first bias signal Va to output a third amplified signal Sa3 associated with the first input signal Sa, where the third amplified signal Sa3 is not associated with the first bias signal Va.

In this embodiment, the small signal processing circuit includes a bias module 104. The bias module 104 is configured to provide a first bias signal Va. It will be appreciated that when the small signal processing circuit is used in a different scenario or device, the bias voltage required by the small signal processing circuit may be different, the bias module 104 may provide bias voltage signals of different magnitudes, and the bias module 104 may provide bias voltage signals of corresponding magnitudes according to the requirements of the small signal processing circuit. Specifically, the bias module 104 in this embodiment provides the same bias signal, i.e., the first bias signal Va, to each module in the small signal processing circuit, and the magnitude of the first bias signal Va is not particularly limited. Of course, the bias module may provide bias signals of different magnitudes to different modules in the small signal processing circuit, as desired for the product.

The first input signal Sa is an original electrical signal to be processed by the small signal processing circuit, and the electrical signal may be an analog signal.

The small signal processing circuit includes a first amplification module 101, and the first amplification module 101 includes a chip capable of performing data processing such as amplification and operation. The first amplifying module 101 includes at least two input terminals and an output terminal, the first input terminal of the first amplifying module 101 receives the first input signal Sa, the second input terminal of the first amplifying module 101 is connected to the bias module 104 to receive the first bias signal Va, and the output terminal of the first amplifying module 101 is connected to the first input terminal IN1 of the third amplifying module 103 to provide the first amplified signal Sa1 to the first input terminal IN1 of the third amplifying module 103. Specifically, the first amplifying module 101 performs data processing such as amplifying on the received first input signal Sa, and performs data processing such as operation on the received first input signal Sa and the received first bias signal Va, so as to generate a first amplified signal Sa1 and output the first amplified signal Sa1 to the first input terminal IN1 of the third amplifying module 103. It will be appreciated that the first amplifying module 101 amplifies the first input signal Sa, and may modulate the first input signal Sa at a high level, so that interference of noise signals generated by the chip of the first amplifying module 101 on the first input signal Sa may be reduced.

The first amplification module 101 generates a first amplified signal Sa1 according to the first input signal Sa and the first bias signal Va if the amplification factor of the optional first amplification module 101 is Na. Wherein, sa1 = Va + Na x Sa, or Sa1 = Va-Na x Sa.

The small signal processing circuit includes a second amplification module 102, and the second amplification module 102 includes a chip capable of performing data processing such as amplification and operation. The second amplifying module 102 includes at least two input terminals and an output terminal, the first input terminal of the second amplifying module 102 receives the first input signal Sa, the second input terminal of the second amplifying module 102 is connected to the bias module 104 to receive the first bias signal Va, and the output terminal of the second amplifying module 102 is connected to the second input terminal IN2 of the third amplifying module 103 to provide the second amplified signal Sa2 to the second input terminal IN2 of the third amplifying module 103. Specifically, the second amplifying module 102 performs data processing such as amplifying on the received first input signal Sa, and performs data processing such as operation on the received first input signal Sa and the received first bias signal Va, so as to generate a second amplified signal Sa2 and output the second amplified signal Sa2 to the second input terminal IN2 of the third amplifying module 103. It can be appreciated that the second amplifying module 102 amplifies the first input signal Sa, and may modulate the first input signal Sa on a high level, so that interference of noise signals generated by the chip of the second amplifying module 102 on the first input signal Sa may be reduced.

The second amplification module 102 generates a second amplified signal Sa2 according to the first input signal Sa and the first bias signal Va if the amplification factor of the optional second amplification module 102 is Nb. Wherein, sa2 = Va + Nb, or Sa2 = Va-Nb Sa.

As described above, for any one of the first amplification module 101 and the second amplification module 102, the amplification module can modulate the first input signal Sa on a high level by performing amplification processing on the first input signal Sa, so that interference of noise signals generated by its own chip on the first input signal Sa can be reduced. In addition, the first amplifying module 101 and the second amplifying module 102 are used as two parallel amplifying modules, and process the first input signal Sa through two parallel paths, so that the requirement of the small signal processing circuit on the chip bandwidth is reduced, the specific small signal processing circuit can reduce at least half of the chip bandwidth requirement, the selectable range of the chip performance of the small signal processing circuit is widened based on the small signal processing circuit, and the design success probability of the small signal processing circuit is improved.

The small signal processing circuit includes a third amplification module 103, and the third amplification module 103 includes a chip capable of performing data processing such as amplification and differential operation. The third amplifying module 103 includes at least three input terminals and one output terminal, the first input terminal IN1 of the third amplifying module 103 receives the first amplified signal Sa1 provided by the first amplifying module 101, the second input terminal IN2 of the third amplifying module 103 receives the second amplified signal Sa2 provided by the second amplifying module 102, and the third input terminal IN3 of the third amplifying module 103 receives the first bias signal Va provided by the bias module 104. Specifically, the third amplifying module 103 uses the first bias signal Va as a common mode reference voltage, performs data processing such as differential amplification on the received first amplified signal Sa1 and second amplified signal Sa2, and generates a third amplified signal Sa3 and outputs the third amplified signal Sa3 to other circuits through the output terminal OUT.

If Sa 1=va+na×sa, sa 2=va+nb×sa, sa 3= (Na-Nb) ×sa, it is apparent that the first input signal Sa is amplified (Na-Nb) times by the small signal processing circuit.

If Sa 1=va+na×sa, sa 2=va-nb×sa, sa 3= (na+nb) ×sa, it is apparent that the first input signal Sa is amplified (na+nb) times by the small signal processing circuit.

If Sa 1=va-na×sa, sa 2=va+nb×sa, sa 3= (-Na-Nb) ×sa, it is apparent that the first input signal Sa is amplified by (-Na-Nb) times by the small signal processing circuit.

If Sa 1=va-na×sa, sa 2=va-nb×sa, sa 3= (Nb-Na) ×sa, it is apparent that the first input signal Sa is amplified (Nb-Na) by the small signal processing circuit.

As described above, the third amplified signal Sa3 output by the third amplifying module 103 is associated with only the first input signal Sa. The third amplifying module 103 may perform differential amplifying processing, so as to demodulate the first bias signal Va, and also simultaneously amplify the first input signal Sa without increasing noise, thereby implementing multiple increases in the signal-to-noise ratio of the small signal processing circuit.

In the invention, a first amplifying module processes a first input signal and a first bias signal to provide a first amplifying signal to a third amplifying module; the second amplifying module processes the first input signal and the first bias signal to provide a second amplified signal to the third amplifying module; the third amplification module processes the first amplified signal, the second amplified signal, and the first bias signal to generate a third amplified signal, the third amplified signal being associated with the first input signal and the third amplified signal being uncorrelated with the first bias signal. In the invention, any one of the first amplifying module and the second amplifying module amplifies the first input signal to modulate the first input signal on a high level, thereby reducing the interference of noise signals generated by the chip of the module on the first input signal, and reducing the effective signal-to-noise ratio without inserting noise generated by the chip of the module into a circuit; in addition, the first input signal is processed in parallel through the first amplifying module and the second amplifying module, so that the requirement of the small signal processing circuit on the chip bandwidth can be reduced, the selectable range of the chip performance of the small signal processing circuit is widened, the design success probability of the small signal processing circuit can be improved, and the design period is reduced; in addition, the third amplified signal output by the third amplifying module is only associated with the first input signal, so that the amplification of the first input signal is realized under the condition of not increasing noise, the signal to noise ratio of the small signal processing circuit is improved multiple times, the signal to noise ratio requirement required by a user is met, and the high signal to noise ratio is realized.

The optional small signal processing circuit further comprises a primary amplifying module; the input end of the primary amplifying module receives a first input signal, and the output end of the primary amplifying module is respectively connected with the first input end of the first amplifying module and the first input end of the second amplifying module.

Fig. 2 is a schematic diagram of another small signal processing circuit according to an embodiment of the present invention, and as shown in fig. 2, the small signal processing circuit further includes a primary amplifying module 105; the input end of the primary amplifying module 105 receives the first input signal Sa, the primary amplifying module 105 amplifies the first input signal Sa and outputs the first input signal Sa, and the signal output by the primary amplifying module 105 is a primary amplified signal Sa'. The output end of the primary amplifying module 105 is connected to the first input end of the first amplifying module 101, so that the electrical signal received by the first input end of the first amplifying module 101 is a signal Sa' obtained by performing primary amplifying processing on the first input signal Sa by the primary amplifying module 105. The output end of the primary amplifying module 105 is connected to the first input end of the second amplifying module 102, and the electrical signal received by the first input end of the second amplifying module 102 is a signal Sa' obtained by performing primary amplifying processing on the first input signal Sa by the primary amplifying module 105.

As described above, the small signal processing circuit shown in fig. 2 includes a three-stage amplifying circuit. The first-stage amplification circuit includes a primary amplification module 105, and performs a first-stage amplification process on an initial first input signal Sa. The second-stage amplification circuit includes a first amplification module 101 and a second amplification module 102, and performs second-stage amplification processing on an output signal Sa' of the first-stage amplification circuit. The third-stage amplifying circuit includes a third amplifying module 103, and performs third-stage amplifying processing on the output signal of the second-stage amplifying circuit.

Whereas the small signal processing circuit shown in fig. 1 comprises a two-stage amplifying circuit. The first-stage amplifying circuit includes a first amplifying module 101 and a second amplifying module 102, and directly performs a first-stage amplifying process on an initial first input signal Sa. The second-stage amplifying circuit includes a third amplifying module 103, and performs second-stage amplifying processing on the output signal of the first-stage amplifying circuit.

The optional primary amplification module includes a low noise power amplifier. The low noise power (LNA) amplifier has low noise, which has less interference to the first input signal Sa and therefore does not reduce the effective signal-to-noise ratio of the small signal processing circuit.

In comparison with fig. 1, fig. 2 adds a primary amplifying module 105, where the primary amplifying module 105 performs a primary amplifying process on the initial first input signal Sa and then transmits the first input signal Sa to the first amplifying module 101 and the second amplifying module 102.

Based on the small signal processing circuit shown in fig. 2, the small signal to noise ratio is improved by multiple times, so that the signal to noise ratio requirement required by a user is met, and the high signal to noise ratio is realized. The primary amplifying module has low noise, and the low noise has small interference to the first input signal Sa, so that the effective signal-to-noise ratio of the small signal processing circuit is not reduced, the requirement condition of the LNA operational amplifier model of the selectable primary amplifying module is widened, and the requirement condition of the total noise performance parameter of the selectable LNA operational amplifier model can be widened. In addition, the second-stage amplifying circuit amplifies and lifts the first input signal Sa after the first-stage amplifying, so that the noise of the chip in the second-stage amplifying circuit has small interference to the circuit, and therefore the noise of the second-stage amplifying circuit is inserted into the circuit without greatly reducing the effective signal to noise ratio. Under the condition of the same-level chip performance, the small signal processing circuit of the embodiment can effectively improve the minimum resolution of the system, the small signal to noise ratio requirement of the small signal processing circuit is not limited by the noise sizes of the primary amplifying module, the first amplifying module and the second amplifying module, the design difficulty and the cost of the small signal processing circuit are reduced, and the design success probability of the small signal processing circuit is improved.

Fig. 3 is a schematic diagram of yet another small signal processing circuit provided in an embodiment of the present invention, and as shown in fig. 3, the optional first amplifying module 101 includes an in-phase amplifier 201; the non-inverting input (+) of the IN-phase amplifier 201 receives the first input signal Sa, the inverting input (-) of the IN-phase amplifier 201 is connected to the bias block 104, and the output of the IN-phase amplifier 201 is connected to the first input IN1 of the third amplifier block 103. The optional first amplifying module 101 further includes a first resistor R11, a second resistor R12, and a third resistor R13; the non-inverting input terminal (+) of the IN-phase amplifier 201 receives the first input signal Sa through the first resistor R11, the inverting input terminal (-) of the IN-phase amplifier 201 is connected to the bias module 104 through the second resistor R12, and the output terminal of the IN-phase amplifier 201 is connected to the first input terminal IN1 of the third amplifier module 103 through the third resistor R13.

In this embodiment, the non-inverting input (+) of the non-inverting amplifier 201 receives the first input signal Sa through the first resistor R11, and the non-inverting input (+) of the non-inverting amplifier 201 is also grounded GND through the resistor R14. The inverting input terminal (-) of the in-phase amplifier 201 is connected to the bias module 104 through the second resistor R12 to receive the first bias signal Va, the inverting input terminal (-) of the in-phase amplifier 201 is further connected to the first power supply terminal VCC1 through the resistor R15 and the resistor R16, and the inverting input terminal (-) of the in-phase amplifier 201 is further connected to the output terminal of the in-phase amplifier 201 through the resistor R15, wherein the first power supply terminal VCC1 provides a positive power supply signal, for example, the first power supply terminal VCC1 provides a +5v voltage signal. The output terminal of the IN-phase amplifier 201 is connected to the first input terminal IN1 of the third amplifying module 103 via a third resistor R13.

It will be appreciated that the port configuration of the in-phase amplifier 201 shown in fig. 3 is only a partial port of the in-phase amplifier, and that in practice the in-phase amplifier will have other ports, only ports of the circuit that are relevant for signal transmission being shown.

Referring to fig. 3, the first input of the optional second amplification module 102 is common to the second input of the second amplification module 102; the second amplification module 102 includes an inverting amplifier 202; the inverting input terminal (-) of the inverting amplifier 202 receives the first input signal Sa, the inverting input terminal (-) of the inverting amplifier 202 is further connected to the bias block 104, the non-inverting input terminal (+) of the inverting amplifier 202 is grounded, and the output terminal of the inverting amplifier 202 is connected to the second input terminal IN2 of the third amplifying block 103. The optional second amplifying module 102 further includes a fourth resistor R21, a fifth resistor R22, and a sixth resistor R23; the inverting input terminal (-) of the inverting amplifier 202 receives the first input signal Sa through the fourth resistor R21, the inverting input terminal (-) of the inverting amplifier 202 is further connected to the biasing module 104 through the fifth resistor R22, and the output terminal of the inverting amplifier 202 is connected to the second input terminal IN3 of the third amplifying module 103 through the sixth resistor R23.

In this embodiment, the first input terminal of the second amplifying module 102 and the second input terminal of the second amplifying module 102 are the same port, so the first input terminal of the second amplifying module 102 receives the first input signal Sa and the first bias signal Va provided by the bias module 104 at the same time.

The second amplification module 102 includes an inverting amplifier 202. The non-inverting input (+) of the inverting amplifier 202 is grounded GND through the resistor R24. The inverting input terminal (-) of the inverting amplifier 202 receives the first input signal Sa through the fourth resistor R21, the inverting input terminal (-) of the inverting amplifier 202 is further connected to the bias module 104 through the fifth resistor R22 to receive the first bias signal Va, the inverting input terminal (-) of the inverting amplifier 202 is further connected to the first power supply terminal VCC1 through the resistor R25 and the resistor R26, and the inverting input terminal (-) of the inverting amplifier 202 is further connected to the output terminal of the inverting amplifier 202 through the resistor R25, wherein the first power supply terminal VCC1 provides a positive power supply signal, for example, the first power supply terminal VCC1 provides a +5v voltage signal. The output terminal of the inverting amplifier 202 is connected to the second input terminal IN3 of the third amplifying module 103 through a sixth resistor R23.

It will be appreciated that the port configuration of the inverting amplifier 202 shown in fig. 3 is only a partial port of the inverting amplifier, and that in practice the inverting amplifier will have other ports, only ports of the circuit that are relevant to signal transmission being shown. The in-phase amplifier 201 and the inverting amplifier 202 in combination can realize a voltage bias modulation function.

Referring to fig. 3, the optional third amplification module 103 includes a differential amplifier 203; the positive input (+IN) of the differential amplifier 203 is connected to the output of the first amplification block 101, the negative input (-IN) of the differential amplifier 203 is connected to the output of the second amplification block 102, and the Reference (REF) of the differential amplifier 203 is connected to the bias block 104.

In this embodiment, the differential amplifier 203 may be a differential amplifier based on a fully differential input. The positive input (+IN) of the differential amplifier 203 is connected to the output of the IN-phase amplifier 201 via a resistor R13, the negative input (-IN) of the differential amplifier 203 is connected to the output of the inverting amplifier 202 via a resistor R23, and the Reference (REF) of the differential amplifier 203 is connected to the bias block 104 to receive the first bias signal Va. It should be noted that, in other embodiments, the optional differential amplifier may be a differential amplifier based on a non-fully differential input; at this time, the first bias signal provided by the bias module is transmitted to the circuit structure for controlling the differential amplifier, and is not required to be directly transmitted to the differential amplifier.

The differential amplifier 203 further has a SENSE terminal (SENSE), and the SENSE terminal (SENSE) of the differential amplifier 203 is connected to the positive input (+in) of the differential amplifier 203 through a resistor R31. The differential amplifier 203 also has a negative power supply terminal (V-) and the negative power supply terminal (V-) of the differential amplifier 203 receives a negative voltage signal VSS1, the optional negative voltage signal VSS1 providing a-5V voltage signal. The differential amplifier 203 also has a positive power supply terminal (v+), the positive power supply terminal (v+) of the differential amplifier 203 receives a positive voltage signal VCC1, and the optional positive voltage signal VCC1 provides a +5v voltage signal. The output terminal (OUT) of the differential amplifier 203 outputs an electric signal through the resistor R32.

It will be appreciated that the port structure of the differential amplifier 203 shown in fig. 3 is only a partial port of the differential amplifier, and that in practice the differential amplifier will have other ports, only ports of the circuit that are relevant for signal transmission being shown. The differential amplifier 203 performs the function of multiplying the useful small signal by the demodulation bias voltage.

Referring to fig. 3, the optional bias module 104 includes a microcontroller 204 and an analog-to-digital converter 205; the control end of the analog-to-digital converter 205 is connected with the microcontroller 204, the output end of the analog-to-digital converter 205 is respectively connected with the first amplifying module 101, the second amplifying module 102 and the third amplifying module 103, and the analog-to-digital converter 205 is used for generating a first bias signal Va according to the instruction of the microcontroller 204. An ADC is an acronym for analog-to-digital converter.

In this embodiment, bias module 104 includes a microcontroller 204 and an analog-to-digital converter 205. The control end of the analog-to-digital converter 205 is connected with the microcontroller 204, the microcontroller 204 issues a control command to the analog-to-digital converter 205, and the analog-to-digital converter 205 generates a corresponding first bias signal Va according to the control command of the microcontroller 204, where the first bias signal Va may be a digital signal.

For example, the bias signal required by the small signal processing circuit is (+5v), the microcontroller 204 issues a control command to the analog-to-digital converter 205, where the control command carries information of "providing the (+5v) bias signal", and the analog-to-digital converter 205 generates a corresponding first bias signal Va according to the control command of the microcontroller 204, where the first bias signal Va is (+5v).

Or the bias signal required by the small signal processing circuit is (-1.4V), the microcontroller 204 issues a control command to the analog-to-digital converter 205, where the control command carries information of providing the (-1.4V) bias signal, and the analog-to-digital converter 205 generates a corresponding first bias signal Va according to the control command of the microcontroller 204, where the first bias signal Va is (-1.4V).

The micro-controller 204 commands the analog-to-digital converter 205 to generate a bias signal of a corresponding magnitude when the bias signal required by the small signal processing circuit changes.

The amplification factor of the optional in-phase amplifier 201 is Na, the first input signal is Sa, the first bias signal is Va, and the output signal of the in-phase amplifier 201 is Sa1, and then sa1=va+na×sa. The amplification factor of the optional inverting amplifier 202 is Nb, the first input signal is Sa, the first bias signal is Va, and the output signal of the inverting amplifier 202 is Sa2, then sa2=va-Nb.

The output signal of the differential amplifier 203 is Sa3, and therefore, sa 3= (na+nb) ×sa, it is apparent that the first input signal Sa is amplified by (na+nb) times by the small signal processing circuit.

The amplification factor of the optional first amplification module is equal to the amplification factor of the second amplification module. As shown in fig. 3, when the amplification factor of the optional in-phase amplifier 201 and the amplification factor of the inverting amplifier 202 are both Na, the first input signal is Sa, the first bias signal is Va, and the output signal Sa3 of the differential amplifier 203 is sa3=2×na×sa, it is obvious that the first input signal Sa is amplified by 2×na times by the small signal processing circuit.

The small signal processing circuit provided in the embodiment can be used for processing the analog small signal, for example, the small signal processing circuit is applied to the front end analog small signal of the non-contact defect detector, can realize the integral improvement of the signal to noise ratio of the small signal, can obtain the small signal meeting the signal to noise ratio requirement without configuring a filter, and is beneficial to realizing high signal to noise ratio.

It will be appreciated that the small signal processing circuit is only a major part of the circuit structure as described above, and if the small signal processing circuit is applied in an apparatus or a device, other corresponding components or structures may need to be configured to the small signal processing circuit, which is not specifically described in the present invention. In addition, in the circuit structure of the small signal processing circuit, the specific parameters of each component are not limited, and relevant practitioners can reasonably select proper components according to the requirements of products, which is not described in detail in the invention.

The small signal processing circuit provided in this embodiment can realize the small signal to noise ratio requirement in the ideal, and the low noise of the primary amplifying module, the noise of the first amplifying module and the noise of the second amplifying module do not seriously damage the effective signal to noise ratio, so the small signal processing circuit is not limited by the low noise of the primary amplifying module, the noise of the first amplifying module and the noise of the second amplifying module. Based on this, when related practitioner designs the circuit, the selectable range of the primary amplifying module, the selectable range of the first amplifying module and the selectable range of the second amplifying module are widened, the selectable range of the primary amplifying module is not limited to be high-performance operational amplifier, and the selectable ranges of the first amplifying module and the second amplifying module are not limited to be high-amplifying gain, so that the difficulty of chip type selection and the design cost in the small-signal processing circuit are reduced.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims (10)

1. A small signal processing circuit, comprising: the device comprises a bias module, a first amplifying module, a second amplifying module and a third amplifying module;

the bias module is used for providing a first bias signal;

A first input end of the first amplifying module receives a first input signal, a second input end of the first amplifying module is connected with the biasing module, and an output end of the first amplifying module provides a first amplifying signal for a first input end of the third amplifying module;

The first input end of the second amplifying module receives the first input signal, the second input end of the second amplifying module is connected with the biasing module, and the output end of the second amplifying module provides a second amplifying signal for the second input end of the third amplifying module;

the third input end of the third amplifying module is connected with the bias module, and the third amplifying module is used for processing the first amplifying signal, the second amplifying signal and the first bias signal so as to output a third amplifying signal associated with the first input signal, and the third amplifying signal is not associated with the first bias signal.

2. The small signal processing circuit as in claim 1, wherein the first amplification module comprises an in-phase amplifier;

The non-inverting input end of the in-phase amplifier receives the first input signal, the inverting input end of the in-phase amplifier is connected with the biasing module, and the output end of the in-phase amplifier is connected with the first input end of the third amplifying module.

3. The small signal processing circuit as in claim 2, wherein the first amplification module further comprises a first resistor, a second resistor, and a third resistor;

The non-inverting input end of the in-phase amplifier receives the first input signal through the first resistor, the inverting input end of the in-phase amplifier is connected with the biasing module through the second resistor, and the output end of the in-phase amplifier is connected with the first input end of the third amplifying module through the third resistor.

4. The small signal processing circuit as in claim 1, wherein the first input of the second amplification module and the second input of the second amplification module are common;

The second amplification module comprises an inverting amplifier;

The inverting input end of the inverting amplifier receives the first input signal, the inverting input end of the inverting amplifier is also connected with the biasing module, the non-inverting input end of the inverting amplifier is grounded, and the output end of the inverting amplifier is connected with the second input end of the third amplifying module.

5. The small signal processing circuit as in claim 4, wherein the second amplification module further comprises a fourth resistor, a fifth resistor, and a sixth resistor;

The inverting input end of the inverting amplifier receives the first input signal through the fourth resistor, the inverting input end of the inverting amplifier is also connected with the biasing module through the fifth resistor, and the output end of the inverting amplifier is connected with the second input end of the third amplifying module through the sixth resistor.

6. The small signal processing circuit as recited in claim 1, wherein the amplification factor of the first amplification module is equal to the amplification factor of the second amplification module.

7. The small signal processing circuit as in claim 1, wherein the third amplification module comprises a differential amplifier;

The positive input end of the differential amplifier is connected with the output end of the first amplifying module, the negative input end of the differential amplifier is connected with the output end of the second amplifying module, and the reference end of the differential amplifier is connected with the biasing module.

8. The small signal processing circuit as in claim 1, wherein the bias module comprises a microcontroller and an analog-to-digital converter;

the control end of the analog-to-digital converter is connected with the microcontroller, the output end of the analog-to-digital converter is respectively connected with the first amplifying module, the second amplifying module and the third amplifying module, and the analog-to-digital converter is used for generating the first bias signal according to the instruction of the microcontroller.

9. The small signal processing circuit as in claim 1, further comprising a primary amplification module;

the input end of the primary amplifying module receives the first input signal, and the output end of the primary amplifying module is respectively connected with the first input end of the first amplifying module and the first input end of the second amplifying module.

10. The small signal processing circuit as in claim 9, wherein the primary amplification module comprises a low noise power amplifier.