CN118711525B

CN118711525B - Display panel

Info

Publication number: CN118711525B
Application number: CN202411201624.XA
Authority: CN
Inventors: 朱亚威
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Filing date: 2024-08-29
Publication date: 2024-11-15
Anticipated expiration: 2044-08-29

Abstract

The application provides a display panel, which comprises a plurality of sub-pixel groups, wherein each sub-pixel group comprises two sub-pixel units, a light emitting device and a pixel driving circuit connected with the light emitting device are arranged in each sub-pixel unit, each pixel driving circuit comprises a switch transistor, a driving transistor, a compensation transistor and a first reset transistor, each compensation transistor comprises a compensation active part, each first reset transistor comprises a first reset active part, the extending direction of at least one of the compensation active part and the first reset active part is the same as the extending direction of a first scanning signal line, the occupied area of the pixel driving circuit in the extending direction of the first scanning signal line can be reduced, the number of pixels in per inch can be increased, the particle feeling of a display picture can be reduced, and the resolution of the display panel is improved.

Description

Display panel

Technical Field

The application relates to the technical field of display, in particular to a display panel.

Background

An Organic Light-Emitting Diode (OLED) display technology is a novel display technology, and is gradually paid attention to by unique advantages of low power consumption, high saturation, fast response time, wide viewing angle and the like, and takes a place in the technical field of panel display.

At present, in order to improve the driving performance of the organic light emitting diode display panel, a low-temperature polycrystalline oxide (Low Temperature Polysilicon Oxide, LTPO) back plate technology is adopted, but the pixel driving circuit occupies a larger area, so that the number of pixels in per inch is smaller, the resolution of a display picture is lower, and the granular feel is obvious.

Disclosure of Invention

The embodiment of the application provides a display panel, which can improve the resolution of the display panel and reduce the granular feel of a display picture.

An embodiment of the present application provides a display panel, including a plurality of sub-pixel groups, each of the sub-pixel groups including two sub-pixel units, each of the sub-pixel units having a light emitting device and a pixel driving circuit connected to the light emitting device, the pixel driving circuit including:

A switching transistor, a first electrode of which is connected to the data signal line, a second electrode of which is connected to the first node, and a switching gate of which is connected to the first scan signal line;

A driving transistor, a first electrode of the driving transistor is connected to the first node, a second electrode of the driving transistor is connected to the second node, and a driving gate of the driving transistor is connected to the third node;

A compensation transistor, a first electrode of the compensation transistor being connected to the third node, a second electrode of the compensation transistor being connected to the second node;

a first reset transistor having a first electrode connected to a first reset signal line and a second electrode connected to the third node;

The first reset transistor includes a first reset active portion, and at least one of the compensation active portion and the first reset active portion extends in the same direction as the first scanning signal line.

According to an embodiment of the present application, the display panel includes:

A substrate;

a first active layer disposed on one side of the substrate, the material of the first active layer including a silicon semiconductor material;

the first grid electrode layer is arranged on one side of the first active layer, which is far away from the substrate;

the second grid electrode layer is arranged on one side of the first grid electrode layer, which is far away from the first active layer;

The second active layer is arranged on one side of the second grid electrode layer far away from the first grid electrode layer, and the material of the second active layer comprises a metal oxide semiconductor material;

the first source-drain electrode layer is arranged on one side of the second active layer far away from the second grid electrode layer;

Wherein the compensation active portion and the first reset active portion are disposed in the second active layer.

According to an embodiment of the present application, the first scan signal line is disposed on the first gate layer, the second gate layer includes a second scan signal line and a third scan signal line, the compensation gate of the compensation transistor is connected to the second scan signal line, and the first reset gate of the first reset transistor is connected to the third scan signal line;

The front projection of the compensation active part on the substrate and the front projection of the first reset active part on the substrate are arranged on two sides of the front projection of the first scanning signal line on the substrate, the front projection of the compensation active part on the substrate and the front projection of the second scanning signal line on the substrate are overlapped, and the front projection of the first reset active part on the substrate and the front projection of the third scanning signal line on the substrate are overlapped.

According to an embodiment of the present application, the first source/drain layer includes a first connection element, and the compensation active portion is connected to the first reset active portion through the first connection element.

According to an embodiment of the present application, the second scanning signal line includes a first sub-scanning line segment and a second sub-scanning line segment connected to the first sub-scanning line segment, and the third scanning signal line includes a third sub-scanning line segment and a fourth sub-scanning line segment connected to the third sub-scanning line segment;

The orthographic projection of the compensation active part on the second scanning signal line is positioned in the second sub-scanning line segment, and the width of the first sub-scanning line segment is smaller than that of the second sub-scanning line segment; the orthographic projection of the first reset active part on the third scanning signal line is positioned in the fourth sub-scanning line segment, and the width of the third sub-scanning line segment is smaller than that of the fourth sub-scanning line segment.

According to an embodiment of the present application, in at least one of the sub-pixel groups, the compensation active portion in one of the sub-pixel units is disconnected from the compensation active portion in the other of the sub-pixel units, and the first reset active portion in one of the sub-pixel units is continuously arranged with the first reset active portion in the other of the sub-pixel units.

According to an embodiment of the present application, the pixel driving circuit includes a boost capacitor, where the boost capacitor includes a first boost plate and a second boost plate, the first boost plate is connected to the first scan signal line, and the second boost plate is connected to the third node;

the first boosting polar plate is arranged on the first grid electrode layer, the second boosting polar plate is arranged on the second grid electrode layer, and the first electrode of the first reset transistor is connected with the second boosting polar plate through the first connecting piece.

According to an embodiment of the present application, the pixel driving circuit further includes a second reset transistor, the first source-drain layer further includes a second reset signal line, a first electrode of the second reset transistor is connected to the second reset signal line, a second electrode of the second reset transistor is connected to a fourth node, and a second reset gate of the second reset transistor is connected to a fourth scan signal line;

the second reset signal line comprises a first sub reset line segment, a second sub reset line segment and a third sub reset line segment, the second sub reset line segment is connected between the first sub reset line segment and the third sub reset line segment, the extending directions of the first sub reset line segment and the third sub reset line segment are the same as the extending directions of the first scanning signal line, the extending directions of the second sub reset line segment are the same as the extending directions of the data signal line, the orthographic projection of the first sub reset line segment on the substrate is arranged between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the second scanning signal line on the substrate, the orthographic projection of the second sub reset line segment on the substrate is arranged between the orthographic projection of the second reset active part of the second reset transistor on the substrate and the orthographic projection of the first reset active part on the substrate, and the orthographic projection of the third sub reset line segment on the substrate is arranged on the orthographic projection of the first reset signal line on one side of the orthographic projection of the second reset signal line on the substrate.

According to an embodiment of the present application, the pixel driving circuit further includes:

A first light emitting control transistor, a first electrode of which is connected to a direct-current high-voltage power supply signal line, a second electrode of which is connected to the first node, and a first light emitting control gate of which is connected to a light emitting control signal line;

a second light emission control transistor, a first electrode of the second light emission control transistor is connected to the second node, a second electrode of the second light emission control transistor is connected to the fourth node, and a second light emission control gate of the second light emission control transistor is connected to the light emission control signal line;

And the first storage polar plate of the storage capacitor is connected with the direct-current high-voltage power supply signal line, and the second storage polar plate of the storage capacitor is connected with the third node.

According to an embodiment of the present application, two sub-pixel units in the same sub-pixel group are symmetrically disposed.

The embodiment of the application has the beneficial effects that: the embodiment of the application provides a display panel, which comprises a plurality of sub-pixel groups, wherein each sub-pixel group comprises two sub-pixel units, a light emitting device and a pixel driving circuit connected with the light emitting device are arranged in each sub-pixel unit, each pixel driving circuit comprises a switch transistor, a driving transistor, a compensation transistor and a first reset transistor, each compensation transistor comprises a compensation active part, each first reset transistor comprises a first reset active part, and the extending direction of at least one of the compensation active part and the first reset active part is the same as the extending direction of a first scanning signal line, so that the occupied area of the pixel driving circuit in the extending direction of the first scanning signal line can be reduced, the number of pixels in per inch can be increased, the granular sense of a display picture can be reduced, and the resolution of the display panel is improved.

Drawings

Fig. 1 is a circuit diagram of a pixel driving circuit in a display panel according to an embodiment of the present application;

Fig. 2 is a schematic diagram of a lamination of film layers of a display panel according to an embodiment of the application;

fig. 3 is a schematic diagram of a film structure of a display panel according to an embodiment of the application;

FIG. 4 is a film layer diagram of a light shielding layer in a display panel according to the present application;

FIG. 5 is a film layer diagram of a first active layer in the display panel of the present application;

FIG. 6 is a film layer diagram of a light shielding layer and a first active layer in a display panel according to the present application;

FIG. 7 is a schematic diagram of a first gate layer of the display panel of the present application;

FIG. 8 is a schematic diagram of a light shielding layer, a first active layer and a first gate layer in a display panel according to the present application;

FIG. 9 is a film layer diagram of a second gate layer in the display panel of the present application;

FIG. 10 is a schematic diagram showing a light shielding layer, a first active layer, a first gate layer and a second gate layer in a display panel according to the present application;

FIG. 11 is a film layer diagram of a first active layer in a display panel according to the present application;

FIG. 12 is a schematic diagram showing a light shielding layer, a first active layer, a first gate layer, a second gate layer and a second active layer in a display panel according to the present application;

FIG. 13 is a film layer diagram of a first source/drain layer in a display panel according to the present application;

FIG. 14 is a schematic diagram showing a light shielding layer, a first active layer, a first gate layer, a second active layer and a first source/drain layer in a display panel according to the present application;

Fig. 15 is a timing diagram of a pixel driving circuit of a display panel according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of a display device according to an embodiment of the application.

Detailed Description

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the application may be practiced. The directional terms mentioned in the present application, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., are only referring to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the application and is not limiting of the application. In the drawings, like elements are designated by like reference numerals.

The application will be further described with reference to the accompanying drawings and specific examples.

An embodiment of the present application provides a display panel, and fig. 1 and fig. 2 are combined, where fig. 1 is a circuit diagram of a pixel driving circuit in the display panel provided by the embodiment of the present application, and fig. 2 is a schematic lamination diagram of each film layer of the display panel provided by the embodiment of the present application, and the display panel includes a plurality of sub-pixel groups 2, each sub-pixel group 2 includes two sub-pixel units 20, and a light emitting device 21 and a pixel driving circuit 22 connected to the light emitting device 21 are disposed in each sub-pixel unit.

In the embodiment of the present application, the pixel driving circuit 22 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3 and a first reset transistor T4, wherein a first electrode of the switching transistor T2 is connected to the Data signal line Data, a second electrode of the switching transistor T2 is connected to the first node a, and a switching gate of the switching transistor T2 is connected to the first scan signal line Pscan; a first electrode of the driving transistor T1 is connected to the first node A, a second electrode of the driving transistor T1 is connected to the second node B, and a driving grid electrode of the driving transistor T1 is connected to the third node Q; the first electrode of the compensation transistor T3 is connected to the third node Q, and the second electrode of the compensation transistor T3 is connected to the second node B; a first electrode of the first reset transistor T4 is connected to the first reset signal line Vi-Gate, and a second electrode of the first reset transistor T4 is connected to the third node Q.

In an embodiment of the present application, the compensation transistor T3 includes a compensation active portion, the first reset transistor T4 includes a first reset active portion, and an extension direction of at least one of the compensation active portion and the first reset active portion is the same as an extension direction of the first scan signal line Pscan.

According to the application, the extending direction of at least one of the compensation active part and the first reset active part is set to be the same as the extending direction of the first scanning signal line Pscan, so that the occupied area of the pixel unit in the extending direction of the first scanning signal line is reduced, the number of pixels in per inch can be increased, the granular sense of a display picture can be reduced, and the resolution of the display panel is improved.

In some embodiments, the light emitting device 21 may be any one of a light emitting diode, an organic light emitting diode, a mini light emitting diode, a micro light emitting diode chip, and other light sources.

In some embodiments, as shown in fig. 1, the pixel driving circuit 22 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first reset transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a second reset transistor T7, a storage capacitor Cst, and a boost capacitor Cboost.

As shown in fig. 1, a first electrode of the switching transistor T2 is connected to the Data signal line Data, a second electrode of the switching transistor T2 is connected to the first node a, and a switching gate of the switching transistor T2 is connected to the first scan signal line Pscan; a first electrode of the driving transistor T1 is connected to the first node A, a second electrode of the driving transistor T1 is connected to the second node B, and a driving grid electrode of the driving transistor T1 is connected to the third node Q; the first electrode of the compensation transistor T3 is connected to the third node Q, the second electrode of the compensation transistor T3 is connected to the second node B, and the compensation gate of the compensation transistor T3 is connected to the second scanning signal line Nscan; a first electrode of the first reset transistor T4 is connected to the first reset signal line Vi-Gate, a second electrode of the first reset transistor T4 is connected to the third node Q, and a first reset Gate of the first reset transistor T4 is connected to the second scan signal line Nscan; a first electrode of the first light emitting control transistor T5 is connected to the direct-current high-voltage power supply signal line VDD, a second electrode of the first light emitting control transistor T5 is connected to the first node a, and a first light emitting control gate of the first light emitting control transistor T5 is connected to the light emitting control signal line EM; the first electrode of the second light-emitting control transistor T6 is connected to the second node B, the second electrode of the second light-emitting control transistor T6 is connected to the fourth node C, and the second light-emitting control gate of the second light-emitting control transistor T6 is connected to the light-emitting control signal line EM; the first electrode of the second reset transistor T7 is connected to the second reset signal line Vi-Ano, the second electrode of the second reset transistor T7 is connected to the fourth node C, and the second reset gate of the second reset transistor T7 is connected to the fourth scan signal line Pscan; the first storage pole plate of the storage capacitor Cst is connected to a direct-current high-voltage power signal line VDD, and the second storage pole plate of the storage capacitor Cst is connected to a third node Q; a first boost plate of the boost capacitor Cboost is connected to the first scan signal line Pscan, and a second boost plate of the boost capacitor Cboost is connected to the third node Q; an anode of the light emitting device 21 is connected to the fourth node C, and a cathode of the light emitting device 21 is connected to the dc power supply signal line VSS.

In the embodiment of the present application, the dc high-voltage power supply signal line VDD is used to supply a constant voltage high-level signal to the pixel driving circuit 22, and the dc low-voltage power supply signal line VSS is used to supply a constant voltage low-level signal to the pixel driving circuit 22.

In the embodiment of the present application, the driving transistor T1, the switching transistor T2, the first light emitting control transistor T5, the second light emitting control transistor T6, and the second reset transistor T7 may be one of a P-type transistor and an N-type transistor, and the compensation transistor T3 and the first reset transistor T4 may be the other of a P-type transistor or an N-type transistor. The present application is described by taking the P-type transistors as the driving transistor T1, the switching transistor T2, the first light emitting control transistor T5, the second light emitting control transistor T6 and the second reset transistor T7, and the N-type transistors as the compensation transistor T3 and the first reset transistor T4.

It should be noted that, in the embodiment of the present application, the first electrode of the transistor is one of the source and the drain, the second electrode is the other of the source and the drain, and the first electrode and the second electrode of each transistor may be the same or different.

In the following embodiments, the angle between the first direction X and the second direction Y is greater than 0 ° and less than or equal to 90 °. For example, the first direction X is a lateral direction and the second direction Y is a longitudinal direction.

The film layer structure of the pixel driving circuit of the present application will be described below with respect to the structure shown in fig. 1.

In some embodiments, the display panel includes a substrate 1, a first active layer 204, a first gate layer 206, a second gate layer 208, a second active layer 210, and a first source drain layer 212, where the first active layer 204 is disposed on a side of the substrate 1, the first gate layer 206 is disposed on a side of the first active layer 204 away from the substrate 1, the second gate layer 208 is disposed on a side of the first gate layer 206 away from the first active layer 204, and the second active layer 210 is disposed on a side of the second gate layer 208 away from the first gate layer 206.

Referring to fig. 3, fig. 3 is a schematic diagram of a film structure of a display panel according to an embodiment of the application, wherein the display panel includes a substrate 1, a light shielding layer 201 disposed on the substrate 1, a barrier layer 202 disposed on the light shielding layer 201, a buffer layer 203 disposed on the barrier layer 202, a first active layer 204 disposed on the buffer layer 203, a first gate insulating layer 205 disposed on the first active layer 204, a first gate layer 206 disposed on the first gate insulating layer 205, a second gate insulating layer 207 disposed on the first gate layer 206, a second gate layer 208 disposed on the second gate insulating layer 207, a first interlayer dielectric layer 209 disposed on the second gate layer 208, a second active layer 210 disposed on the first interlayer dielectric layer 209, a second interlayer dielectric layer 211 disposed on the second active layer 210, a first source drain layer 212 disposed on the first source drain layer 212, a first drain layer 213 disposed on the first planarization layer 213, a second drain layer 214 disposed on the first planarization layer 214, and a second drain layer 214 disposed on the second planarization layer 214.

As shown in fig. 3, a light shielding layer 201 is provided on a substrate 1, the light shielding layer 201 is used for shielding external light from entering a thin film transistor from the bottom, and the material of the light shielding layer 201 may be a black light shielding material or a light-impermeable material, for example, black ink or a metal material.

As shown in fig. 3, the barrier layer 202 is disposed on the light shielding layer 201, the buffer layer 203 is disposed on the barrier layer 202, the barrier layer 202 and the buffer layer 203 are used for isolating the light shielding layer 201 and the upper metal material, and the barrier layer 202 and the buffer layer 203 may have a single-layer structure or a stacked-layer structure formed of at least one of silicon nitride, silicon oxide, and silicon oxynitride.

As shown in fig. 3, the first active layer 204 is disposed on the buffer layer 203, the second active layer 210 is disposed on the first interlayer dielectric layer 209, and materials of the first active layer 204 and the second active layer 210 include a metal oxide semiconductor material or a silicon semiconductor material, where the metal oxide semiconductor material may be indium gallium zinc oxide, and the silicon semiconductor material may be amorphous silicon or low-temperature polysilicon.

In an embodiment of the present application, the material of the first active layer 204 comprises low temperature polysilicon and the material of the second active layer 210 comprises indium gallium zinc oxide.

As shown in fig. 3, the first gate insulating layer 205, the second gate insulating layer 207, the first interlayer dielectric layer 209 and the second interlayer dielectric layer 211 are respectively disposed on the corresponding metal layer or active layer, so that the metal layers or active layers of different layers are separately and insulatively disposed. The first gate insulating layer 205, the second gate insulating layer 207, the first interlayer dielectric layer 209, and the second interlayer dielectric layer 211 may have a single-layer structure or a stacked-layer structure formed of at least one of silicon nitride, silicon oxide, and silicon oxynitride.

As shown in fig. 3, the first gate layer 206, the second gate layer 208, the first source drain layer 212, and the second source drain layer 214 are respectively disposed on corresponding insulating layers or interlayer dielectric layers, and the first gate layer 206, the second gate layer 208, the first source drain layer 212, and the second source drain layer 214 may have a single-layer structure formed of at least one of copper, molybdenum, titanium, aluminum, silver, and the like, or may have a stacked structure formed of at least two metal materials.

As shown in fig. 3, the first planarization layer 213 is disposed on the first source/drain layer 212, the second planarization layer 215 is disposed on the second source/drain layer 214, and the materials of the first planarization layer 213 and the second planarization layer 215 may be at least one inorganic insulating material selected from silicon nitride, silicon oxide and silicon oxynitride, or may be an organic insulating material having leveling property.

As shown in fig. 3, the display panel further includes a light emitting device layer 3, where the light emitting device layer 3 is disposed on a side of the second planar layer 215 away from the second source-drain layer 214, and the light emitting device layer 3 includes an anode layer 301 disposed on the second planar layer 215, a pixel defining layer 302 disposed on the anode layer 301, a spacer layer 303 disposed on the pixel defining layer 302, a light emitting material layer and a cathode layer (not shown in the drawing) disposed on the pixel defining layer 302.

As shown in fig. 4, fig. 4 is a film layer diagram of a light shielding layer in a display panel according to the present application, the light shielding layer 201 includes a light shielding portion 2011, the shape of the light shielding portion 2011 may be square or rectangular, and four vertex angles of the light shielding portion 2011 may be chamfered.

As shown in fig. 5, fig. 5 is a film layer diagram of a first active layer in the display panel of the present application, and the first active layer 204 includes a driving active portion T1A of the driving transistor T1, a switching active portion T2A of the switching transistor T2, a first light emitting control active portion T5A of the first light emitting control transistor T5, a second light emitting control active portion T6A of the second light emitting control transistor T6, and a second reset active portion T7A of the second reset transistor T7.

As shown in fig. 5, the driving active portion T1A, the switching active portion T2A, the first light emission control active portion T5A, and the second light emission control active portion T6A are connected to each other, the second reset active portion T7A is disposed apart from other active portions, and the switching active portion T2A, the first light emission control active portion T5A, the second light emission control active portion T6A, and the second reset active portion T7A are elongated and extend in the second direction Y, and the driving active portion T1A is shaped like a "few" and disposed between the first light emission control active portion T5A and the second light emission control active portion T6A. The first end of the switching active portion TA2, the first end of the driving active portion T1A and the first end of the first light emitting control transistor T5A are all connected to the first connection point P1, the second end of the driving active portion T1A and the first end of the second light emitting control active portion T6A are connected to the second connection point P2, and the second end of the first light emitting control active portion T5A and the second end of the second light emitting control active portion T6A are connected to the third connection point P3.

In this embodiment, the first connection point P1 is the first node a, the second connection point P2 is the second node B, and the third connection point P3 is the point where the anode of the light emitting device 21 is located, that is, the third connection point P3 is the fourth node C.

As shown in fig. 6, fig. 6 is a film layer diagram of a light shielding layer and a first active layer in the display panel of the present application, where the light shielding portion 2011 overlaps with the driving active portion T1A, and the light shielding portion 2011 can shield the ambient light irradiated from the substrate 1 side to the driving active portion T1A of the driving transistor T1, so that the electrical performance of the driving transistor T1 can be prevented from being affected by the ambient light.

As shown in fig. 7, fig. 7 is a stacked view of a first gate layer in the display panel of the present application, the first gate layer 206 includes a driving gate T1G of the driving transistor T1, a switching gate T2G of the switching transistor T2, a first light emitting control gate T5G of the first light emitting control transistor T5, a second light emitting control gate T6G of the second light emitting control transistor T6, a second reset gate T7G of the second reset transistor T7, a first storage plate Cst1 of the storage capacitor Cst, a first boost plate Cboost1 of the boost capacitor Cboost, a first scan signal line Pscan, and a light emitting control signal line EM.

As shown in fig. 7, the first scanning signal line Pscan and the light-emitting control signal line EM extend along the first direction X, the first scanning signal line Pscan and the light-emitting control signal line EM are arranged at intervals along the second direction Y, the driving gate T1G and the first storage electrode Cst1 are arranged between the first scanning signal line Pscan and the light-emitting control signal line EM, the first light-emitting control gate T5G is connected to the second light-emitting control gate T6G and the light-emitting control signal line EM, and the switching gate T2G is connected to the second reset gate T7G and the first scanning signal line Pscan.

In this embodiment, the driving gate T1G may be multiplexed into the first storage plate Cst1 of the storage capacitor Cst, the emission control signal line EM may be directly used as the first emission control gate T5G and the second emission control gate T6G, and the first scan signal line Pscan1 may be directly used as the switching gate T2G and the second reset gate T7G.

As shown in fig. 8, fig. 8 is a laminated view of a light shielding layer, a first active layer and a first gate layer in the display panel of the present application, wherein a driving gate T1G is partially overlapped with a driving active portion T1A, and a portion of the driving gate T1G overlapped with the active portion T1A is a channel of the driving active portion T1A; the switch grid electrode T2G is partially overlapped with the switch active part T2A, and the overlapped part of the switch grid electrode T2G and the switch active part T2A is a channel of the switch active part T2A; the first light-emitting control grid electrode T5G is partially overlapped with the first light-emitting control active part T5A, and the part of the first light-emitting control grid electrode T5G overlapped with the first light-emitting control active part T5A is a channel of the first light-emitting control active part T5A; the second light-emitting control gate T6G is partially overlapped with the second light-emitting control active portion T6A, and the portion of the second light-emitting control gate T6G overlapped with the second light-emitting control active portion T6A is a channel of the second light-emitting control active portion T6A; the second reset gate T7G partially overlaps the second reset active portion T7A, and the portion of the second reset gate T7G overlapping the second reset active portion T7A is a channel of the second reset active portion T7A.

As shown in fig. 9, fig. 9 is a film layer diagram of a second Gate layer in the display panel of the present application, wherein the second Gate layer 208 includes a compensation Gate T3G of the compensation transistor T3, a first reset Gate T4G of the first reset transistor T4, a second storage electrode Cst2 of the storage capacitor Cst, a second boost electrode Cboost2 of the boost capacitor Cboost, a second scan signal line Nscan1, a third scan signal line Nscan2, and a first reset signal Vi-Gate.

As shown in fig. 9, the second scan signal line Nscan, the third scan signal line Nscan2, and the first reset signal Vi-Gate are all disposed along the first direction X, the second scan signal line Nscan, the third scan signal line Nscan, and the first reset signal Vi-Gate are disposed at intervals along the second direction Y, the second boost plate Cboost2 is disposed between the second scan signal line Nscan1 and the third scan signal line Nscan2, the second storage plate Cst2 is disposed on a side of the second scan signal line Nscan away from the second boost plate Cboost2, and the first reset signal line Vi-Gate is disposed on a side of the third scan signal line Nscan away from the second boost plate Cboost 2.

As shown in fig. 9, the second storage electrode Cst2 has a rectangular shape, the second boost electrode Cboost2 has a square shape, and at least part of the top corners of the second storage electrode Cst2 and the second boost electrode Cboost2 may be chamfered.

Referring to fig. 9 and 10, fig. 10 is a laminated diagram of a light shielding layer, a first active layer, a first gate layer and a second gate layer in the display panel of the present application, the area of the second storage electrode Cst2 is larger than that of the first storage electrode Cst1, the orthographic projection of the first storage electrode Cst1 on the second storage electrode Cst2 is located in the second storage electrode Cst2, the second storage electrode Cst2 is provided with a first hole H1, and the first hole H1 exposes a part of the first storage electrode Cst1.

As shown in fig. 9 and 10, the area of the second boost plate Cboost2 is smaller than the area of the first boost plate Cboost1, and the orthographic projection of the second boost plate Cboost2 on the first boost plate Cboost1 is located within the first boost plate Cboost 1.

Referring to fig. 11 and 12, fig. 11 is a film layer diagram of a first active layer in the display panel of the present application, and fig. 12 is a stacked layer diagram of a light shielding layer, a first active layer, a first gate layer, a second gate layer, and a second active layer in the display panel of the present application, wherein the second active layer 210 includes a compensation active portion T3A of a compensation transistor T3 and a first reset active portion T4A of a first reset transistor T4, and at least one of the compensation active portion T3A and the first reset active portion T4A has the same extension direction as the first scan line Pscan 1.

In some embodiments, as shown in fig. 11 and 12, the compensation active portion T3A, the first reset active portion T4A, and the first scan line Pscan a are all disposed along the first direction X, and the compensation active portion T3A and the first reset active portion T4A are spaced apart along the second direction Y and are disposed parallel to each other.

In this embodiment, the compensation active portion T3A and the first reset active portion T4A are disposed to extend along the first direction X, and the compensation active portion T3A and the first reset active portion T4A are disposed to be spaced apart and parallel to each other along the second direction Y, so that the area occupied by the pixel driving circuit in the extending direction of the first scanning signal line can be reduced, the number of pixels possessed per inch can be increased, the graininess of the display screen can be reduced, and the resolution of the display panel can be improved.

In other embodiments, the compensation active portion T3A and the first scan signal line Pscan are disposed to extend along the first direction X, and the first reset active portion T4A is disposed to extend along the second direction Y; or the first reset active portion T4A and the first scanning signal line Pscan a extend along the first direction X, and the compensation active portion T3A extends along the second direction Y, so that the area occupied by the pixel driving circuit in the extending direction of the first scanning signal line can be reduced, the number of pixels in per inch can be increased, the granular sense of the display screen can be reduced, and the resolution of the display panel can be improved.

As shown in fig. 12, the orthographic projection of the compensation active portion T3A on the substrate 1 overlaps with the orthographic projection of the first reset active portion T4A on the substrate 1, which overlaps with the orthographic projection of the third scan signal line Nscan2 on the substrate 1, by the orthographic projection of the compensation active portion T3A on the substrate 1 and the orthographic projection of the second scan signal line Nscan1 on the substrate 1, which are disposed on both sides of the orthographic projection of the first scan signal line Pscan1 on the substrate 1.

In this embodiment, as shown in fig. 12, the second active layer 210 is not subjected to the conductive treatment, the area of the compensation gate T3G is larger than the area of the compensation active portion T3A, the orthographic projection of the compensation active portion T3A on the compensation gate T3G is located in the compensation gate T3G, and the orthographic projection of the first reset active portion T4A on the first reset gate T4G is located in the first reset gate T4G.

As shown in fig. 9 to 12, the second scanning signal line Nscan includes a first sub-scanning line segment Nscan-1 and a second sub-scanning line segment Nscan1-2 connected to the first sub-scanning line segment Nscan-1, the orthographic projection of the compensation active portion T3A on the second scanning signal line Nscan1 is located in the second sub-scanning line segment Nscan1-2, the second sub-scanning line segment Nscan-2 can be multiplexed into a compensation gate T3G, and the width of the first sub-scanning line segment Nscan-1 is smaller than the width of the second sub-scanning line segment Nscan-2, so as to ensure that the orthographic projection of the compensation active portion T3A on the second scanning signal line Nscan1 is located in the second sub-scanning line segment Nscan 1-2.

As shown in connection with fig. 9 to 12, the third scan signal line Nscan includes a third sub-scan line segment Nscan-1 and a fourth sub-scan line segment Nscan2-2 connected to the third sub-scan line segment Nscan-1, the orthographic projection of the first reset active portion T4A on the third scan signal line Nscan2 is located in the fourth sub-scan line segment Nscan-2, the fourth sub-scan line segment Nscan-2 can be multiplexed into the first reset gate T4G, and the width of the third sub-scan line segment Nscan-1 is smaller than the width of the fourth sub-scan line segment Nscan-2, so as to ensure that the orthographic projection of the first reset active portion T4A on the third scan signal line Nscan2 is located in the fourth sub-scan line segment Nscan-2.

In some embodiments, in at least one sub-pixel group 2, the compensation active portion T3A in one sub-pixel unit 20 is disconnected from the compensation active portion T3A in another sub-pixel unit 20, and the first reset active portion T4A in one sub-pixel unit 20 is continuously arranged with the first reset active portion T4A in another sub-pixel unit 20.

As shown in fig. 11 and 12, the area shown by a dashed box in fig. 12 is one sub-pixel unit 20, two adjacent sub-pixel units 20 form one sub-pixel group 2, and the compensation active portions T3A of the compensation transistors T3 in the sub-pixel units 20 located on the left side are disconnected from the compensation active portions T3A of the compensation transistors T3 in the sub-pixel units 20 located on the right side, that is, the compensation active portions T3A of the two sub-pixel units 20 in the same sub-pixel group 2 extend along the first direction X and are disposed at intervals. The first reset active portions T4A of the first reset transistors T4 in the sub-pixel units 20 located on the left are disposed continuously with the first reset active portions T4A of the first reset transistors T4 of the sub-pixel units 20 located adjacent on the right, that is, the first reset active portions T4A of the two sub-pixel units 20 in the same sub-pixel group 2 are both disposed extending in the first direction X and are directly connected to each other.

In some embodiments, in any one sub-pixel group 2, the compensation active portion T3A in one sub-pixel unit 20 is disconnected from the compensation active portion T3A in another sub-pixel unit 20, and the first reset active portion T4A in one sub-pixel unit 20 is continuously arranged with the first reset active portion T4A in another sub-pixel unit 20.

In some embodiments, two sub-pixel elements 20 in the same sub-pixel group 2 are symmetrically arranged.

As shown in fig. 2 to 12, taking the sub-pixel group 2 shown in fig. 2 as an example, the sub-pixel group 2 includes two sub-pixel units 20, and the two sub-pixel units 20 are symmetrically disposed, that is, orthographic projections of patterns of respective film layers in the two sub-pixels 20 on the substrate 1 are symmetrically disposed about a symmetry center line of the two sub-pixels 20.

It should be noted that, fig. 2 to 12 only illustrate one sub-pixel group 2, and the structure of the other sub-pixel groups is the same as that of the sub-pixel group 2 shown in fig. 2, and will not be repeated here.

As shown in fig. 13 and 14, fig. 13 is a film layer diagram of a first source drain layer in the display panel of the present application, fig. 14 is a stacked layer diagram of a light shielding layer, a first active layer, a first gate layer, a second active layer, and a first source drain layer in the display panel of the present application, the first source drain layer 212 includes a first connection member 311, the first connection member 311 is disposed between the second scan signal line Nscan1 and the third scan signal line Nscan, the compensation active portion T3A is connected to the first reset active portion T4A through the first connection member 311, wherein the first connection member 311 is disposed extending along the second direction Y, the first end of the first connection member 311 is connected to the first end of the compensation active portion T3A through the second hole H2, the second end of the first connection member 311 is connected to the first end of the first reset active portion T4A through the third hole H3, and the middle portion of the first connection member 311 is connected to the second boost plate Cboost2 through the fourth hole H4.

In this embodiment, the second hole H2 penetrates the second interlayer dielectric layer 211, the third hole H3 penetrates the second interlayer dielectric layer 211, and the fourth hole H4 penetrates the second interlayer dielectric layer 211 and the first interlayer dielectric layer 209.

As shown in fig. 13 and 14, the first source-drain layer 212 further includes a second connection member 312, the second connection member 312 is disposed between the emission control signal line EM and the second scanning signal line Nscan, a first end of the second connection member 312 is connected to one end of the first connection member 311, and a second end of the second connection member 312 is connected to the driving gate T1G of the driving transistor T1 through the first hole H1.

In this embodiment, the first hole H1 penetrates the second interlayer dielectric layer 211, the first interlayer dielectric layer 209, and the second gate insulating layer 207.

As shown in fig. 13 and 14, the first source-drain layer 212 further includes a third connection member 313, the third connection member 313 is disposed between the third scan signal line Nscan and the first reset signal line Vi-Gate, the third connection member 313 is disposed to extend along the second direction Y, a first end of the third connection member 313 is connected to the second end of the first reset active portion T4A through the fifth hole H5, and a second end of the third connection member 313 is connected to the first reset signal line Vi-Gate through the sixth hole H6.

In this embodiment, the fifth hole H5 penetrates the second interlayer dielectric layer 211, and the sixth hole H6 penetrates the second interlayer dielectric layer 211 and the first interlayer dielectric layer 209.

As shown in fig. 13 and 14, the first source-drain layer 212 further includes a fourth connection member 314 and a fifth connection member 315, the fourth connection member 314 is disposed between the second scan signal line Nscan and the emission control signal line EM, the fourth connection member 314 extends along the second direction Y, the first end of the fourth connection member 314 is connected to the second end of the compensation active portion T3A through the seventh hole H7, and the second end of the fourth connection member 314 is connected to the first end of the second emission control active portion T6A of the second emission control transistor T6 through the eighth hole H8. The fifth connection member 315 is disposed on a side of the emission control signal line EM away from the second scan signal line Nscan, and the fifth connection member 315 is connected to the second end of the second emission control active portion T6A through a ninth hole H9.

In this embodiment, the seventh hole H7 penetrates the second interlayer dielectric layer 211, and the eighth hole H8 penetrates the second interlayer dielectric layer 211, the first interlayer dielectric layer 209, the second gate insulating layer 207, and the first gate insulating layer 205.

As shown in fig. 13 and 14, the first source-drain layer 212 further includes a sixth connection member 316, the sixth connection member 316 is disposed between the second scan signal line Nscan and the emission control signal line EM, the sixth connection member 316 is connected to the first end of the first emission control active portion T5A through the tenth hole H10, and the sixth connection member 316 is connected to the first end of the driving active portion T1A through the eleventh hole H11.

In the present embodiment, the tenth hole H10 penetrates the second interlayer dielectric layer 211, the first interlayer dielectric layer 209, the second gate insulating layer 207, and the first gate insulating layer 205, and the eleventh hole H11 penetrates the second interlayer dielectric layer 211, the first interlayer dielectric layer 209, the second gate insulating layer 207, and the first gate insulating layer 205.

As shown in fig. 13 and 14, the first source-drain layer 212 further includes a seventh connection member 317, the seventh connection member 317 is disposed between the first scanning signal line Pscan and the third scanning signal line Nscan, the seventh connection member 317 is square, and a vertex angle of the seventh connection member 317 may be chamfered. The seventh link 317 is connected to a first end of the switching active part T2A through a twelfth hole H12.

In the present embodiment, the twelfth hole H12 penetrates the second interlayer dielectric layer 211, the first interlayer dielectric layer 209, the second gate insulating layer 207, and the first gate insulating layer 205.

As shown in fig. 13 and 14, the first source-drain layer further includes a second reset signal line Vi-Ano connected to the first end of the second reset active portion T7A through a thirteenth hole H13, and the thirteenth hole H13 penetrates the second interlayer dielectric layer 211, the first interlayer dielectric layer 209, the second gate insulating layer 207, and the first gate insulating layer 205.

In this embodiment, the second reset signal line Vi-Ano includes a first sub-reset line segment Vi-Ano1, a second sub-reset line segment Vi-Ano2, and a third sub-reset line segment Vi-Ano3, the second sub-reset line segment Vi-Ano2 is connected between the first sub-reset line segment Vi-Ano1 and the third sub-reset line segment Vi-Ano3, the extension directions of the first sub-reset line segment Vi-Ano1 and the third sub-reset line segment Vi-Ano3 are the same as the extension direction of the first scan signal line Pscan1, and the first sub-reset line segment Vi-Ano1, the third sub-reset line segment Vi-Ano3, and the first scan signal line Pscan are all extended along the first direction X. The extending direction of the second sub-reset line segment Vi-Ano2 is the same as the extending direction of the Data signal line Data, and the second sub-reset line segment Vi-Ano2 and the Data signal line Data are both arranged along the second direction Y in an extending manner.

The front projection of the first sub-reset line segment Vi-Ano1 on the substrate 1 is arranged between the front projection of the first scanning signal line Pscan on the substrate 1 and the front projection of the second scanning signal line Nscan1 on the substrate 1, the front projection of the second sub-reset line segment Vi-Ano2 on the substrate 1 is arranged between the front projection of the second reset active portion T7A of the second reset transistor T7 on the substrate 1 and the front projection of the first reset active portion T4A on the substrate 1, and the front projection of the third sub-reset line segment Vi-Ano3 on the substrate 1 is arranged on the side of the front projection of the first reset signal line Vi-Gate on the substrate 1 away from the front projection of the first reset active portion T4A on the substrate 1.

As shown in fig. 2 to 14, the second source-drain layer 214 includes a Data signal line Data and a dc high voltage power signal line VDD, which are both extended in the second direction Y and are spaced apart in the first direction X, and the Data signal line Data is connected to the first end of the switching active portion T2A through a twelfth via H12, and the twelfth via H12 penetrates the first planarization layer 213, the second interlayer dielectric layer 211, the first interlayer dielectric layer 209, the second gate insulating layer 207, and the first gate insulating layer 205.

In some embodiments, the first scan signal line Pscan is a first scan signal line Pscan (n), the second scan signal line Nscan is a second scan signal line Nscan (n), the third scan signal line Nscan2 is a third scan signal line Nscan (n-5), and the fourth scan signal line Pscan2 is a fourth scan signal line Pscan (n-1), where n is a positive integer.

As shown in fig. 15, fig. 15 is a timing chart of a pixel driving circuit of a display panel according to an embodiment of the present application, and the operation principle of the pixel driving circuit is described as follows, in a first stage T1, a third scanning signal line Nscan (n-5) outputs a high potential, a first reset transistor T4 is turned on, and a first reset signal line Vi-Gate outputs a first reset signal to reset a third node Q; in the second stage T2, the first scan signal line Pscan (n) inputs a low potential, the second scan signal line Nscan (n) inputs a high potential, the switching transistor T2 and the compensation transistor T3 are turned on, the Data signal line Data outputs a Data signal to the third node Q, and simultaneously the fourth scan signal line Pscan (n-1) inputs a low potential, the second reset transistor T7 is turned on, the second reset signal line Vi-Ano outputs a second reset signal to reset the fourth node C; in the third stage T3, the emission control signal line EM outputs a low potential, the first and second emission control transistors T5 and T6 are turned on, and the direct-current high-voltage power signal line VDD writes signals to the first, second and fourth nodes a, B and C, so that the light emitting device 21 emits light.

The embodiment of the application further provides a display device, and fig. 16 is a schematic structural diagram of the display device provided by the embodiment of the application, where fig. 16 is a schematic structural diagram of the display device provided by the embodiment of the application, and the display device 1000 includes a display panel 100 and a housing 200, where the display panel 100 is disposed on the housing 200, the display panel 100 may be the display panel 100 provided by any one of the embodiments, the display device 1000 may be a mobile display device, such as a smart phone, a smart watch, a tablet computer, a notebook computer, and the like, and the display device 1000 may also be a fixed display device, such as a television, a desktop computer, and the like.

In summary, although the present application has been described in terms of the preferred embodiments, the preferred embodiments are not limited to the above embodiments, and various modifications and alterations can be made by those skilled in the art without departing from the spirit and scope of the application, and the scope of the application is defined by the appended claims.

Claims

1. The utility model provides a display panel, its characterized in that includes substrate and a plurality of sub-pixel group, every sub-pixel group includes two sub-pixel units, every sub-pixel unit is interior to be equipped with light emitting device and with the pixel drive circuit that light emitting device connects, pixel drive circuit includes:

A compensation transistor, a first electrode of which is connected to the third node, a second electrode of which is connected to the second node, and a compensation gate of which is connected to a second scan signal line;

A first reset transistor having a first electrode connected to a first reset signal line, a second electrode connected to the third node, and a first reset gate connected to a third scan signal line;

wherein the compensation transistor includes a compensation active portion, the first reset transistor includes a first reset active portion, and an extension direction of at least one of the compensation active portion and the first reset active portion is the same as an extension direction of the first scan signal line; the front projection of the compensation active part on the substrate and the front projection of the first reset active part on the substrate are arranged on two sides of the front projection of the first scanning signal line on the substrate, the front projection of the compensation active part on the substrate and the front projection of the second scanning signal line on the substrate are overlapped, and the front projection of the first reset active part on the substrate and the front projection of the third scanning signal line on the substrate are overlapped.

2. The display panel of claim 1, wherein the display panel comprises:

the first source-drain electrode layer is arranged on one side of the second active layer, which is far away from the second grid electrode layer;

3. The display panel of claim 2, wherein the first scan signal line is disposed at the first gate layer, and the second gate layer includes the second scan signal line and the third scan signal line.

4. The display panel of claim 3, wherein the first source-drain layer includes a first connection member, and the compensation active portion is connected to the first reset active portion through the first connection member.

5. The display panel of claim 3, wherein the second scan signal line includes a first sub-scan line segment and a second sub-scan line segment connected to the first sub-scan line segment, and the third scan signal line includes a third sub-scan line segment and a fourth sub-scan line segment connected to the third sub-scan line segment;

6. A display panel as claimed in claim 3, characterized in that in at least one of the sub-pixel groups the compensation active in one of the sub-pixel units is disconnected from the compensation active in the other of the sub-pixel units, the first reset active in one of the sub-pixel units being arranged in succession with the first reset active in the other of the sub-pixel units.

7. The display panel of claim 4, wherein the pixel driving circuit comprises a boost capacitor comprising a first boost plate and a second boost plate, the first boost plate connected to the first scan signal line, the second boost plate connected to the third node;

8. The display panel according to claim 7, wherein the pixel driving circuit further comprises a second reset transistor, wherein the first source-drain layer further comprises a second reset signal line, wherein a first electrode of the second reset transistor is connected to the second reset signal line, wherein a second electrode of the second reset transistor is connected to a fourth node, and wherein a second reset gate of the second reset transistor is connected to a fourth scan signal line;

9. The display panel of claim 8, wherein the pixel driving circuit further comprises:

10. A display panel as claimed in any one of claims 1 to 9, characterized in that two of the sub-pixel elements of the same sub-pixel group are symmetrically arranged.