CN118693107A

CN118693107A - Display panel and display device

Info

Publication number: CN118693107A
Application number: CN202411200049.1A
Authority: CN
Inventors: 陈菲
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2024-08-29
Filing date: 2024-08-29
Publication date: 2024-09-24

Abstract

The application provides a display panel and a display device; the display panel comprises a second active layer and a second shading layer, wherein the second shading layer is arranged between the substrate and the second active layer, the pattern of the second shading layer is the same as that of the second active layer, and the pattern of the second shading layer is correspondingly arranged with that of the second active layer, so that the second shading layer can be correspondingly arranged with that of a transistor in the second active layer, the second shading layer can shade the active pattern of the transistor in the second active layer, the active pattern of the transistor in the second active layer is prevented from being influenced by light, the photosensitivity and the electrical property of the transistor are improved, and the performance of the display panel is improved; and the second shading layer has the same pattern as the second active layer, so that the second shading layer can be formed by adopting a mask plate for forming the second active layer, thereby reducing the complexity and cost of the process without increasing the mask plate.

Description

Display panel and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

With the development of display devices, the requirements of the existing display devices on power consumption and screen ratio are higher and higher, and in order to reduce the power consumption and improve the screen ratio, the existing display devices adopt low-temperature polysilicon oxide (Low Temperature Polysilicon Oxide, LTPO) technology. The LTPO technology refers to that a low-temperature polysilicon thin film transistor and an oxide thin film transistor are adopted at the same time, so that the driving circuit has the advantages of the low-temperature polysilicon thin film transistor and the oxide thin film transistor, and therefore power consumption and leakage current are reduced. However, the existing display device adopting LTPO technology has the defects of more film layers and correspondingly more required mask plates, so that the process is more complex and the cost is higher. In order to reduce the number of masks, some gate layers and insulating layers are removed in the conventional display device, but this may result in bottom gate loss of the oxide thin film transistor, and photosensitivity and electrical property of the thin film transistor are deteriorated.

Therefore, the conventional display device using LTPO technology has the technical problems of poor photosensitivity and poor electrical property caused by the bottom gate deficiency of the oxide thin film transistor.

Disclosure of Invention

The embodiment of the application provides a display panel and a display device, which are used for solving the technical problems of poor photosensitivity and poor electrical property caused by bottom gate deficiency of an oxide thin film transistor in the existing display device adopting LTPO technology.

An embodiment of the present application provides a display panel including:

A substrate;

The driving circuit layer is arranged on one side of the substrate and comprises a first shading layer, a second shading layer, a first active layer and a second active layer, wherein the first shading layer is arranged between the substrate and the first active layer, the first active layer is arranged between the first shading layer and the second active layer, and the second shading layer is arranged between the substrate and the second active layer;

The pattern of the second light shielding layer is the same as the pattern of the second active layer, and the pattern of the second light shielding layer is arranged corresponding to the pattern of the second active layer.

Meanwhile, an embodiment of the present application provides a display device including the display panel according to any one of the above embodiments.

The beneficial effects are that: the application provides a display panel and a display device; the display panel comprises a second active layer and a second shading layer, wherein the second shading layer is arranged between the substrate and the second active layer, the pattern of the second shading layer is the same as that of the second active layer, and the pattern of the second shading layer is correspondingly arranged with that of the second active layer, so that the second shading layer can be correspondingly arranged with that of a transistor in the second active layer, the second shading layer can shade the active pattern of the transistor in the second active layer, the active pattern of the transistor in the second active layer is prevented from being influenced by light, the photosensitivity and the electrical property of the transistor are improved, and the performance of the display panel is improved; and the second shading layer has the same pattern as the second active layer, so that the second shading layer can be formed by adopting a mask plate for forming the second active layer, thereby reducing the complexity and cost of the process without increasing the mask plate.

Drawings

The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a first comparative display device according to an embodiment of the present application.

Fig. 2 is a schematic diagram of a second comparative display device according to an embodiment of the present application.

Fig. 3 is a schematic diagram of a third comparative display device according to an embodiment of the present application.

Fig. 4 is a schematic diagram of a fourth comparative display device according to an embodiment of the present application.

Fig. 5 is a schematic view of a light shielding film of the comparative display device of fig. 4.

Fig. 6 is a schematic diagram of a film layer of a display panel according to an embodiment of the application.

Fig. 7 is a circuit diagram of a pixel driving circuit of a display panel according to an embodiment of the application.

Fig. 8 is a laminated diagram of film layers of a display panel according to an embodiment of the present application.

Fig. 9 is an exploded view of a second light shielding layer of the display panel of fig. 8.

Fig. 10 is an exploded view of a first light shielding layer of the display panel of fig. 8.

Fig. 11 is an exploded view of a first active layer of the display panel of fig. 8.

Fig. 12 is an exploded view of a first gate layer of the display panel of fig. 8.

Fig. 13 is an exploded view of a second active layer of the display panel of fig. 8.

Fig. 14 is an exploded view of a second gate layer of the display panel of fig. 8.

Fig. 15 is an exploded view of a first source/drain layer of the display panel of fig. 8.

Fig. 16 is an exploded view of a second source/drain layer of the display panel of fig. 8.

Fig. 17 is an exploded view of a first via of the display panel of fig. 8.

Fig. 18 is an exploded view of a second via of the display panel of fig. 8.

Fig. 19 is an exploded view of a third via of the display panel of fig. 8.

Fig. 20 is an exploded view of a fourth via of the display panel of fig. 8.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.

In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

In the present application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.

The following disclosure provides many different embodiments, or examples, for implementing different features of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.

Fig. 1 is a schematic diagram of a first comparative display device according to an embodiment of the present application. Fig. 2 is a schematic diagram of a second comparative display device according to an embodiment of the present application. Fig. 3 is a schematic diagram of a third comparative display device according to an embodiment of the present application. Fig. 4 is a schematic diagram of a fourth comparative display device according to an embodiment of the present application. Fig. 5 is a schematic view of a light shielding film of the comparative display device of fig. 4.

As shown in fig. 1 to 5, as primers of the embodiments of the present application, some comparative display devices are provided to illustrate the principle of the technical problem to be solved by the embodiments of the present application. As shown in fig. 1, a contrast display device employing LTPO technology includes a substrate 101, a light-shielding film 102, a barrier film 103, a buffer film 104, a low-temperature polysilicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source-drain film 116, a first planarization film 117, a second source-drain film 118, a second planarization film 119, a third source-drain film 121, a third planarization film 122, an anode film 123, a pixel defining film 124, and a support film 125. As can be seen from fig. 1, the comparative display device includes three layers of source-drain electrode films and three layers of gate electrode films, so that the comparative display device needs to be formed by using 16 mask plates, and the process is relatively complex and the cost is relatively high.

In order to solve the problem of complex process of the comparative display device, one of the gate films and the insulating film is removed in another comparative display device, as shown in fig. 2, it can be seen that the second gate film 109 and the second gate insulating film 108 are removed in the comparative display device, and the number of mask plates can be reduced to 14, but still there are problems of more mask plates, more complex process and higher cost.

In order to solve the problem of complex process of the comparative display device, another comparative display device further removes a layer of source drain film and insulating film, as shown in fig. 3, by removing the third source drain film 121 and the third planarization film 122, the number of mask plates can be reduced to 13; however, as can be seen from fig. 2 and 3, the oxide semiconductor film 112 is not masked, which results in the bottom gate of the oxide thin film transistor being missing, and the photosensitivity and electrical properties of the thin film transistor are deteriorated. Therefore, the conventional display device using LTPO technology has the technical problems of poor photosensitivity and poor electrical property caused by the bottom gate deficiency of the oxide thin film transistor.

Even in some contrast display devices, in order to solve the problem of bottom gate deficiency of the oxide thin film transistor in the contrast display device, a light shielding film is used to shield the oxide semiconductor film, as shown in fig. 4 and 5, it can be seen that the light shielding film 102 is disposed under the oxide semiconductor film 112, but this may result in that the light shielding films are only connected laterally and not connected longitudinally, and further, the impedance of the light shielding film is gradually increased from two sides to the middle, and further, the electrical property of the low temperature polysilicon thin film transistor is different, so that poor display is caused, that is, a new problem may be introduced.

The embodiment of the application aims at the technical problems and provides a display panel and a display device, which are used for solving the technical problems.

Fig. 6 is a schematic diagram of a film layer of a display panel according to an embodiment of the application. Fig. 7 is a circuit diagram of a pixel driving circuit of a display panel according to an embodiment of the application. Fig. 8 is a laminated diagram of film layers of a display panel according to an embodiment of the present application. Fig. 9 is an exploded view of a second light shielding layer of the display panel of fig. 8. Fig. 10 is an exploded view of a first light shielding layer of the display panel of fig. 8. Fig. 11 is an exploded view of a first active layer of the display panel of fig. 8. Fig. 12 is an exploded view of a first gate layer of the display panel of fig. 8. Fig. 13 is an exploded view of a second active layer of the display panel of fig. 8. Fig. 14 is an exploded view of a second gate layer of the display panel of fig. 8. Fig. 15 is an exploded view of a first source/drain layer of the display panel of fig. 8. Fig. 16 is an exploded view of a second source/drain layer of the display panel of fig. 8. Fig. 17 is an exploded view of a first via of the display panel of fig. 8. Fig. 18 is an exploded view of a second via of the display panel of fig. 8. Fig. 19 is an exploded view of a third via of the display panel of fig. 8. Fig. 20 is an exploded view of a fourth via of the display panel of fig. 8.

The embodiment of the present application provides a display panel, as shown in fig. 6 to 20, the display panel 2 includes a substrate 201 and a driving circuit layer 22; the driving circuit layer 22 is disposed on one side of the substrate 201, the driving circuit layer 22 includes a first light shielding layer 204, a second light shielding layer 202, a first active layer 207 and a second active layer 212, the first light shielding layer 204 is disposed between the substrate 201 and the first active layer 207, the first active layer 207 is disposed between the first light shielding layer 204 and the second active layer 212, and the second light shielding layer 202 is disposed between the substrate 201 and the second active layer 212;

The pattern of the second light shielding layer 202 is the same as the pattern of the second active layer 212, and the pattern of the second light shielding layer 202 is disposed corresponding to the pattern of the second active layer 212.

The embodiment of the application provides a display panel, which comprises a second active layer and a second shading layer, wherein the second shading layer is arranged between a substrate and the second active layer, the pattern of the second shading layer is the same as that of the second active layer, and the pattern of the second shading layer is correspondingly arranged with that of the second active layer, so that the second shading layer can be correspondingly arranged with that of a transistor in the second active layer, the second shading layer can shade the active pattern of the transistor in the second active layer, the active pattern of the transistor in the second active layer is prevented from being influenced by light, the photosensitivity and the electrical property of the transistor are improved, and the performance of the display panel is improved; and the second shading layer has the same pattern as the second active layer, so that the second shading layer can be formed by adopting a mask plate for forming the second active layer, thereby reducing the complexity and cost of the process without increasing the mask plate.

Specifically, the embodiment of the present application refers to that the pattern of the second light shielding layer is the same as the pattern of the second active layer, which means that the pattern of the second light shielding layer is substantially the same as the pattern of the second active layer, and both may be completely the same, but in consideration of the process error, there may be a certain difference between the two, and at this time, the pattern of the second light shielding layer may still be considered to be the same as the pattern of the second active layer, for example, the pattern of the second light shielding layer is substantially the same as the pattern of the second active layer, but when etching two film layers, due to a certain error in the process, there is a certain difference between the shape of a certain edge of the second light shielding layer and the shape of the corresponding edge of the second active layer, and at this time, the pattern of the second light shielding layer may still be considered to be the same as the pattern of the second active layer.

Specifically, the second light shielding layer and the second active layer can be formed by adopting the same mask plate, so that when the display panel is formed, the active patterns of the second active layer can be shielded by the second light shielding layer, and the number of mask plates required by forming the display panel can not be increased. Compared with the method that the number of mask plates is increased by adding new film layers to shade active patterns (including active patterns of compensation transistors and active patterns of first initialization transistors) in a second active layer in some display devices, the method and the device have the advantages that the process complexity is increased and the cost is increased.

Specifically, when the second light-shielding layer and the second active layer are formed by using the same mask plate, it is understood that, in theory, the patterns of the second light-shielding layer and the second active layer should be the same pattern, but in the actual production process, it is understood that a slight difference may exist between the second light-shielding layer and the second active layer due to a process deviation, particularly when the material of the second light-shielding layer is different from the material of the second active layer, different methods may be adopted to etch the second light-shielding layer and the second active layer when the second light-shielding layer and the second active layer are etched, even if the same method is adopted to etch, a certain difference may exist between the patterns of the second light-shielding layer and the second active layer due to a difference of the characteristics of the material, and at this time, the pattern of the second light-shielding layer and the pattern of the second active layer may still be considered to be the same.

Specifically, the arrangement of the pattern of the second light shielding layer corresponding to the pattern of the second active layer in the embodiment of the present application means that the projection of the pattern of the second light shielding layer on the substrate coincides with the projection of the pattern of the second active layer on the substrate, and in the same manner, the arrangement of the light shielding pattern corresponding to the active pattern of the transistor means that the projection of the light shielding pattern on the substrate coincides with the projection of the active pattern of the transistor on the substrate, and it is understood that the active patterns of the transistors each include a doped portion and a channel portion, and the channel portion is susceptible to the influence of light to cause the performance to change, so that the light shielding pattern can be arranged corresponding to the active pattern of the transistor, specifically, for example, the arrangement of the light shielding pattern corresponding to the active pattern of the compensation transistor means that the projection of the light shielding pattern on the substrate coincides with the projection of the active pattern of the compensation transistor on the substrate.

Specifically, compared with the scheme of forming an active pattern shielding a second active layer by adopting a first light shielding layer, the voltage drop of the first light shielding layer can be increased along two sides to the middle area, so that the problem of poor display is caused, and the second shading layer can shade the active pattern of the second active layer, so that the transistor adopting the active pattern of the second active layer is prevented from being influenced by light, the electrical property and the photosensitivity of the thin film transistor are improved, the performance of the display panel is improved, the second shading layer is identical to the pattern of the second active layer, the second shading layer and the second active layer can be formed by adopting the same mask plate, and the second shading layer is not required to be formed by adding the mask plate.

In some embodiments, as shown in fig. 6 and 8, the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array, and each of the repeating units 30 includes two pixel driving circuits 31 symmetrically arranged.

In particular, it will be appreciated that the display panel will include a plurality of repeating units arranged in an array, and the pixel driving circuit in each repeating unit may be referred to as a design in one of the repeating units according to the embodiments of the present application.

Specifically, it is understood that, in order to illustrate a specific design of a certain film layer or a certain structure, each part will be named separately, but it is understood that, when a plurality of parts of a certain film layer or a certain structure are connected together, the same signals are transmitted, and the parts belong to the same structure, and in fact, the same naming can be adopted. For example, as shown in fig. 10, the first light shielding layer 204 includes a light blocking pattern 204a and a connection line 204b, but in reality, the light blocking pattern 204a and the connection line 204b are portions of the same structure, and are connected to each other, and the portions of the structure transmit the same signal without considering a voltage drop, which may be named the same, for example, each portion may be named as a portion of the light blocking pattern. Similarly, for other film layers and other structures, reference may be made to the above description, and the description will not be repeated in the following embodiments.

Specifically, as shown in fig. 8, in order to show the structure of the second light shielding layer in the stacked view of the respective film layers of the display panel, the second light shielding layer is disposed on the uppermost side, but it is understood that in practice, the second light shielding layer is located between the substrate and the second active layer, and the specific disposition of the film layers can be seen from the description in the embodiments described below.

In some embodiments, as shown in fig. 6 and 7, the driving circuit layer 22 includes a pixel driving circuit 31, and the pixel driving circuit 31 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3, and a first initialization transistor T4, where the switching transistor T2 and the driving transistor T1 are connected to a first node a; an electrode of the compensation transistor T3, an electrode of the first initializing transistor T4 and the driving transistor T1 are connected to the second node Q, and another electrode of the compensation transistor T3 and the driving transistor T1 are connected to the third node B;

Wherein the second active layer 212 includes an active pattern T3A of the compensation transistor T3 and an active pattern T4A of the first initialization transistor T4, the second light shielding layer 202 includes a light shielding pattern 202a, the light shielding pattern 202a is identical to the active pattern T3A of the compensation transistor T3 and the active pattern T4A of the first initialization transistor T4, and the light shielding pattern 202a is disposed corresponding to the active pattern T3A of the compensation transistor T3 and the active pattern T4A of the first initialization transistor T4. By making the light shielding pattern identical to the active pattern of the compensation transistor and the active pattern of the first initialization transistor and the light shielding pattern being provided corresponding to the active pattern of the compensation transistor and the active pattern of the first initialization transistor, the active pattern of the compensation transistor and the active pattern of the first initialization transistor can be shielded from light by the light shielding pattern, whereby the electric property and photosensitivity of the compensation transistor and the first initialization transistor can be improved.

In some embodiments, as shown in fig. 7, 8 and 9, the pixel driving circuit 31 further includes a storage capacitor Cst, the second active layer 212 further includes a plate of the storage capacitor Cst, the second light shielding layer 202 further includes an auxiliary pattern 202b, the auxiliary pattern 202b is the same as the plate of the storage capacitor Cst, and the auxiliary pattern is disposed corresponding to the plate of the storage capacitor Cst. When two gate layers are adopted in the display panel, a second active layer is adopted to form a polar plate of the storage capacitor, and accordingly, the second shading layer can be made to form an auxiliary pattern which is the same as the pattern of the polar plate of the storage capacitor and is correspondingly arranged with the polar plate of the storage capacitor.

In particular, the second active layer may form a second plate of the storage capacitor.

Specifically, it can be understood that the second active layer forms the second plate of the storage capacitor, so that the second plate of the storage capacitor needs to have better electrical property, so that the second plate of the storage capacitor can be doped, the electrical property of the second plate of the storage capacitor is consistent with or even exceeds that of the doped part of the active pattern, and the electrical property of the storage capacitor is better.

In some embodiments, as shown in fig. 7, the gate of the switching transistor T2 is connected to the first scan signal line Pscan, the first electrode of the switching transistor T2 is connected to the DATA line DATA, and the second electrode of the switching transistor T2 and the first electrode of the driving transistor T1 are connected to the first node a; the gate of the compensation transistor T3 is connected to the second scanning signal line Nscan, the first electrode of the compensation transistor T3 and the gate of the driving transistor T1 are connected to the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the first initializing transistor T4 is connected to the third scanning signal line Nscan, the first electrode of the first initializing transistor T4 is connected to the first initializing signal line VI-G, and the second electrode of the first initializing transistor T4 and the gate of the driving transistor T1 are connected to the second node Q; the pixel driving circuit 31 further includes:

a first light emitting control transistor T5, a gate electrode of the first light emitting control transistor T5 is connected to a light emitting control signal line EM, a first electrode of the first light emitting control transistor T5 is connected to a high potential power line VDD, and a second electrode of the first light emitting control transistor T5 and a first electrode of a driving transistor T1 are connected to a first node a;

A second light emission control transistor T6, a gate of the second light emission control transistor T6 is connected to the light emission control signal line EM, and a first electrode of the second light emission control transistor T6 and a second electrode of the driving transistor T1 are connected to the third node B;

A second initialization transistor T7, wherein a gate of the second initialization transistor T7 is connected to the fourth scan signal line Pscan, a first electrode of the second initialization transistor T7 is connected to the second initialization signal line VI-ANO, and a second electrode of the second initialization transistor T7 is connected to the second electrode of the second emission control transistor T6 at a fourth node C;

A third initialization transistor T8, a gate of the third initialization transistor T8 is connected to the fourth scan signal line Pscan, a first electrode of the third initialization transistor T8 is connected to a third initialization signal line VI3, and a second electrode of the third initialization transistor T8 is connected to the first node a with a first electrode of the driving transistor T1;

A storage capacitor Cst, wherein one polar plate of the storage capacitor Cst is connected with the high-potential power line VDD, and the other polar plate of the storage capacitor Cst and the gate electrode of the driving transistor T1 are connected to a second node Q;

and one polar plate of the boost capacitor Cboost is connected with the first scanning signal line Pscan, and the other polar plate of the boost capacitor Cboost is connected with the second electrode of the first initializing transistor T4.

Specifically, as shown in fig. 6 and 7, the display panel 2 further includes a light emitting layer 23, the light emitting layer 23 includes a light emitting device LED, the light emitting device LED is connected to the pixel driving circuit, the positive electrode of the light emitting device LED is connected to the second electrode of the second initializing transistor T7, and the negative electrode of the light emitting device LED is connected to the low potential power supply line VSS.

In some embodiments, as shown in fig. 6, the driving circuit layer 22 further includes a first gate layer 209, a second gate layer 214, a first source drain layer 216, and a second source drain layer 218, where the first gate layer 209 is disposed between the first active layer 207 and the second active layer 212, the second gate layer 214 is disposed between the second active layer 212 and the first source drain layer 216, and the first source drain layer 216 is disposed between the second gate layer 214 and the second source drain layer 218. By making the driving circuit layer include the first gate layer, the second gate layer, the first source drain layer and the second source drain layer, the process steps of the display panel can be reduced, and mask plates required for forming the display panel can be reduced.

In some embodiments, as shown in fig. 6 to 8 and 11, the first active layer 207 includes an active pattern T1A of a driving transistor T1, an active pattern T2A of a switching transistor T2, an active pattern T6A of a second light emission control transistor T5, an active pattern T7A of a second initialization transistor T7, and an active pattern T8A of a third initialization transistor T8, the active pattern T1A of the driving transistor T1 is disposed along a first direction X, and the active pattern T1A of the driving transistor T1 is connected to the active pattern T2A of the switching transistor T2, the active pattern T5A of the first light emission control transistor T5, and the active pattern T6A of the second light emission control transistor T6, the active pattern T2A of the switching transistor T2 is disposed along the first direction X with the active pattern T7A of the first light emission control transistor T5, and the active pattern T8A of the second initialization transistor T7 is disposed along the first direction X, and the active pattern T7A of the second light emission control transistor T6 is connected to the active pattern T1A of the first light emission control transistor T5, and the active pattern T6A of the second light emission control transistor T6 is disposed along the first direction X, and the active pattern T7A of the second light emission control transistor T6 is disposed along the first direction X with the active pattern T6A of the first light emission control transistor T5; and an included angle between the first direction X and the second direction Y is larger than 0 and smaller than or equal to 90 degrees.

Specifically, it can be seen that the active patterns T7A of the second initialization transistors T7 of the adjacent two pixel driving circuits are connected within one repeating unit.

In some embodiments, as shown in fig. 6 to 8 and 12, the first gate layer 209 includes a first initialization signal line VI-G, a first scan signal line Pscan, a light emission control signal line EM, a fourth scan signal line Pscan, a gate T1G of a driving transistor T1, a gate T2G of a switching transistor T2, a gate T5G of a first light emission control transistor T5, a gate T6G of a second light emission control transistor T6, a gate T7G of a second initialization transistor T7, a gate T8G of a third initialization transistor T8, and a first plate Cst1 of a storage capacitor Cst, wherein the first initialization signal line VI-G, the first scan signal line Pscan, the first plate Cst1 of the storage capacitor Cst, the light emission control signal line EM, and the fourth scan signal line Pscan are sequentially spaced along the second direction Y.

Specifically, as can be seen from fig. 12, the gate T2G of the switching transistor T2 is a part of the first scanning signal line Pscan, and it can be understood that, since the gate T2G of all the switching transistors T2 in a row of pixel units is connected to the same first scanning signal line Pscan, when the first scanning signal line Pscan is formed, the portion of the first scanning signal line corresponding to the channel of the switching transistor T2 of each pixel unit is used as the gate of the switching transistor T2 of each pixel unit, the same structure is identified by two reference numerals, and the gate T1G of the driving transistor T1 is used as the first plate Cst1 of the storage capacitor Cst, the portion of the light-emitting control signal line corresponding to the channel of the first light-emitting control transistor T5 is used as the gate T5G of the first light-emitting control transistor T5, the portion of the light-emitting control signal line EM corresponding to the channel of the second light-emitting control transistor T6 is used as the gate T6G of the second light-emitting control transistor T6, the portion of the fourth scanning signal line Pscan corresponds to the channel of the initializing transistor T7 is used as the gate T8 of the third gate of the initializing transistor T7 of the third transistor T8.

In some embodiments, as shown in fig. 6 to 8 and 13, the second active layer 212 includes an active pattern T3A of the compensation transistor T3, an active pattern T4A of the first initialization transistor T4, and a second plate Cst2 of the storage capacitor Cst, the active pattern T3A of the compensation transistor T3 is connected to the active pattern T4A of the first initialization transistor T4, the second plate Cst2 of the storage capacitor Cst is disposed on one side of the active pattern T3A of the compensation transistor T3 along the first direction X, and a via 331 is disposed on the second plate Cst of the storage capacitor Cst. The second active layer forms the second polar plate of the storage capacitor, so that the storage capacitor can be arranged in the pixel driving circuit, and the second polar plate of the storage capacitor is provided with a through hole, so that the first electrode of the compensation transistor can be normally connected to the grid electrode of the driving transistor.

Specifically, the first electrode of the compensation transistor passes through the second electrode plate of the storage capacitor and is connected to the grid electrode of the driving transistor by arranging the through hole on the second electrode plate of the storage capacitor, so that the pixel driving circuit works normally.

Specifically, as shown in fig. 12 and 13, the first gate layer 209 further includes a first plate Cboost1 of the boost capacitor Cboost, the second active layer 212 further includes a second plate Cboost2 of the boost capacitor Cboost, an overlapping portion of the first scan signal line Pscan and the active pattern T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and an overlapping portion of the active pattern T4A of the first initialization transistor T4 and the first scan signal line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

In some embodiments, as shown in fig. 6 to 8 and 14, the second gate layer 214 includes a second scan signal line Nscan, a third scan signal line Nscan2, a third initialization signal line VI3, a gate T3G of the compensation transistor T3, and a gate T4G of the first initialization transistor T4, and the third scan signal line Nscan2, the second scan signal line Nscan, and the third initialization signal line VI3 are sequentially disposed along the second direction Y.

Specifically, the projection of the light shielding pattern on the substrate may overlap with the projection of the third scanning signal line on the substrate, so that the coupling capacitance between the light shielding pattern and other signal lines is reduced, and even if the light shielding pattern is coupled with the third scanning signal line, the potential of the third scanning signal line may be the same as the shielding of the active pattern of the first initialization transistor by the light shielding pattern, so that the gate control capability of the first initialization transistor may be improved.

Specifically, the projection of the light shielding pattern on the substrate may overlap with the projection of the second scanning signal line on the substrate, so that the coupling capacitance between the light shielding pattern and other signal lines is reduced, and even if the light shielding pattern is coupled with the second scanning signal line, the potential of the second scanning signal line may be the same as the shielding of the active pattern of the compensation transistor by the light shielding pattern, so that the gate control capability of the compensation transistor may be improved.

In some embodiments, as shown in fig. 6 to 8 and 15, the first source drain layer 216 includes a first data connection line L1, a first electrode T2S of the switching transistor T2, a first electrode T3S of the compensation transistor T3, a second electrode T3D of the compensation transistor T3, a first electrode T4S of the first initialization transistor T4, a second electrode T4D of the first initialization transistor T4, a first electrode T5S of the first light emitting control transistor T5, a second electrode T5D of the first light emitting control transistor T5, a first electrode T6S of the second light emitting control transistor T6, a second electrode T6D of the second light emitting control transistor T6, a first electrode T7S of the second initialization transistor T7, a second electrode T7D of the second initialization transistor T7, a first electrode T8S of the third initialization transistor T8, a second electrode T8D of the third initialization transistor T8, and a second electrode VI-o line.

Specifically, as shown in fig. 15, it can be understood that, since the electrodes of the transistors are connected together, but in practical design, in order to increase the aperture ratio, the electrodes of the transistors share the same structure, and therefore, in fig. 15, the same structure is labeled with a plurality of reference numerals, for example, a structure is used as the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4, and as can be seen in fig. 7, the position where the second node Q is connected. Similarly, other structures can be used as a plurality of electrodes, and the positions of the nodes can be correspondingly determined.

Specifically, as shown in fig. 12 and 15, the first initializing signal line VI-G is connected to the first electrode T4S of the first initializing transistor T4 via the first connection terminal K1. For the problem that the projection distance between the first initializing signal line VI-G and the third scanning signal line Nscan on the substrate is smaller, a via hole is directly formed in the corresponding area of the first electrode of the first initializing transistor to connect the first initializing signal line, and the via hole is formed on the third scanning signal line Nscan, therefore, the first connecting end K1 can be arranged on the first source drain layer, the first electrode of the first initializing transistor T4 is connected through the first connecting end K1, meanwhile, a via hole is formed in the corresponding area of the first connecting end K1, so that the first connecting end K1 is connected with the first initializing signal line VI-G, connection between the first initializing signal line VI-G and the first electrode T4S of the first initializing transistor T4 is realized, and the first connecting end K1 is arranged on the symmetry axis of the two symmetrically arranged pixel driving circuits, so that the first electrode of the first initializing transistor T4 in the two symmetrically arranged pixel driving circuits is connected to the first initializing signal line through the same first connecting end K1, the number of via holes is reduced, and the yield is improved.

Specifically, as shown in fig. 8, 15 and 16, since the high-potential power line VDD is not overlapped with the first electrode T5S of the first light emitting control transistor T5 and the high-potential power line VDD is connected to one plate of the storage capacitor, the second connection terminal K2 is required to be provided, so that the second connection terminal K2 is connected to the high-potential power line VDD, and thus, a signal of the high-potential power line VDD can be transmitted to the first electrode T5S of the first light emitting control transistor T5, and the second connection terminal K3 can be provided, so that the second connection terminal K3 is connected to the second plate Cst2 of the storage capacitor Cst, thereby realizing connection of one plate of the storage capacitor Cst, the first light emitting control transistor T5 and the high-potential power line VDD.

Specifically, as shown in fig. 8 to 15, the first electrode T3S of the compensation transistor T3 is connected to the gate electrode T1G of the driving transistor T1, and therefore, a fourth connection terminal K4 may be disposed on the first source-drain layer, and the fourth connection terminal K4 passes through the through hole 331 to be connected to the gate electrode T1G of the driving transistor T1, thereby realizing connection between the gate electrode of the driving transistor T1 and the first electrode T3S of the compensation transistor T3.

In some embodiments, as shown in fig. 6 to 16, the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array, each of the repeating units 30 includes two pixel driving circuits 31 symmetrically arranged, and within the repeating units 30, the second source-drain layer 218 includes two DATA lines DATA, an initialization signal connection line L3, two high-potential power lines VDD and a second DATA connection line L2, two DATA lines DATA are symmetrically arranged, two high-potential power lines VDD are symmetrically arranged, and the initialization signal connection line L3 and the second DATA connection line L2 are symmetrically arranged.

Specifically, the high potential power line VDD may be connected to the second connection terminal K2 through a via hole, and the data line may be connected to the first electrode T2S of the switching transistor T2 through a via hole.

Specifically, as shown in fig. 16, the second source-drain layer 218 further includes a fifth connection terminal K5, where the fifth connection terminal K5 connects the second electrode T6D of the second light-emitting control transistor T6 and one electrode of the light-emitting device.

Specifically, it will be understood that, due to the design of the pixel driving circuit In the display area shown In the embodiment of the present application, the connection of the partial wires is located In the non-display area, so that there may be some failure of the connection of the partial wires together, but In reality, there may be connection, for example, the DATA line DATA may be provided with the first DATA connection line L1 arranged along the first direction and the second DATA connection line L2 arranged along the second direction for using the technique of arranging the fan-out line In the display area (Fanout In AA, FIAA), and may be connected with the DATA line outside the display area, but the embodiment of the present application shows the design of the pixel driving circuit, so that the connection is not shown, but In reality, it may be connected.

Meanwhile, in order to realize the mesh structure design of the initialization signal lines, the embodiment of the application sets the initialization signal connection line L3, wherein the initialization signal connection line L3 can realize the mesh structure design of at least one of the first initialization signal line, the second initialization signal line and the third initialization signal line, and the initialization signal connection line is connected with the initialization signal line in the same way.

For example, the first initializing signal line may be connected to the initializing signal connection line outside the display area, so as to implement the mesh structure design of the first initializing signal line, and similarly, implement the mesh structure designs of the second initializing signal line and the third initializing signal line. However, the embodiment of the present application is not limited thereto, and the partial initialization signal connection line may be connected to one of the first initialization signal line, the second initialization signal line, and the third initialization signal line, and the partial initialization signal connection line may be connected to the other of the first initialization signal line, the second initialization signal line, and the third initialization signal line, thereby implementing the mesh structure design of each initialization signal line.

In some embodiments, as shown in fig. 17, fig. 17 illustrates a location of a first via 341, where the first via 341 is a via etched from the first source-drain layer to the first active layer or the first gate layer.

In some embodiments, as shown in fig. 18, fig. 18 illustrates a location of a second via 342, where the second via 342 is a via etched from the first source-drain layer to the second active layer or the second gate layer.

In some embodiments, as shown in fig. 19, fig. 19 shows a location of a third via 343, where the third via 343 is a via etched from the second source drain layer to the first source drain layer.

In some embodiments, as shown in fig. 20, fig. 20 shows the placement of a fourth via 344, where the fourth via 344 is a via etched from the anode of the light emitting layer to the second source drain layer.

In some embodiments, as shown in fig. 10 and 11, the first active layer 207 includes an active pattern T1A of the driving transistor T1, the first light shielding layer 204 includes a light blocking pattern 204a and a connection line 204b, the light blocking pattern 204a is disposed corresponding to the active pattern T1A of the driving transistor T1, and the connection line 204b connects adjacent light blocking patterns 204a. The first shading layer comprises the light blocking pattern, so that the active pattern of the driving transistor can be shaded, the light is prevented from affecting the performance of the driving transistor, the performance of the driving transistor is improved, the connecting line is connected with the light blocking pattern, the first shading layer can form a net structure, and the uniformity of signals on the first shading layer is good.

Specifically, as shown in fig. 10, it can be seen that each light blocking pattern 204a is connected by a connecting line 204b around, so that the mesh structure design of the first light shielding layer can be realized, and the uniformity of the signals transmitted on the first light shielding layer can be improved.

Specifically, the first light shielding layer may input a high potential voltage, and may be specifically connected to a high potential power line.

In some embodiments, the second light shielding layer 202 is disposed between the first light shielding layer 204 and the substrate 201; or the second light shielding layer 202 is disposed between the first light shielding layer 204 and the first active layer 207; or the driving circuit layer 22 further includes a first gate layer 209, the first gate layer 209 is disposed between the first active layer 207 and the second active layer 212, and the second light shielding layer 202 is disposed between the first gate layer 209 and the first active layer 207; or the driving circuit layer 22 further includes a first gate layer 209, the first gate layer 209 is disposed between the first active layer 207 and the second active layer 212, and the second light shielding layer 202 is disposed between the first gate layer 209 and the second active layer 212.

Specifically, in order to avoid that the second light shielding layer affects the design of other film layers, the second light shielding layer may be separately disposed, and the second light shielding layer may be located between the substrate and the second active layer, and the specific disposition position is not limited, so that the second light shielding layer may be disposed between the first light shielding layer and the substrate, or between the first light shielding layer and the first active layer, or between the first active layer and the first gate layer, or between the first gate layer and the second active layer, respectively.

Specifically, for the difference of the selection of the material of the second light shielding layer, an insulating layer may be disposed between the second light shielding layer and other film layers, and also the second light shielding layer may be directly contacted with other film layers, for example, the second light shielding layer is made of a semiconductor material with light shielding characteristics, and the second light shielding layer may be separated from the first light shielding layer by the insulating layer, and may also be directly contacted with the first light shielding layer, where the second light shielding layer may improve the electrical properties of other film layers or may not affect the electrical properties of other film layers, and may be directly contacted with other film layers, which will not be described herein.

In some embodiments, the second light shielding layer is suspended, so that the second light shielding layer can be coupled with the second scanning signal line and the third scanning signal line, and therefore the second light shielding layer can be used as bottom gates of the compensation transistor and the first initialization transistor, and gate control capability of the compensation transistor and the first initialization transistor is improved.

Specifically, the above embodiment is described taking the example that the second light shielding layer is suspended, but the embodiment of the application is not limited thereto, and for example, the light shielding pattern may be grounded, or the light shielding pattern may be connected to the first light shielding layer.

In some embodiments, the first light-shielding layer and the second light-shielding layer are of different materials.

In some embodiments, the material of the second light shielding layer includes one of amorphous silicon and polysilicon. By making the material of the second light shielding layer amorphous silicon or polysilicon, the second light shielding layer has light shielding property, and the second light shielding layer is made of semiconductor material, and the second light shielding layer can be connected with signals, so that the property of the oxide semiconductor transistor can be improved.

Specifically, as shown in fig. 6, the driving circuit layer 22 further includes a first barrier layer 203, a second barrier layer 205, a buffer layer 206, a first gate insulating layer 208, a first interlayer insulating layer 211, a second gate insulating layer 213, a second interlayer insulating layer 215, a first planarizing layer 217, and a second planarizing layer 219.

Specifically, as shown in fig. 6, the display panel 2 further includes a light emitting layer 23, and the light emitting layer 23 includes a pixel electrode layer 221, a pixel defining layer 222, a light emitting material layer, a common electrode layer, and a support column 223.

Specifically, the first electrode of the transistor in the above embodiment is a source electrode, and the second electrode is a drain electrode; or the first electrode of the transistor in the above embodiment is a drain electrode and the second electrode is a source electrode.

Specifically, the first scanning signal line Pscan, the second scanning signal line Nscan1, the third scanning signal line Nscan, the fourth scanning signal line Pscan, and the emission control signal line EM may be respectively connected to different gate driving circuits, and specifically, five groups of gate driving circuits may be used to output signals to the first scanning signal line Pscan, the second scanning signal line Nscan1, the third scanning signal line Nscan, the fourth scanning signal line Pscan, and the emission control signal line EM, respectively, where the gate driving circuits connected to the first scanning signal line Pscan may be double-sided driving, and the other gate driving circuits may be single-sided driving.

Specifically, the material of the first active layer includes a silicon semiconductor material, which may be specifically low-temperature polysilicon.

Specifically, the material of the second active layer includes an oxide semiconductor material, specifically, may be a metal oxide semiconductor material, and more specifically, may be indium gallium zinc oxide.

Specifically, the material of the first light shielding layer includes a metal material.

Specifically, the driving transistor, the switching transistor, the first light emitting transistor, the second initializing transistor and the third initializing transistor are P-type transistors, and the first initializing transistor and the compensating transistor are N-type transistors.

Specifically, the foregoing embodiments respectively describe the pixel driving circuit, the film layer structure, the specific structure, the material and the electric potential of each layer in the display panel in detail, and it is understood that when there is no conflict between the embodiments, the embodiments may be combined, for example, the light shielding pattern is grounded, or the light shielding pattern is connected to the first light shielding layer, and the material of the second light shielding layer includes one of amorphous silicon and polysilicon.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The display panel and the display device provided by the embodiments of the present application are described in detail, and specific examples are applied to illustrate the principles and the embodiments of the present application, and the description of the above embodiments is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. A display panel, comprising:

A substrate;

2. The display panel of claim 1, wherein the driving circuit layer includes a pixel driving circuit including a switching transistor, a driving transistor, a compensation transistor, and a first initialization transistor, the switching transistor and the driving transistor being connected to a first node; an electrode of the compensation transistor, an electrode of the first initialization transistor and the driving transistor are connected to a second node, and another electrode of the compensation transistor and the driving transistor are connected to a third node;

The second active layer comprises an active pattern of the compensation transistor and an active pattern of the first initialization transistor, the second shading layer comprises a shading pattern which is identical to the active pattern of the compensation transistor and the active pattern of the first initialization transistor, and the shading pattern is correspondingly arranged with the active pattern of the compensation transistor and the active pattern of the first initialization transistor.

3. The display panel of claim 2, wherein the pixel driving circuit further comprises a storage capacitor, the second active layer further comprises a plate of the storage capacitor, the second light shielding layer further comprises an auxiliary pattern, the auxiliary pattern is identical to a pattern of a plate of the storage capacitor, and the auxiliary pattern is disposed corresponding to a plate of the storage capacitor.

4. The display panel according to claim 3, wherein a gate electrode of the switching transistor is connected to a first scan signal line, a first electrode of the switching transistor is connected to a data line, and a second electrode of the switching transistor and a first electrode of the driving transistor are connected to a first node; the grid electrode of the compensation transistor is connected with a second scanning signal line, the first electrode of the compensation transistor and the grid electrode of the driving transistor are connected to a second node, and the second electrode of the compensation transistor is connected with the second electrode of the driving transistor; the grid electrode of the first initializing transistor is connected with the third scanning signal line, the first electrode of the first initializing transistor is connected with the first initializing signal line, and the second electrode of the first initializing transistor and the grid electrode of the driving transistor are connected with the second node; the pixel driving circuit further includes:

A first light emitting control transistor, a gate electrode of which is connected with a light emitting control signal line, a first electrode of which is connected with a high potential power line, and a second electrode of which is connected with a first electrode of a driving transistor at a first node;

A second light emission control transistor, a gate of which is connected to a light emission control signal line, a first electrode of which is connected to a third node with a second electrode of the driving transistor;

a second initialization transistor, a gate of which is connected to a fourth scan signal line, a first electrode of which is connected to a second initialization signal line, and a second electrode of which is connected to a fourth node;

A third initialization transistor, a gate of which is connected to the fourth scan signal line, a first electrode of which is connected to a third initialization signal line, and a second electrode of which is connected to a first node with a first electrode of the driving transistor;

A storage capacitor, wherein one polar plate of the storage capacitor is connected with the high-potential power line, and the other polar plate of the storage capacitor and the grid electrode of the driving transistor are connected to a second node;

And one polar plate of the boost capacitor is connected with the first scanning signal line, and the other polar plate of the boost capacitor is connected with the second electrode of the first initializing transistor.

5. The display panel of claim 4, wherein the driving circuit layer further comprises a first gate layer, a second gate layer, a first source drain layer, and a second source drain layer, the first gate layer disposed between the first active layer and the second active layer, the second gate layer disposed between the second active layer and the first source drain layer, and the first source drain layer disposed between the second gate layer and the second source drain layer.

6. The display panel according to claim 5, wherein the first active layer includes an active pattern of a driving transistor, an active pattern of a switching transistor, an active pattern of a first light emission control transistor, an active pattern of a second initialization transistor, and an active pattern of a third initialization transistor, the active pattern of the driving transistor being disposed in a first direction, and the active pattern of the driving transistor being connected to the active pattern of the switching transistor, the active pattern of the first light emission control transistor, and the active pattern of the second light emission control transistor, the active pattern of the switching transistor and the active pattern of the first light emission control transistor being disposed in a second direction, the active pattern of the second light emission control transistor and the active pattern of the second initialization transistor being disposed in the second direction, and the active pattern of the second light emission control transistor and the active pattern of the second initialization transistor being connected to the active pattern of the second initialization transistor, the active pattern of the first light emission control transistor, the active pattern of the second light emission control transistor, and the active pattern of the first light emission control transistor being disposed in a second direction;

and an included angle between the first direction and the second direction is larger than 0 and smaller than or equal to 90 degrees.

7. The display panel according to claim 6, wherein the first gate layer includes a first initialization signal line, a first scan signal line, a light emission control signal line, a fourth scan signal line, a gate of the driving transistor, a gate of the switching transistor, a gate of the first light emission control transistor, a gate of the second initialization transistor, a gate of the third initialization transistor, and a first plate of a storage capacitor, the first initialization signal line, the first scan signal line, the first plate of the storage capacitor, the light emission control signal line, and the fourth scan signal line being sequentially arranged at intervals in the second direction.

8. The display panel of claim 7, wherein the second active layer includes an active pattern of a compensation transistor, an active pattern of a first initialization transistor, and a second plate of a storage capacitor, the active pattern of the compensation transistor is connected to the active pattern of the first initialization transistor, the second plate of the storage capacitor is disposed on one side of the active pattern of the compensation transistor in a first direction, and a via hole is disposed on the second plate of the storage capacitor.

9. The display panel according to claim 8, wherein the second gate layer includes a second scan signal line, a third initialization signal line, a gate of the compensation transistor, and a gate of the first initialization transistor, the third scan signal line, the second scan signal line, and the third initialization signal line being sequentially disposed along the second direction.

10. The display panel of claim 9, wherein the first source-drain layer includes a first data connection line, a first electrode of the switching transistor, a first electrode of the compensation transistor, a second electrode of the compensation transistor, a first electrode of the first initialization transistor, a second electrode of the first initialization transistor, a first electrode of the first light emitting control transistor, a second electrode of the first light emitting control transistor, a first electrode of the second light emitting control transistor, a second electrode of the second light emitting control transistor, a first electrode of the second initialization transistor, a second electrode of the second initialization transistor, a first electrode of the third initialization transistor, a second electrode of the third initialization transistor, and a second initialization signal line.

11. The display panel of claim 10, wherein the driving circuit layer includes a plurality of repeating units arranged in an array, each of the repeating units including two pixel driving circuits symmetrically arranged, and wherein within the repeating units, the second source-drain layer includes two data lines, an initialization signal connection line, two high-potential power supply lines, and a second data connection line, the two data lines are symmetrically arranged, and the two high-potential power supply lines are symmetrically arranged, and the initialization signal connection line and the second data connection line are symmetrically arranged.

12. The display panel of claim 1, wherein the first active layer includes an active pattern of a driving transistor, the first light shielding layer includes a light blocking pattern and a connection line, the light blocking pattern is disposed corresponding to the active pattern of the driving transistor, and the connection line connects adjacent light blocking patterns.

13. The display panel of claim 1, wherein the second light shielding layer is disposed between the first light shielding layer and the substrate; or the second light shielding layer is arranged between the first light shielding layer and the first active layer; or the driving circuit layer further comprises a first grid layer, the first grid layer is arranged between the first active layer and the second active layer, the second shading layer is arranged between the first grid layer and the first active layer, or the driving circuit layer further comprises a first grid layer, the first grid layer is arranged between the first active layer and the second active layer, and the second shading layer is arranged between the first grid layer and the second active layer.

14. The display panel of claim 1, wherein the second light shielding layer is suspended.

15. The display panel of claim 1, wherein the material of the second light shielding layer comprises one of amorphous silicon and polysilicon.

16. A display device comprising the display panel according to any one of claims 1 to 15.