CN118631607B

CN118631607B - CAN communication chip system, manufacturing method and electronic equipment

Info

Publication number: CN118631607B
Application number: CN202411045292.0A
Authority: CN
Inventors: 邹宇佳; 陈龙; 何东; 牟森林
Original assignee: Chengdu Srandway Technology Co ltd
Current assignee: Chengdu Srandway Technology Co ltd
Priority date: 2024-08-01
Filing date: 2024-08-01
Publication date: 2024-10-18
Anticipated expiration: 2044-08-01
Also published as: CN118631607A

Abstract

The embodiment of the application provides a CAN communication chip system, a manufacturing method and electronic equipment, and relates to the technical field of CAN communication. The CAN communication chip system comprises a processor, a CAN PHY module and an FPGA module; the FPGA module is used for being connected with the master controller through a controller bus, and the CAN PHY module is used for being connected with CAN communication equipment. The FPGA is not limited by the chip types and hardware fixation of the chip system, a DMA controller, a CAN MAC, a bus matrix, a bus controller, a DPRAM and the like CAN be realized in an IP Core of the FPGA module in a programming mode, the DMA controller and the CAN MAC cooperate to obviously improve the data transmission rate, and the IP Core realizes the substitution of a plurality of physical chips such as an AT96 bus logic chip, a dual-port RAM chip system, a CAN MAC chip system and the like, thereby reducing the supply requirement and cost of various hardware chips.

Description

CAN communication chip system, manufacturing method and electronic equipment

Technical Field

The application relates to the technical field of CAN (Controller Area Network ) communication, in particular to a CAN communication chip system, a manufacturing method and electronic equipment.

Background

In the field of CAN communication, CAN communication technologies currently on the market are supported by pure hardware chip systems.

For a pure hardware chip system, the internal composition is fixed, and the number of interfaces, the hardware chips connected by the interfaces, the types and the number of the internal hardware chips and the connection relation among the hardware chips are all fixed.

Because CAN communication systems are limited by these stationarities, CAN communication systems have low flexibility, and in particular, there are two factors:

(1) On one hand, the development period and the productivity of the chip are long from the new design of a hardware chip system to the completion of manufacturing, and the time cost is increased;

(2) On the other hand, the production cost of the chip, especially for the chip with higher performance requirement, the corresponding manufacturing equipment has scarcity, and larger production cost is required to be input.

Although the number and performance of CAN communication devices may vary from application scenario to application scenario, CAN communication systems cannot be flexibly adjusted accordingly. Under various application scenes and various requirements, only one CAN communication system CAN be adopted, the performance of the CAN communication system depends on hardware, the performance is not changed when the hardware is not changed, namely, the performance of the CAN communication system cannot be flexibly changed along with the application scenes, and finally, the data transmission and processing efficiency is greatly limited.

How to improve the flexibility of CAN communication and the data transmission processing efficiency is a technical problem to be solved by the application.

Disclosure of Invention

The application aims to provide a CAN communication chip system, a manufacturing method and electronic equipment, so as to improve the flexibility of CAN communication and the data transmission processing efficiency.

In order to achieve the above purpose, the following technical scheme is adopted in the embodiment of the application.

In a first aspect, an embodiment of the present application provides a CAN communication chip system, including a processor, a CAN PHY (CAN PHYSICAL LAYER, controller area network physical layer) module, and an FPGA (Field Programmable GATE ARRAY ) module; the FPGA module is used for being connected with the master controller through a controller bus;

The FPGA module comprises a DMA (Direct Memory Access ) controller and a CAN MAC (CAN MEDIA ACCESS Control), and the controller is used for local area network media access Control); the DMA controller and the CAN MAC are implemented in a programmed manner in the IP Core (Intellectual Property Core ) of the FPGA module; the number of the DMA controllers is greater than or equal to 1;

the first group of ports of the CAN MAC are in communication connection with the CAN PHY module, and the second group of ports of the CAN MAC, the DMA controller and the processor are in communication connection; the CAN PHY module is used for being connected with at least one CAN communication device;

When the master controller needs to send data to the CAN communication equipment, the FPGA module receives an instruction of the master controller through the controller bus, the instruction comprises a control instruction and first data, the FPGA module sends the control instruction to the processor, the processor reads the first data in the FPGA module according to the control instruction and sends the first data to the DMA controller, and the first data in the DMA controller is transmitted to the CAN communication equipment through the CAN MAC and the CAN PHY module;

When the CAN communication equipment needs to send data to the master controller, the CAN MAC receives second data of the CAN communication equipment through the CAN PHY module and stores the second data into the DMA controller, the processor reads the second data from the DMA controller, and the processor sends the second data to the master controller through the FPGA module and the controller bus.

Optionally, the DMA controller includes a receive FIFO (FIRST IN FIRST Out, first-in first-Out data buffer) and a transmit FIFO:

The receiving FIFO is used for storing data which comes from the CAN communication equipment and waits to be read by the processor;

The transmit FIFO is used to store data to be sent to the CAN communication device.

Optionally, the number of DMA controllers is 1, the number of receive FIFOs is 1, and the number of transmit FIFOs, the number of CAN MACs, the number of CAN PHYs in the CAN PHY module, and the number of CAN communication devices are the same.

Optionally, the number of CAN communication devices is greater than 1; the CAN communication equipment comprises first equipment and second equipment;

the CAN MAC comprises a first CAN MAC and a second CAN MAC;

the CAN PHY module comprises a first CAN PHY and a second CAN PHY;

The DMA controller communicates with the first device through the first CAN MAC and the first CAN PHY;

The DMA controller communicates with the second device through the second CAN MAC and the second CAN PHY;

When the second device needs to send information to the first device, the second CAN MAC receives third data of the second device through the second CAN PHY; the DMA controller receives the third data transmitted by the second CAN MAC and stores the third data into the receiving FIFO;

The processor reads the third data from the receiving FIFO and sends the third data to the DMA controller;

the DMA controller stores the third data into the transmission FIFO, transmits the third data in the transmission FIFO to the first CAN MAC, and transmits the third data to the first device through the first CAN PHY after the conversion of the first CAN MAC.

Optionally, the number of DMA controllers is greater than 1.

Optionally, the FPGA module further comprises a bus matrix; the bus matrix is realized in an IP Core of the FPGA module in a programming mode;

The second set of ports of the CAN MAC, the DMA controller and the processor are all in communication connection through the bus matrix.

Optionally, the FPGA module further comprises a bus controller and a DPRAM (Dual-Port Random Access Memory ); the bus controller and the DPRAM are realized in an IP Core of the FPGA module in a programming mode, the DPRAM has the function of realizing mutual exclusion lock in a semaphore mode, and the DPRAM allows a plurality of CPUs to realize mutual exclusion shared access in a semaphore token application mode so as to protect data security; the DPRAM is provided with a plurality of independent semaphores to improve the protection granularity;

the first group of ports of the bus controller are used for being connected with the master controller, the second group of ports of the bus controller are connected with the bus matrix, the third group of ports of the bus controller are connected with the first group of ports of the DPRAM, and the second group of ports of the DPRAM are connected with the bus matrix.

Optionally, the number of DPRAMs is greater than 1.

Optionally, the bus matrix is an AXI4 (Advanced eXtensible Interface 4, fourth generation version of advanced extensible interface) bus matrix;

the controller bus is an AT96 bus or ISA (Industry Standard Architecture ) bus.

In a second aspect, an embodiment of the present application provides a method for manufacturing a CAN communication chip system, configured to manufacture the CAN communication chip system of the first aspect, where the method for manufacturing the CAN communication chip system includes:

acquiring an unprogrammed CAN communication chip system, wherein the CAN communication chip system comprises a processor, a CAN PHY module and an FPGA module; the FPGA module is used for being connected with the master controller through a controller bus;

programming a DMA controller, a CAN MAC, a bus matrix, a bus controller and a DPRAM into an IP Core of an FPGA module, enabling a first group of ports of the CAN MAC to be in communication connection with the CAN PHY module, enabling a second group of ports of the CAN MAC, the DMA controller and the processor to be in communication connection through the bus matrix, enabling the first group of ports of the bus controller to be connected with the bus matrix, enabling the second group of ports of the bus controller to be connected with the bus matrix, enabling the third group of ports of the bus controller to be connected with the first group of ports of the DPRAM, and enabling the second group of ports of the DPRAM to be connected with the bus matrix.

In a third aspect, an embodiment of the present application provides an electronic device, including the CAN communication chip system of the first aspect.

Compared with the prior art, the application has the following beneficial effects:

The CAN communication chip system provided by the embodiment of the application utilizes the programmable characteristic of the FPGA, not only realizes the substitution of a plurality of physical chips such as an AT96 bus logic chip, a dual-port RAM chip system, a CAN MAC chip system and the like in the IP Core of the FPGA, but also reduces the supply requirement and cost of various hardware chips; and the DMA controller and the CAN MAC are realized in an IP Core of the FPGA module in a programming mode, wherein the quantity of the CAN MAC CAN be flexibly adjusted through programming, the method CAN adapt to the condition of different quantities of CAN communication equipment, and further, the DMA controller and the CAN MAC cooperate to improve the data transmission rate.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a conventional CAN communication board card architecture;

fig. 2 is a schematic diagram of a CAN communication chip system according to an embodiment of the present application;

fig. 3 is a schematic diagram of a CAN communication chip system with a bus matrix set in an FPGA module according to an embodiment of the present application;

Fig. 4 is a schematic diagram of a CAN communication chip system connected to three CAN communication devices according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a data flow between an ARM processor and a CAN bus through a DMA controller and a CAN MAC;

FIG. 6 is a schematic diagram of a flow of data for collaborative operation between a DMA controller and a CAN MAC according to an embodiment of the application;

Fig. 7 is a schematic diagram of a FIFO divided into different areas for storing data packets according to an embodiment of the application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application. The following embodiments and features of the embodiments may be combined with each other without conflict.

In the description of the present application, it should be noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The term "coupled" is to be interpreted broadly, as being a fixed connection, a removable connection, or an integral connection, for example; can be directly connected or indirectly connected through an intermediate medium.

Fig. 1 shows a conventional CAN communication board architecture, which is a pure hardware chip system, and the core part of the CAN communication board architecture is composed of an AT96 bus logic chip system, a dual-port RAM (Random Access Memory ) chip system, a CPLD (Complex Programmable Logic Device ) chip system, a CPU (MCU) chip system, a CAN MAC chip system and a CAN PHY chip system. The external connection equipment is a CAN PHY equipment and a master controller, and the CAN communication board is connected with the master controller through an AT96 bus or an ISA bus.

However, hardware such as the type and the number of chips forming the CAN communication board card are fixed, the flexibility of CAN communication is low, the problem that the CAN communication board card is easy to drop lines is easy to occur, and the data transmission and processing efficiency is low.

Referring to fig. 2, the embodiment of the present application provides a CAN communication chip system, which includes an FPGA module 10, a processor 20, and a CAN PHY module 30. The FPGA module 10 is configured to connect to the overall controller 50 via a controller bus. The overall controller 50 may be an external CPU.

As in fig. 2, the fpga module 10 includes a DMA controller and a CAN MAC. The first group of ports of the CAN MAC are in communication connection with the CAN PHY module 30, and the second group of ports of the CAN MAC, the DMA controller and the processor 20 are in communication connection; the CAN PHY module 30 is configured to connect with at least one CAN communication device 40.

When the overall controller 50 needs to send data to the CAN communication device 40, the FPGA module 10 receives an instruction of the overall controller 50 through the controller bus, the instruction includes a control instruction and first data, the FPGA module 10 sends the control instruction to the processor 20, the processor 20 reads the first data in the FPGA module 10 according to the control instruction and sends the first data to the DMA controller, and the first data in the DMA controller is transmitted to the CAN communication device 40 through the CAN MAC and CAN PHY module 30.

When the CAN communication device 40 needs to send data to the overall controller 50, the CAN MAC receives the second data of the CAN communication device 40 through the CAN PHY module 30 and stores the second data in the DMA controller, the processor 20 reads the second data from the DMA controller, and the processor 20 sends the second data to the overall controller 50 through the FPGA module 10 and the controller bus. The controller bus may be an AT96 bus or an ISA bus.

The CAN communication chip system CAN be realized by an integrated chip, and the integrated chip comprises an ARM processor and an FPGA. The ARM processor is used as the processor, the DMA controller and the CAN MAC are programmed into the IP Core of the FPGA module, a first group of ports of the CAN MAC are in communication connection with the CAN PHY module, and a second group of ports of the CAN MAC, the DMA controller and the processor are in communication connection.

The processor may employ ARM CortexTM-A53, which may support multiple types of external memory devices, including DDR (Double Data Rate), etc.

The CAN communication chip system utilizes the programmable characteristic of the FPGA to realize the DMA controller and the CAN MAC in an IP Core of the FPGA module in a programming mode, wherein the quantity of the CAN MAC CAN be flexibly adjusted through programming, and the system CAN adapt to the condition of different quantities of CAN communication equipment. Further, the DMA controller in cooperation with the CAN MAC may enable an increase in data transfer rate.

The DMA controller includes a plurality of FIFOs that can be divided into a receive FIFO and a transmit FIFO for different data transfer directions:

The specific FIFO is divided for executing different data transmission directions, so that the data transmission can be more orderly, and the data transmission error or packet loss is avoided. And under the condition that the communication rate of the CAN communication equipment, the communication rate of the processor and the communication rate of the overall controller are different, the problem that data in the same transmission direction occupies the FIFO and blocks data transmission in the other direction CAN be avoided.

As in fig. 3, a bus matrix may be programmed into the FPGA module 10 to facilitate communications between the CAN MAC, DMA controller and processor. The bus matrix may be an AXI4 bus matrix.

As in fig. 4, the bus controller and DPRAM may also be programmed in the FPGA module, and the number of DPRAMs may be greater than 1 (fig. 4 illustrates an embodiment comprising 2 DPRAMs, DPRAM1 and DPRAM 2), to achieve a higher communication rate. The first group of ports of the bus controller are used for being connected with the master controller, the second group of ports of the bus controller are connected with the bus matrix, the third group of ports of the bus controller are connected with the first group of ports of the DPRAM, and the second group of ports of the DPRAM are connected with the bus matrix.

The FIFO, CAN MAC, processor and DPRAM of the DMA controller transmit data through the bus matrix, so that the coupling problem caused by module interconnection CAN be avoided.

The DPRAM programmed by the FPGA module has a function of signal quantity communication (semaphore signaling between ports) among ports, the DPRAM has a function of realizing mutual exclusion lock in a signal quantity mode, the DPRAM allows a plurality of CPUs to realize mutual exclusion sharing access in a signal quantity token application mode so as to protect data safety, and the DPRAM has a plurality of independent signal quantities so as to improve protection granularity, specifically:

For example, DPRAM has 10kb total, 1kb uses one semaphore, i.e. 10 total semaphores. For 1KB, the master controller and the processor need to operate the 1KB at the same time, the operation can be read or write, then the operation can be realized in a mode of applying for the signal quantity, one party which is preoccupied by the 1KB in the master controller and the processor operates first, the other party waits first, even if both the master controller and the processor initiate the application at the same time, the DPRAM can also make an arbitration and only successfully acquire the signal quantity by one party, the two cannot conflict, after the whole 1KB operation is finished, the signal quantity which the 1KB belongs to is released immediately, and the other party continues to operate, so that the loss in time efficiency is reduced as much as possible while the safety and reliability of data are ensured.

The conventional dual-port RAM module in the FPGA chip does not have the mutual exclusion function realized by the semaphore, and when the overall controller and the processor need to operate on the 1KB at the same time, the 1KB may perform data transmission inconsistent with expectations.

The data transmission mode of the CAN communication chip system comprises at least three modes.

In one mode, the overall controller sends data to the CAN communication device, and the process is as follows:

when the master controller needs to send data to the CAN communication equipment, the master controller sends out an instruction, and the master controller receives the instruction through a controller bus interface; the instruction comprises a control instruction and first data;

The bus controller sends a control instruction to the processor, the bus controller sends first data to the DPRAM through the AXI4 bus matrix, and the DPRAM stores the first data;

the processor receives the control instruction, reads the first data from the DPRAM, and sends the first data to the DMA controller, and the DMA controller stores the first data in a transmission FIFO, such as FIFO1 in FIG. 4;

the DMA controller sends the first data of the FIFO1 to the CAN MAC through the AXI4 bus matrix, and sends the first data to the CAN communication equipment through the CAN PHY after the conversion of the CAN MAC.

The processor may store more data to other transmit FIFOs, after which the processor may serve other functional items, with subsequent data processing and transfer being performed by the DMA controller.

Each transmit FIFO may correspond to one CAN communication device, for example, 3 CAN communication devices in total in fig. 4, where the 3 CAN communication devices are a first device, a second device, and a third device, respectively, FIFO1 is used to store data transmitted to the first device, FIFO2 is used to store data transmitted to the second device, and FIFO3 is used to store data transmitted to the third device. The beneficial effect of this design lies in making CAN communication chip system CAN adapt to the CAN communication equipment of different transmission rates.

In the case where the first device, the second device, and the third device receive data at different rates, if the first device, the second device, and the third device share one transmit FIFO, one device with a faster rate will quickly occupy the transmit FIFO, and a device with a slower rate will have difficulty in obtaining data. And each CAN communication device is provided with a transmission FIFO, so that each CAN communication device CAN be ensured to receive data in time.

The number of CAN MAC and the number of CAN PHYs CAN be set to be larger than or equal to the number of CAN communication devices, so that each CAN communication device CAN transmit data through a corresponding CAN PHY and convert and process data signals through a corresponding CAN MAC. The number of DPRAMs may be greater than 1 and the number of dma controllers may be greater than 1. The increase in the number of DPRAM and DMA controllers can increase the efficiency of data transfer and processing.

In a second mode, data of the CAN communication device is sent to the master controller, and the process is as follows:

When the CAN communication equipment needs to send data to the master controller, the CAN MAC receives second data of the CAN communication equipment through the CAN PHY, the DMA controller receives the second data through the AXI4 bus matrix and transmits the second data to the receiving FIFO, and the receiving FIFO stores the second data; the processor reads the second data from the receiving FIFO and sends the second data to the DPRAM;

The bus controller reads the second data from the DPRAM through the AXI4 bus matrix and sends the second data to the overall controller through the controller bus.

In this process, the DMA controller encodes the second data, and the encoded information is used to identify the device from which the data came, so the processor can identify the device from which the data came based on the encoding. The data of the reception FIFOs are received by the processor in time, so that even if the rates at which the first device, the second device, and the third device receive the data are different, it is possible to receive the data by only one reception FIFO. As shown in fig. 4, FIFO1, FIFO2, and FIFO3 may be used as transmit FIFOs, and FIFO4 may be used as receive FIFOs.

In summary, the number of sending FIFOs is set to be equal to the number of the CAN communication devices, and the number of receiving FIFOs is 1, so that resources CAN be saved to the greatest extent and effective transmission of data CAN be guaranteed. In addition, transmission FIFOs of different capacities may be set according to characteristics of devices such as CAN communication devices, and reception FIFOs may be set to FIFOs of maximum capacities to ensure reception of data originating from the respective devices.

In the communication process of the first mode and the second mode, the DPRAM plays a role in carrying high-speed communication between the master controller and the processor.

In the communication process of the first mode and the second mode, the cooperation of the DMA controller and the CAN MAC plays a key role, fig. 5 shows a Data flow direction from the ARM processor to the CAN bus through the DMA controller and the CAN MAC, fig. 6 shows a Data flow direction from the DMA controller to the CAN MAC in cooperation operation, in which tx_data is Data sent by the master controller to the CAN communication device, and rx_data is Data received by the ARM processor from the CAN communication device; FIFO (X) represents the memory area of different tx_data, X is the partition number of FIFO (X), x=1, 2..n (X is a natural number of ≡1), FIFO (n+1) represents the memory area of rx_data, N represents the number of CAN communication devices, for example, when there are 3 CAN communication devices in total, the memory area of tx_data shares three areas of FIFO (1), FIFO (2) and FIFO (3), and the memory area of rx_data is FIFO (4). CAN MAC (X) represents a data transmission and processing functional module corresponding to FIFO (X) one by one; tx _x_Data_x/Rx_x_Data_x is a Data packet of tx_data/rx_data, one FIFO may store a plurality of CAN frames, 1 CAN frame contains a plurality of Data packets, as shown in fig. 7, FIFO (X) is divided into different areas Data (1), data (2) … Data (X), each area stores one Data packet, and CAN be sent to CAN MAC in units of Data packets.

As shown in fig. 5, the dma controller and the CAN MAC operate cooperatively to perform transmission and processing of instruction data in two lines:

The ARM CAN send Data Tx_Data to an AXI4 bus matrix through a BRIDGE switching BRIDGE, and then the Data is transmitted to a plurality of Data storage area FIFOs divided by a CAN DMA through the AXI4 bus matrix for Data storage, the ARM only performs the work of storing all Data Tx_Data to be sent to a sending FIFO, except that the FIFO (N+1) does not store the sending Data, and other FIFOs (X) CAN store the sending Data. After all data are stored in the FIFO functional area, the ARM CAN serve other functional items, and subsequent data processing and transmission are executed by the CAN DMA. The method is equivalent to the conventional work of ARM in the CAN communication data transmission and processing part of CAN DMA, so that ARM CAN be withdrawn to process other projects more effectively, and the data transmission and processing efficiency of the whole system is greatly improved.

After the CAN DMA receives all data transmitted by the ARM, the CAN DMA sequentially transmits instruction data to the CAN MAC through the AXI4 bus matrix according to the transmission sequence of the data storage area, the data is converted through the CAN MAC and then transmitted to the CAN PHY and the CAN bus, and finally a path I is formed.

And the second path is formed by transmitting the reply instruction data to the CAN PHY through the CAN bus, transmitting the reply instruction data to the CAN MAC through the CAN PHY to perform data conversion processing, and finally storing all the reply instruction data to the FIFO (N+1) through the AXI4 bus matrix through the CAN MAC, so that the ARM does not need to actively upload the reply instruction data to the ARM, and the ARM CAN call the reply data of the FIFO (N+1) at any time to perform processing according to the requirement of the ARM.

The first and second paths form a complete loop for transmission and processing of instruction data in the first and second modes.

In a third mode, one CAN communication device sends information to another CAN communication device, for example, the second device in fig. 4 sends information to the first device, and then the procedure is as follows:

the CAN MAC2 receives third data of the second device through the CAN PHY2, the DMA controller receives the third data through the AXI4 bus matrix and transmits the third data to a receiving FIFO (FIFO 4), and the FIFO4 stores the third data;

The DMA controller stores the third data in a transmission FIFO (for example, FIFO 1), transmits the third data in the transmission FIFO to CAN MAC1 through the AXI4 bus matrix, and transmits the third data to the first device through CAN PHY1 after being converted by CAN MAC 1.

Based on the above embodiment, the embodiment of the present application further provides a method for manufacturing a CAN communication chip system, which is used in the above CAN communication chip system, where the method for manufacturing a CAN communication chip system includes:

Further, the type and number of FIFOs in the DMA controller may be set, and the FIFOs may be divided into a receive FIFO and a transmit FIFO for different data transmission directions. The number of the sending FIFOs is set to be equal to the number of the CAN communication devices, and the number of the receiving FIFOs is set to be 1, so that resources CAN be saved to the maximum extent, and meanwhile effective transmission of data CAN be guaranteed.

Based on the above embodiment, the embodiment of the present application further provides an electronic device, where the electronic device includes the above CAN communication chip system, and the CAN communication chip system implements communication connection between the overall controller and the CAN communication device.

In general, the application provides a CAN communication chip system, a manufacturing method and electronic equipment, which CAN realize the following beneficial effects:

The method realizes domestic substitution of the CAN communication technology chip system by the mode of the technical scheme, and particularly, the flexible processor is formed by the FPGA module and the processor, has the advantages of simulating any CPU, being high in redundancy, high in reliability, inheritable and the like, is highly suitable for developed application software, and effectively solves the problems of cost, performance, reliability, stability and delivery of a special signal processing system chip; traditional CAN communication requires various hardware chip systems, such as an AT96 bus logic chip, a dual-port RAM chip system, a CPLD chip system, a CPU (MCU) chip system and a CAN MAC chip system, wherein various chip specifications depend on import, and the FPGA module and the processor CAN completely adopt domestic chip hardware; the imported chip system with the program has the advantages that the program code is not disclosed, the internal program is not traceable and can not be imitated, and the chip system is in a black box state, and the FPGA programming is traceable and reusable, can be used as a white box state, is convenient for subsequent further research and development, and has higher commercial value;

By utilizing the programmable characteristic of the FPGA, a DMA controller, a CAN MAC, a bus matrix, a bus controller, a DPRAM and the like are realized in an IP Core of the FPGA module in a programming manner, the IP Core of the FPGA module realizes the substitution of the AT96 bus logic chip, the dual-port RAM chip system, the CPLD chip system, the CPU (MCU) chip system, the CAN MAC chip system and other physical chips, the types of the chips are reduced, namely, the requirements and the dependence on the supply of various chips are reduced, and the purchase cost of the chips is reduced;

The FPGA is not limited by the chip type and hardware fixation of the chip system, the DMA controller is realized in an IP Core of the FPGA module in a programming mode, the DMA controller and the CAN MAC cooperate to improve the data transmission rate, improve the system flexibility and simultaneously improve the system performance, and the DMA controller and the CAN MAC cooperate to transmit and process instruction data, so that the conventional work of a processor in a CAN communication data transmission and processing part is shared, the processor is drawn out to process other projects more effectively, and the data transmission and processing efficiency of the whole system is greatly improved;

Under the actual application scene, under the transmission rate of 1Mbit/s, a single CAN channel CAN perform 8333 frame operation every second, and the whole system comprises a plurality of CAN channels, so that the frame operation of multiple of the single CAN channel CAN be simultaneously performed, the professional level of business application is completely reached, and the instruction data transmission and processing efficiency of an original chip system CAN only reach one tenth or lower of the scheme;

Along with the change of the number of CAN communication equipment in an application scene, the number of CAN MAC, DPRAM, DMA controllers and FIFO thereof CAN be adjusted in a programming adjustment mode, so that the research and development period is shortened.

The above-described embodiments of the apparatus and system are merely illustrative, and some or all of the modules may be selected according to actual needs to achieve the objectives of the present embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

The foregoing is only a preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present application should be covered by the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. The CAN communication chip system is characterized by comprising a processor, a CAN PHY module and an FPGA module; the FPGA module is used for being connected with the master controller through a controller bus;

The FPGA module comprises a DMA controller and a CAN MAC; the DMA controller and the CAN MAC are realized in an IP Core of the FPGA module in a programming mode; the number of the DMA controllers is greater than or equal to 1;

2. The CAN communication chip system of claim 1 wherein the DMA controller includes a receive FIFO and a transmit FIFO:

3. The CAN communication chip system of claim 2 wherein the number of DMA controllers is 1, the number of receive FIFOs is 1, the number of transmit FIFOs, the number of CAN MACs, the number of CAN PHYs in the CAN PHY module, and the number of CAN communication devices are the same.

4. The CAN communication chip system of claim 3, wherein the number of CAN communication devices is greater than 1; the CAN communication equipment comprises first equipment and second equipment;

the CAN MAC comprises a first CAN MAC and a second CAN MAC;

the CAN PHY module comprises a first CAN PHY and a second CAN PHY;

5. The CAN communication chip system of claim 1, wherein the FPGA module further comprises a bus matrix; the bus matrix is realized in an IP Core of the FPGA module in a programming mode;

6. The CAN communication chip system of claim 5, wherein the FPGA module further comprises a bus controller and a DPRAM; the bus controller and the DPRAM are realized in an IP Core of the FPGA module in a programming mode, the DPRAM has the function of realizing mutual exclusion lock in a semaphore mode, and the DPRAM allows a plurality of CPUs to realize mutual exclusion shared access in a semaphore token application mode so as to protect data security; the DPRAM is provided with a plurality of independent semaphores to improve the protection granularity;

7. The CAN communication chip system of claim 6, wherein the number of DPRAMs is greater than 1.

8. The CAN communication chip system of claim 5, wherein the bus matrix is an AXI4 bus matrix;

The controller bus is an AT96 bus or ISA bus.

9. A CAN communication chip system manufacturing method, characterized in that it is used for manufacturing the CAN communication chip system according to any one of claims 1 to 8, and the CAN communication chip system manufacturing method includes:

10. An electronic device characterized in that it comprises the CAN communication chip system of any one of claims 1 to 8.