CN118588690A

CN118588690A - Image sensor test structure and image sensor structure

Info

Publication number: CN118588690A
Application number: CN202411065837.4A
Authority: CN
Inventors: 关富升; 潘冬; 刘珩
Original assignee: Wuhan Xinxin Integrated Circuit Co ltd
Current assignee: Wuhan Xinxin Integrated Circuit Co ltd
Priority date: 2024-08-05
Filing date: 2024-08-05
Publication date: 2024-09-03

Abstract

The application provides an image sensor testing structure and an image sensor structure, wherein the image sensor testing structure comprises a substrate and a shielding layer, the substrate comprises a first surface and a second surface which are opposite to each other, and at least one photosensitive testing pixel positioned between the first surface and the second surface, and the first surface is used as a light incident surface; and the shielding layer is covered on the first surface to prevent external light signals from entering the photosensitive test pixels, so that dark field test is performed by using the photosensitive test pixels. The method and the device realize the testing of the number of white pixels in the image sensor in the manufacturing stage so as to adjust the manufacturing of the image sensor in advance, shorten the test cycle period, improve the efficiency, reduce the abnormal loss and improve the performance and the quality of the image sensor.

Description

Image sensor test structure and image sensor structure

Technical Field

The present application relates to the field of semiconductor manufacturing technology, and in particular, to an image sensor testing structure and an image sensor structure.

Background

In the CIS (CMOS Image Sensor, image sensor) field, photodiodes often generate free electrons due to defects or metal contamination, which can affect the optical signal reading under normal exposure. The number of pixels whose free electrons cause the read value of the optical signal to exceed a certain value in a dark field state (i.e., in the absence of light) is conventionally called the number of White Pixels (WP), which is an important index for evaluating the performance of CIS devices, directly reflects the imaging quality of the devices, and thus, reducing the number of White pixels is a long-term goal of the CIS device manufacturing process.

WP is one of the key parameters for evaluating the performance of CIS devices, and the WP of CIS devices needs to be obtained through a CP (Circuit Probing) test of a customer, but for a wafer factory, there is currently a lack of WP test means, which causes that research personnel in the wafer factory cannot obtain WP related data in time, and thus, immediate adjustment of CIS production cannot be performed. The correlation factors generated by WP are both charge and plasma dependent and hardly can be found to be abnormal in fabrication, so it is necessary to implement a WAT (WAFER ACCEPTANCE TEST ) test structure that can test WP in the wafer fab.

Disclosure of Invention

The application provides an image sensor testing structure and an image sensor structure, which provide a dark field environment to realize the test of the number of white pixels in an image sensor in a manufacturing stage.

In order to solve the above technical problems, the present application provides an image sensor testing structure, including: a substrate including first and second surfaces facing away from each other, and at least one photosensitive test pixel between the first and second surfaces, the first surface being a light incident surface; and the shielding layer is covered on the first surface to prevent external light signals from entering the photosensitive test pixels, so that dark field test is performed by using the photosensitive test pixels.

In some embodiments, the image sensor test structure further comprises: a first bottom dielectric layer disposed between the first surface and the barrier layer; and the first protective layer is used for covering the shielding layer and wrapping the shielding layer.

In some embodiments, the shielding layer comprises a metal shielding layer.

In some embodiments, each of the photosensitive test pixels includes: a first photosensitive device detecting the number of dark electrons of the photosensitive test pixels while performing the dark field test; and the first processing circuit is connected with the first photosensitive device and generates corresponding electric signals for output based on the quantity of dark electrons of the photosensitive test pixels.

In some embodiments, the first processing circuit includes a first pass transistor, a first reset transistor, a first source follower transistor, and a first gate transistor.

In some embodiments, the plurality of the photosensitive test pixels are arranged, and the first processing circuits of the plurality of the photosensitive test pixels are connected in parallel.

In order to solve the above technical problems, the present application further provides an image sensor structure, including:

A substrate comprising a first surface and a second surface opposite to each other, the substrate comprising at least one chip structure and a test structure, the test structure being an image sensor test structure as described in any one of the above.

In some embodiments, the chip structure includes a plurality of photosensitive pixels located between the first surface and the second surface; the chip structure further comprises a plurality of metal grids arranged on the first surface of the substrate, and a corresponding metal grid is arranged between every two adjacent photosensitive pixels.

In some embodiments, the chip structure further comprises: the second bottom dielectric layer is arranged on the first surface of the substrate in the area where the chip structure is located, and the metal grid is arranged on the second bottom dielectric layer; and the second protective layer covers the metal grid and the second bottom dielectric layer and wraps the metal grid.

In some embodiments, the metal grid of the chip structure and the shielding layer of the test structure are made of the same material and are made synchronously; the second bottom dielectric layer of the chip structure and the first bottom dielectric layer of the test structure are made of the same material and are manufactured synchronously; the second protective layer of the chip structure and the first protective layer of the test structure are made of the same material and are manufactured synchronously.

In some embodiments, each of the photosensitive pixels in the chip structure includes: a second photosensitive device for detecting the number of photoelectrons captured by the photosensitive pixels when performing exposure; and the second processing circuit is connected with the second photosensitive device and generates corresponding electric signals for output based on the quantity of photoelectrons captured by the photosensitive pixels.

In some embodiments, the photosensitive pixels and the photosensitive test pixels have the same structure and are made simultaneously.

In some embodiments, when the image sensor structure is diced to manufacture an image sensor chip, the dicing location is the location of the test structure, and the diced chip structure is used as the image sensor chip.

The application provides an image sensor testing structure, which comprises a substrate and a shielding layer, wherein the substrate comprises a first surface and a second surface which are opposite to each other, and at least one photosensitive testing pixel positioned between the first surface and the second surface, and the first surface is used as a light incident surface; and the shielding layer is covered on the first surface to prevent external light signals from entering the photosensitive test pixels, so that dark field test is performed by using the photosensitive test pixels. The method and the device realize the testing of the number of white pixels in the image sensor in the manufacturing stage so as to adjust the manufacturing of the image sensor in advance, shorten the test cycle period, improve the efficiency, reduce the abnormal loss and improve the performance and the quality of the image sensor.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:

FIG. 1 is a schematic diagram of an image sensor testing structure according to some embodiments of the present application;

FIG. 2 is a top view of an image sensor test structure according to some embodiments of the present application;

FIG. 3 is a schematic diagram of a first processing circuit according to some embodiments of the present application;

fig. 4 is a schematic structural diagram of an image sensor structure according to some embodiments of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first" and "second" in the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

All directional indications (such as up, down, left, right, front, rear, top, bottom … …) in embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the figures), and if the particular gesture changes, the directional indication changes accordingly.

Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

The term "about" as used herein, unless otherwise defined, is understood to mean a range of about + -15% of a certain value, in terms of the number of values or quantitative relationships.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

After the CIS (CMOS Image Sensor, image sensor) is manufactured, WAT (WAFER ACCEPTANCE TEST, wafer is tested) is performed, and the purpose of WAT is to detect the process condition of each wafer product by testing the electrical parameters of a specific test structure on the wafer, evaluate the quality and stability of the semiconductor manufacturing process, and determine whether the wafer product meets the electrical specification requirements of the process technology platform. However, the WAT is currently unable to test the WP (White Pixel) of the CIS, which results in that the wafer factory developers cannot obtain WP related data in time, and thus cannot make timely adjustments to the CIS fabrication.

In order to solve the above-mentioned technical problems, the present application provides an image sensor testing structure, referring to fig. 1, fig. 1 is a schematic structural diagram of an image sensor testing structure according to some embodiments of the present application. The image sensor test structure 100 includes a substrate 110 and a shielding layer 120. The substrate 110 includes a first surface 111, a second surface 112 opposite to each other, and at least one photosensitive test pixel 113 located between the first surface 111 and the second surface 112, the substrate 110 may be a single-layer structure or a stacked structure of more than two layers, the substrate 110 may be made of a semiconductor material or a non-semiconductor material, the substrate 110 is, for example, a wafer, a chip, or a stack of wafers and chips, and preferably, the substrate 110 is a pixel wafer. In some embodiments, the first surface 111 is a back surface of the substrate 110, and is also a light incident surface of the substrate 110, and in general, an external optical signal enters the photosensitive test pixel 113 from the first surface 111 and is converted into an electrical signal; the second surface 112 is a front surface of the substrate 110. The shielding layer 120 covers the first surface 111 to prevent external light signals from entering the photosensitive test pixels 113, and creates an absolute dark field test environment, so that dark field test is performed by using the photosensitive test pixels 113, dark current in the image sensor test structure 100 is tested, and thus the number of dark electrons in the image sensor test structure 100 is obtained, and further WP related data of the image sensor test structure 100 is obtained. The method realizes the testing of the number of white pixels in the image sensor to which the image sensor testing structure 100 belongs in the manufacturing stage so as to adjust the manufacturing of the image sensor in advance, shorten the testing cycle period, improve the efficiency, reduce the abnormal loss and improve the performance and the quality of the image sensor. In some embodiments, the image sensor test structure 100 may be used to perform WAT testing, and in other embodiments, the image sensor test structure 100 may be used for other tests requiring dark field conditions.

With continued reference to fig. 1, in some embodiments, each photosensitive test pixel 113 includes a first photosensitive device 1131 and a first processing circuit 1132. Wherein, when performing the dark field test, an external light signal cannot enter the photosensitive test pixel 113, the first photosensitive device 1131 may detect the number of dark electrons in the photosensitive test pixel 113 when performing the dark field test, and in some embodiments, the first photosensitive device 1131 is a photodiode. The first processing circuit 1132 is correspondingly connected to the first photosensitive device 1131, and is configured to receive and process the electrical signal in the first photosensitive device 1131, generate a corresponding electrical signal based on the number of dark electrons of the photosensitive test pixel 113 to output, and in some embodiments, the output electrical signal is a current value, and calculate the number of dark electrons converted into the photosensitive test pixel 113 based on the current value, thereby obtaining the number of white pixels in the image sensor test structure 100. Further, the image sensor test structure 100 and the image sensor to which the image sensor test structure 100 belongs are formed in the same process, and the number of white pixels of the image sensor to which the image sensor test structure 100 belongs can be represented according to the number of white pixels in the image sensor test structure 100. In some embodiments, the first photosensitive device 1131 and the first processing circuit 1132 may be configured in a stacked structure, that is, the first processing circuit 1132 is disposed on a side of the first photosensitive device 1131 away from the first surface 111, and disposed on a different substrate than the first photosensitive device 1131; in other embodiments, the first photosensitive device 1131 and the first processing circuit 1132 may be configured in a non-stacked structure, that is, the first processing circuit 1132 and the first photosensitive device 1131 are disposed on the same substrate.

Referring to fig. 1 and 3, fig. 3 is a schematic diagram of a first processing circuit according to some embodiments of the present application. In some embodiments, the light sensing test pixel 113 adopts a 4T (4 transistor) structure, that is, the first processing circuit 1132 includes a first transfer transistor 11321, a first reset transistor 11322, a first source follower transistor 11323, and a first gate transistor 11324. When the first transfer transistor 11321 is turned on, the corresponding electrical signal generated by detecting the number of dark electrons when the first photosensitive device 1131 performs the dark field test is transferred to the floating diffusion region (Floating Diffusing, FD) 11325 of the first transfer transistor 11321; the first source follower transistor 11323 generates a corresponding current based on the magnitude of the electrical signal on the floating diffusion region (Floating Diffusing, FD) of the first pass transistor 11321; the first gate transistor 11324 is used to control when the current generated by the first source follower transistor 11323 is output, i.e., to control the sequence of signal outputs of the photosensitive test pixel 113; the first reset transistor 11322 is configured to reset an electrical signal on a floating diffusion (Floating Diffusing, FD) of the first transfer transistor 11321. Specifically, the dark field test includes the following steps that dark electrons are accumulated in the first photosensitive device 1131, the first reset transistor 11322 and the first gating transistor 11324 are turned on for resetting in the first stage of the test, and an electric signal in a floating diffusion region (Floating Diffusing, FD) 11325 of the first transfer transistor 11321 is conducted, so that interference of a residual signal of the last test on the signal transmission is avoided; the second stage of the test turns off the first reset transistor 11322 to complete the reset; the third stage of the test turns on the first transfer transistor 11321, transferring the dark electron signal in the first photosensitive device 1131 into the floating diffusion region (Floating Diffusing, FD) 11325 of the first transfer transistor 11321; the fourth stage of the test turns off the first transfer transistor 11321, the first source follower transistor 11323 generates a corresponding current based on the magnitude of the electrical signal on the floating diffusion (Floating Diffusing, FD) of the first transfer transistor 11321, and turns on the first gate transistor 11324 to output the generated current; finally, all transistors are turned on for reset and the next test cycle is entered. In other embodiments, the light sensing test pixel 113 may also have a 3T (3 transistors) structure, a 5T (5 transistors) structure, or other structures, i.e. the first processing circuit 1132 may also have transistors in other combinations, so long as the processing of the electrical signal is not affected and the corresponding dark current value is output. In some embodiments, the first processing circuit 1132 also includes other devices such as a power supply.

With continued reference to fig. 1, the image sensor test structure 100 further includes a first bottom dielectric layer 130 and a first protective layer 140. The first bottom dielectric layer 130 is disposed between the first surface 111 and the shielding layer 120, and the image sensor test structure 100 further includes a first deep trench Isolation structure (DEEP TRENCH Isolation, DTI), where the first deep trench Isolation structure 131 enters the substrate 110 from the first surface 111 to isolate an optical signal entering an adjacent first photosensitive device 1131. In some embodiments, the material of the first bottom dielectric layer 130 is silicon oxide and/or silicon nitride. The first protection layer 140 covers and wraps the shielding layer 120, and plays a certain role in protecting the shielding layer 120. In some embodiments, the material of the first protective layer 140 may be formed of a material including at least one of silicon oxide, silicon nitride, and silicon oxynitride. The materials of the first bottom dielectric layer 130 and the first protection layer 140 are not limited in the present application.

With continued reference to fig. 1, in some embodiments, the barrier layer 120 includes a metal barrier layer 121, wherein the material of the metal barrier layer 121 may include at least one of elemental metal (e.g., copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, molybdenum, platinum, aluminum, hafnium, ruthenium, etc.) and an alloy (e.g., copper alloy or aluminum alloy, etc.). Thereby, external light is prevented from entering the photosensitive test pixels 113, and an absolute dark field environment is realized. The material of the shielding layer 120 is not limited by the present application.

Referring to fig. 1 and 2, fig. 2 is a top view of an image sensor testing structure according to some embodiments of the present application. In some embodiments, in order to improve the accuracy and stability of the test, reduce the signal interference generated in the test process, the number of the photosensitive test pixels 113 is multiple, and the first processing circuits 1132 of the photosensitive test pixels 113 are connected in parallel, so that the average value of the dark electron numbers of the photosensitive test pixels 113 is tested, and the overall situation of the photosensitive test pixels 113 can be reflected. Meanwhile, the plurality of photosensitive test pixels 113 are connected in parallel for testing, so that the measured signals can be amplified, and the reading is convenient. In some embodiments, the first processing circuits 1132 of the adjacent 4, 8 or 10 photosensitive test pixels 113 may be connected in parallel for testing according to different requirements and testing conditions, and the number of parallel first processing circuits 1132 is not limited herein. In other embodiments, each photosensitive test pixel 113 may be tested separately, and WP corresponding to the photosensitive test pixel 113 may be tested, thereby obtaining a more accurate test result.

In order to further solve the above technical problems, the present application further provides an image sensor structure. Referring to fig. 4, fig. 4 is a schematic structural diagram of an image sensor structure according to some embodiments of the present application. The image sensor structure 10 includes a substrate 110a, where the substrate 110a includes a first surface 111a and a second surface 112a opposite to each other, and in some embodiments, the first surface 111a is a back surface of the substrate 110a, and is also a light incident surface of the substrate 110a, that is, an external optical signal enters the substrate 110a from the first surface 111 a; the second surface 112a is a front surface of the substrate 110 a. Further, the substrate 110a includes at least one chip structure 200 and a test structure, where the test structure is any one of the image sensor test structures 100 described above.

With continued reference to fig. 4, image sensor structure 10 includes device regions and scribe line regions between adjacent device regions, and chip structure 200 is located in the device regions of image sensor structure 10. In some embodiments, the test structure is located in a scribe line region of the image sensor structure 10, and the chip structure 200 obtained after the image sensor structure 10 is diced along the scribe line region (scribe line y) is used as an image sensor chip, and the test structure, that is, the image sensor test structure 100, is used only for testing, for testing the performance of the image sensor structure 10, and for testing the process of manufacturing the image sensor structure 10. In other embodiments, the test structures are located in the device region of the image sensor structure 10.

With continued reference to fig. 4, the chip structure 200 includes a plurality of photosensitive pixels 210 located between the first surface 111a and the second surface 112 a. In some embodiments, each photosensitive pixel 210 includes a second photosensitive device 211 and a second processing circuit 212, respectively. Wherein the second photosensitive device 211 may convert the optical signal into an electrical signal, in some embodiments, the second photosensitive device 211 is a photodiode. The second processing circuit 212 is correspondingly connected to the second photosensitive device 211, and is configured to process the electrical signal converted by the second photosensitive device 211, generate a corresponding electrical signal based on the number of photoelectrons captured by the photosensitive pixel 210, and output the electrical signal, in some embodiments, the electrical signal is a current value, so as to be used for subsequent imaging display. In some embodiments, the second photosensitive device 211 and the second processing circuit 212 may be arranged in a stacked configuration; in other embodiments, the second photosensitive device 211 and the second processing circuit 212 may be configured in a non-stacked structure, which is the same as the first photosensitive device 1131 and the first processing circuit 1132 described above, and will not be described herein.

In some embodiments, the photosensitive pixel 210 adopts a 4T (4 transistor) structure, that is, the second processing circuit 212 includes a second transfer transistor 2121, a second reset transistor (not shown), a second source follower transistor (not shown), and a second gate transistor (not shown). The second processing circuit 212 has the same structure as the first processing circuit 1132 described above, and is not described here. The operation of the second processing circuit 212 may refer to the operation of a prior art 4T-APS (4T-advanced photo system) circuit, which is not described herein. In other embodiments, the photosensitive pixel 210 may also have a 3T (3 transistors) structure, a 5T (5 transistors) structure, or other structures, i.e. the second processing circuit 212 may also have other transistors in combination, so long as the processing of the electrical signal is not affected and the corresponding current value is output. In some embodiments, the second processing circuit 212 also includes other devices such as a power supply.

Further, the chip structure 200 further includes a plurality of metal grids 220 disposed on the first surface 111a of the substrate 110a, and a corresponding metal grid 220 is disposed between two adjacent photosensitive pixels 210, for isolating light from the outside, which irradiates the second photosensitive devices 211 in the photosensitive pixels 210 from the first surface 111 a. In some embodiments, the metal grid 220 of the chip structure 200 and the shielding layer 120 of the image sensor test structure 100 are made of the same material and are manufactured by at least partially simultaneous deposition processes, such as PVD (Physical Vapor Deposition ), CVD (Chemical Vapor Deposition, chemical vapor deposition), etc., to save the mask, process and cost, i.e., the structure of the shielding layer 120 is the same as the structure of the metal grid 220 before the photolithography is formed.

With continued reference to fig. 4, in some embodiments, the chip structure 200 further includes a second bottom dielectric layer 230 and a second protective layer 240. The second bottom dielectric layer 230 is disposed on the first surface 111a of the substrate 110a in the area where the chip structure 200 is located, and the metal grid 220 is disposed on the second bottom dielectric layer 230. Further, in some embodiments, the chip structure 200 includes a second deep trench isolation structure 231 entering the substrate 110a from the first surface 111a, and the second deep trench isolation structure 231 is used to isolate the optical signal entering the second photosensitive device 211. Also as shown in fig. 4, in some embodiments, the metal grid 220 and the second deep trench isolation structure 231 are disposed corresponding to a gap between the second photosensitive devices 211 of each photosensitive pixel 210. In some embodiments, the material of the second bottom dielectric layer 230 is silicon oxide and/or silicon nitride. The second protection layer 240 covers the metal grid 220 and the second bottom dielectric layer 230, and wraps the metal grid 220, and plays a role in protecting the metal grid 220 and the second bottom dielectric layer 230. In some embodiments, the material of the second protective layer 240 may be formed of a material including at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the second bottom dielectric layer 230 of the chip structure 200 and the first bottom dielectric layer 130 of the image sensor test structure 100 are made of the same material and are made using at least partially simultaneous photolithographic etching and/or deposition processes; in some embodiments, the second protective layer 240 of the chip structure 200 and the first protective layer 140 of the image sensor test structure 100 are made of the same material and are made using at least partially simultaneous photolithographic etching and/or deposition processes. Thus, the photomask, the process and the cost can be saved.

The image sensor test structure 100 provided by the application comprises a substrate 110 and a shielding layer 120. The substrate 110 includes a first surface 111, a second surface 112, and at least one photosensitive test pixel 113 disposed between the first surface 111 and the second surface 112, wherein the first surface 111 is used as a light incident surface of the substrate 110. The shielding layer 120 covers the first surface 111 to prevent external light signals from entering the photosensitive test pixels 113, and creates an absolute dark field test environment, thereby performing dark field test by using the photosensitive test pixels 113. Therefore, the number of white pixels in the image sensor to which the image sensor test structure 100 belongs is tested in the manufacturing stage, so that adjustment can be made on the manufacturing of the image sensor in advance, the test cycle period is shortened, the efficiency is improved, the abnormal loss is reduced, and the performance and the quality of the image sensor are improved.

The foregoing is only the embodiments of the present application, and therefore, the patent scope of the application is not limited thereto, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the application.

Claims

1. An image sensor test structure, comprising:

A substrate including first and second surfaces facing away from each other, and at least one photosensitive test pixel between the first and second surfaces, the first surface being a light incident surface;

And the shielding layer is covered on the first surface to prevent external light signals from entering the photosensitive test pixels, so that dark field test is performed by using the photosensitive test pixels.

2. The image sensor test structure of claim 1, further comprising:

a first bottom dielectric layer disposed between the first surface and the barrier layer;

and the first protective layer is used for covering the shielding layer and wrapping the shielding layer.

3. The image sensor test structure of claim 1, wherein the shielding layer comprises a metallic shielding layer.

4. The image sensor test structure of claim 1, wherein each of the photosensitive test pixels comprises:

A first photosensitive device detecting the number of dark electrons of the photosensitive test pixels while performing the dark field test;

And the first processing circuit is connected with the first photosensitive device and generates corresponding electric signals for output based on the quantity of dark electrons of the photosensitive test pixels.

5. The image sensor test structure of claim 4, wherein the first processing circuit comprises a first pass transistor, a first reset transistor, a first source follower transistor, and a first gate transistor.

6. The image sensor test structure of claim 4, wherein,

The first processing circuits of the plurality of photosensitive test pixels are connected in parallel.

7. An image sensor structure, comprising:

a substrate comprising a first surface and a second surface opposite to each other, said substrate comprising at least one chip structure and a test structure, said test structure being an image sensor test structure according to any one of claims 1-6.

8. The image sensor structure of claim 7, wherein,

The chip structure includes a plurality of photosensitive pixels located between the first surface and the second surface; the chip structure further comprises a plurality of metal grids arranged on the first surface of the substrate, and a corresponding metal grid is arranged between every two adjacent photosensitive pixels.

9. The image sensor structure of claim 8, wherein the chip structure further comprises:

The second bottom dielectric layer is arranged on the first surface of the substrate in the area where the chip structure is located, and the metal grid is arranged on the second bottom dielectric layer;

And the second protective layer covers the metal grid and the second bottom dielectric layer and wraps the metal grid.

10. The image sensor structure of claim 9, wherein the image sensor structure comprises,

The metal grating of the chip structure and the shielding layer of the test structure are made of the same material and are manufactured synchronously;

The second bottom dielectric layer of the chip structure and the first bottom dielectric layer of the test structure are made of the same material and are manufactured synchronously;

the second protective layer of the chip structure and the first protective layer of the test structure are made of the same material and are manufactured synchronously.

11. The image sensor structure of claim 8, wherein each of the photosensitive pixels in the chip structure comprises:

A second photosensitive device for detecting the number of photoelectrons captured by the photosensitive pixels when performing exposure;

And the second processing circuit is connected with the second photosensitive device and generates corresponding electric signals for output based on the quantity of photoelectrons captured by the photosensitive pixels.

12. The image sensor structure of claim 11, wherein the photosensitive pixels and the photosensitive test pixels have the same structure and are fabricated simultaneously.

13. The image sensor structure of claim 7, wherein,

When the image sensor structure is cut to manufacture an image sensor chip, the cutting position is the position of the test structure, and the cut chip structure is used as the image sensor chip.