CN118550736A - Communication method among multiple CPUs - Google Patents
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- CN118550736A CN118550736A CN202411027771.XA CN202411027771A CN118550736A CN 118550736 A CN118550736 A CN 118550736A CN 202411027771 A CN202411027771 A CN 202411027771A CN 118550736 A CN118550736 A CN 118550736A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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- G06F9/546—Message passing systems or structures, e.g. queues
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Abstract
The invention discloses a communication method among multiple CPUs, which comprises the steps of establishing communication channels between a strong computation CPU and a plurality of weak computation CPUs; setting a message format in which a strong computing power CPU communicates with a plurality of weak computing power CPUs; after the strong calculation CPU receives the message sent by the weak calculation CPU, decoding is carried out according to the message format to obtain a source CPU of the message, a destination CPU of the message and the message content; the strong calculation CPU determines a corresponding communication channel according to the destination CPU of the obtained message and forwards the message to the corresponding weak calculation CPU; the weak calculation CPU performs execution according to the message content after receiving the message, and returns the execution result to the strong calculation CPU; the powerful CPU sends the execution result to the source CPU of the message. The invention can realize the mutual communication among multiple CPUs, reduces the memory of the weak calculation CPU and reduces the design difficulty of hardware.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a communication method among multiple CPUs.
Background
The weak power CPUs do not support the establishment of multiple communication channels, and in the specific case that communication is required between the weak power CPUs, it is difficult to realize that all the CPUs can communicate with each other. Particularly, under the condition that a plurality of low-power CPUs exist in one piece of hardware, if all CPUs are required to communicate with each other, the design difficulty of the hardware is increased, and the memory requirement on the low-power CPUs is high.
The communication mode between the CPUs in the prior art can adopt various modes according to different physical connection and system architectures. The following are several common communication modes between CPUs and their advantages and disadvantages:
shared memory:
The advantages are that:
efficient data access: the CPU can directly read and write the shared memory, and the data access efficiency is high.
Low delay: the communication delay is low due to the direct access to the memory.
Disadvantages:
consistency management: a complex cache coherency protocol is required to ensure coherency of the shared data.
Scalability limitations: as the number of CPUs increases, the shared memory architecture may face scalability challenges.
Limitations: not suitable for distributed systems or massively parallel processing.
Message delivery:
The advantages are that:
Parallelism: each CPU can independently execute tasks without waiting for the results of other CPUs, suitable for highly parallel tasks.
Flexible: the method is suitable for different hardware layouts and scales, and can be easily expanded to larger systems.
Disadvantages:
Communication overhead: the creation, transmission and reception of messages all consume time and resources, i.e. overhead.
Complex programming models: the messaging model may require more complex programming skills and management than shared memory.
Internet or DMA (direct memory access):
The advantages are that:
low delay: the data transmission is directly carried out through hardware, and the system has better performance characteristics than a shared memory and a system bus.
Disadvantages:
depending on hardware support: hardware support between the CPU and the motherboard is required.
Complexity: the internet needs to be designed and implemented or precise configuration and management is required to ensure the correctness and consistency of data transmission.
Disclosure of Invention
In order to solve the above problems, the present invention proposes a communication method between multiple CPUs, which enables all CPUs to perform message communication, and has a simpler hardware design.
In order to achieve the above object, the present invention is realized by the following technical scheme:
The invention relates to a communication method among multiple CPUs, which comprises the following operations:
Establishing a communication channel between a strong computing power CPU and a plurality of weak computing power CPUs;
setting a message format in which a strong computing power CPU communicates with a plurality of weak computing power CPUs, wherein the message format comprises a source CPU of a message, namely SrcCPU, a destination CPU of the message, namely DstCPU, a main type, namely Mtype, a subtype, namely Stype, and message Content, namely Content;
After the strong calculation CPU receives the message sent by the weak calculation CPU through the communication channel, decoding is carried out according to the message format to obtain a source CPU of the message, a destination CPU of the message and the message content;
the strong calculation CPU determines a corresponding communication channel according to the destination CPU of the obtained message, and forwards the message to the corresponding weak calculation CPU through the corresponding communication channel;
The weak calculation power CPU executes the received message according to the content of the message decoded by the strong calculation power CPU, and returns the execution result to the strong calculation power CPU;
The powerful CPU sends the execution result to the source CPU of the message through the communication channel.
The invention further improves that: the establishing mode of the communication channel between the strong computing power CPU and the weak computing power CPU comprises an asynchronous transceiver, a serial peripheral interface and a direct memory access mode.
The invention further improves that: the source CPU and the destination CPU of the message in the message format are both three-bit binary codes, the main type is two-bit binary codes, and the sub type is eight-bit binary codes.
The invention further improves that: the message content is obtained by decoding a main type and a subtype in the message according to the powerful CPU, wherein the main type indicates the type of the message and comprises a control message, a management message and a data message, and the subtype indicates the specific function of the message.
The beneficial effects of the invention are as follows: for the hardware with the strong-power CPU and the plurality of weak-power CPUs, the invention can lead all CPUs to carry out message communication, has more convenient function realization and more concise hardware design, and does not need to establish communication connection between every two CPUs. The invention can reduce the memory of the weak calculation CPU.
Drawings
FIG. 1 is a schematic diagram of a communication mode among multiple CPUs in an embodiment of the invention;
FIG. 2 is a schematic flow chart of an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The embodiment is a method for realizing the mutual communication among all CPUs while reducing the design difficulty caused by hardware interleaving aiming at hardware with at least one strong-power CPU matched with a plurality of weak-power CPUs.
As shown in fig. 2, the communication method between multiple CPUs of the present embodiment includes the following operations:
step 1, establishing communication channels between a strong computing power CPU and a plurality of weak computing power CPUs;
Step 2, setting a message format in which a strong computing power CPU communicates with a plurality of weak computing power CPUs;
Step 3, after the strong calculation CPU receives the message sent by the weak calculation CPU through the communication channel, decoding is carried out according to the message format to obtain a source CPU of the message, a destination CPU of the message and message content;
Step 4, the strong calculation CPU determines a corresponding communication channel according to the destination CPU of the obtained message, and forwards the message to the corresponding weak calculation CPU through the corresponding communication channel; the weak calculation power CPU executes the received message according to the content of the message decoded by the strong calculation power CPU, and returns the execution result to the strong calculation power CPU;
And 5, the powerful CPU sends the execution result to the source CPU of the message through the communication channel.
In step 1, the communication channels between the strong power CPU and the weak power CPUs are shown in fig. 1, CPU3 is the strong power CPU, and CPU1, CPU2, CPU4 and CPU5 are all weak power CPUs, and only have the capability of establishing one communication channel. The CPU3 establishes four communication channels to communicate with the CPU1, the CPU2, the CPU4, and the CPU5, respectively, while the CPU3 has the capability of processing four channel messages. In practical application, although the four weak calculation CPUs have own functions, in some cases, the four weak calculation CPUs also need to communicate to have perfect functions, because the weak calculation CPUs only have one communication channel to be established, and cannot directly establish the communication channel, in the mode of fig. 1, each weak calculation CPU establishes the communication channel with the strong calculation CPU3, so that the strong calculation CPU3 communicates with all the weak calculation CPUs, processes the message according to the message content or forwards the message to the target weak calculation CPUs, and the communication function among each weak calculation CPU is realized. The communication between the powerful CPU and the weaker CPU may use UART (asynchronous transceiver), SPI (serial peripheral interface), DMA (direct memory access), etc., and may be determined according to the function of the chip in particular.
The message format in step 2 may be configured according to requirements, and table 1 is a specific message format:
table 1: message format
Wherein SrcCPU is a message source CPU, which is used to indicate the source of the message, is a three-bit binary code, and can be configured as required, for example: 1 denotes CPU1,2 denotes CPU2, CPU3,4 denotes CPU4, and 5 denotes CPU5.
DstCPU is a destination CPU of the message, indicating that the destination of the message is a three-bit binary code, and can be configured as needed, for example: 1 denotes CPU1,2 denotes CPU2, CPU3,4 denotes CPU4, and 5 denotes CPU5.
Mtype is a main type, is a two-bit binary code, and can be configured according to requirements, for example, including: 0 denotes a control message, 1 denotes a management message, and 2 denotes a data message.
Stype is a subtype, an eight bit binary code, which can be configured as desired, for example: 0 denotes that DDR maps to CPU1 memory, in which case message Content includes memory starting address, DDR address and length to be mapped;
1 represents the DDR mapping result, where success is represented as 0 and failure is represented as 1.
Where Mtype and Stype are classifications and distinctions of messages, mtype indicates what type of message is, e.g., messages may be classified as including control messages, management messages, data messages, etc., stype indicates the specific function of the message.
For the specific explanation with reference to fig. 1, it is assumed that after the powerful CPU3 receives a message, decoding is performed according to the message format as described in table 1, so as to obtain SrcCPU =1 and dstcu=3, which indicates that the message is sent by the powerful CPU3 to the powerful CPU3 by the powerful CPU1, and the powerful CPU3 continues to parse Mtype =2 and stype=0, so as to obtain that the CPU3 needs to perform memory mapping. The powerful CPU3 obtains specific messages from Mtype and Stype, that is, determines the format of the Content of the message, as above, mtype =2 and type=2, and then the Content of the message can solve the starting addresses CPU3_addr and DDR in the CPU3 memory and the length len to be mapped. CPU3 may map DDR memory ddr_addr onto CPU3_addr with a mapping length of cold. The above is one message communication of the weak power CPU1 and the strong power CPU 3.
If the strong force CPU3 receives a message, decodes the message according to the message format described in table 1 to obtain SrcCPU =1 and dstcpu=2, then the strong force CPU3 indicates that the message is sent to the weak force CPU2 by the weak force CPU1, continues to decode the message to obtain the message content, and sends the message to the weak force CPU2 from the message channels of the strong force CPU3 and the weak force CPU2, and after receiving the message, the weak force CPU2 completes the corresponding operation according to the message content obtained by decoding the strong force CPU3, so as to realize the communication between the weak force CPU1 and the weak force CPU 2.
For the strong calculation force CPU, a time-sharing system or a real-time system can be configured according to the installed system and the demand, and if the information of each weak calculation force CPU is equally important, the strong calculation force CPU is a time-sharing system, and all the information is processed in a time-sharing manner. If the message priorities of the weak calculation CPUs are different, configuring the strong calculation CPUs as a real-time system by setting message grades, so as to realize message priority division, and decoding the messages of the weak calculation CPUs by the strong calculation CPUs according to the message priorities.
For SSD hard disk using multiple CPUs, the linux master is a powerful CPU, the boot CPU is mainly hardware configuration, ftl CPU is mainly used for memory management, the EV71 CPU is used for AI, and audio and video processing is mainly performed. The linux is the most powerful in main calculation and functions, and is regarded as a powerful CPU, while the EV71 CPU, ftl CPU and boot CPU are regarded as a weak calculation CPU. If the EV71 CPU needs to adjust the transmission speed of the audio and video data, the EV71 CPU sends a message to the linux master through a communication channel between the EV71 CPU and the linux master, the linux master decodes the message after receiving the message to obtain a message source CPU (i.e., EV71 CPU), a message destination CPU (i.e., boot CPU) and a message content, and sends the message to the boot CPU, the boot CPU sets according to the message content, after the setting is successful, returns a success message to the linux master, and the linux master forwards the success message to the EV71 CPU, where the EV71 CPU knows that the transmission speed of the audio and video data has been adjusted successfully.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
While the foregoing is directed to embodiments of the present invention, other and further details of the invention may be had by the present invention, it should be understood that the foregoing description is merely illustrative of the present invention and that no limitations are intended to the scope of the invention, except insofar as modifications, equivalents, improvements or modifications are within the spirit and principles of the invention.
Claims (4)
1. A communication method among multiple CPUs is characterized in that: the method comprises the following operations:
Establishing a communication channel between a strong computing power CPU and a plurality of weak computing power CPUs;
setting a message format in which a strong computing power CPU communicates with a plurality of weak computing power CPUs, wherein the message format comprises a source CPU of a message, namely SrcCPU, a destination CPU of the message, namely DstCPU, a main type, namely Mtype, a subtype, namely Stype, and message Content, namely Content;
After the strong calculation CPU receives the message sent by the weak calculation CPU through the communication channel, decoding is carried out according to the message format to obtain a source CPU of the message, a destination CPU of the message and the message content;
the strong calculation CPU determines a corresponding communication channel according to the destination CPU of the obtained message, and forwards the message to the corresponding weak calculation CPU through the corresponding communication channel;
The weak calculation power CPU executes the received message according to the content of the message decoded by the strong calculation power CPU, and returns the execution result to the strong calculation power CPU;
The powerful CPU sends the execution result to the source CPU of the message through the communication channel.
2. The method for communication between multiple CPUs according to claim 1, wherein: the establishing mode of the communication channel between the strong computing power CPU and the weak computing power CPU comprises an asynchronous transceiver, a serial peripheral interface and a direct memory access mode.
3. The method for communication between multiple CPUs according to claim 1, wherein: the source CPU and the destination CPU of the message in the message format are both three-bit binary codes, the main type is two-bit binary codes, and the sub type is eight-bit binary codes.
4. The method for communication between multiple CPUs according to claim 1, wherein: the message content is obtained by decoding a main type and a subtype in the message according to a powerful CPU, wherein the main type indicates the type of the message and comprises a control message, a management message and a data message, and the subtype indicates the specific function of the message.
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| CN103513965A (en) * | 2013-10-29 | 2014-01-15 | 浪潮电子信息产业股份有限公司 | Method for extracting parallel AdaBoost characteristics of heterogeneous system |
| CN112910763A (en) * | 2021-02-09 | 2021-06-04 | 恒安嘉新（北京）科技股份公司 | Method, device, equipment and medium for providing real-time data interface service |
| CN115878550A (en) * | 2021-09-29 | 2023-03-31 | 华为技术有限公司 | Data processing method, chip, equipment and system |
| CN116208565A (en) * | 2021-11-30 | 2023-06-02 | 华为技术有限公司 | Data transmission method, optical transmitting device and optical receiving device |
| CN118055066A (en) * | 2022-11-09 | 2024-05-17 | 中兴通讯股份有限公司 | Computing power resource notification method, computing power flow processing method, communication equipment and medium |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103513965A (en) * | 2013-10-29 | 2014-01-15 | 浪潮电子信息产业股份有限公司 | Method for extracting parallel AdaBoost characteristics of heterogeneous system |
| CN112910763A (en) * | 2021-02-09 | 2021-06-04 | 恒安嘉新（北京）科技股份公司 | Method, device, equipment and medium for providing real-time data interface service |
| CN115878550A (en) * | 2021-09-29 | 2023-03-31 | 华为技术有限公司 | Data processing method, chip, equipment and system |
| CN116208565A (en) * | 2021-11-30 | 2023-06-02 | 华为技术有限公司 | Data transmission method, optical transmitting device and optical receiving device |
| CN118055066A (en) * | 2022-11-09 | 2024-05-17 | 中兴通讯股份有限公司 | Computing power resource notification method, computing power flow processing method, communication equipment and medium |
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