Nothing Special   »   [go: up one dir, main page]

CN118555830A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
CN118555830A
CN118555830A CN202410832178.6A CN202410832178A CN118555830A CN 118555830 A CN118555830 A CN 118555830A CN 202410832178 A CN202410832178 A CN 202410832178A CN 118555830 A CN118555830 A CN 118555830A
Authority
CN
China
Prior art keywords
hard mask
dielectric layer
storage node
node contact
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202410832178.6A
Other languages
Chinese (zh)
Inventor
冯立伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujian Jinhua Integrated Circuit Co Ltd
Original Assignee
Fujian Jinhua Integrated Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujian Jinhua Integrated Circuit Co Ltd filed Critical Fujian Jinhua Integrated Circuit Co Ltd
Priority to CN202410832178.6A priority Critical patent/CN118555830A/en
Publication of CN118555830A publication Critical patent/CN118555830A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device includes: a substrate including a cell region and a peripheral region; a plurality of bit lines on the cell region; a plurality of gate structures located on the peripheral region; a first dielectric layer located between adjacent gate structures; a plurality of connectors within the first dielectric layer connected to the substrate; a plurality of storage node contact structures located between adjacent bit lines; a plurality of capacitor structures located on the storage node contact structures; a hard mask layer covering the top surface of the connection member; and a second dielectric layer including a first portion over the hard mask layer and a second portion over the storage node contact structure, the apex of the first portion of the second dielectric layer being at a different level than the apex of the second portion. By adopting the semiconductor device, the technical effect of improving the performance of the semiconductor device on the basis of not increasing the process time and the process cost is realized.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
Dynamic Random Access Memory (DRAM) is a type of volatile memory. DRAM devices typically include a memory region comprised of an array of memory cells, and a peripheral region comprised of control circuitry. The control circuit in the peripheral region may address each memory cell in the memory region by crossing a plurality of column word lines (word lines) and a plurality of row bit lines (bit lines) of the memory region and electrically connect with each memory cell to perform reading, writing or erasing of data.
In the current semiconductor manufacturing, the semiconductor devices of the memory cells and the peripheral circuits are formed simultaneously by the same manufacturing process, which generally includes a patterning process, and how to form the memory cells and the peripheral circuits by multiple processes such as the patterning process while ensuring the device performance is a problem to be solved in the prior art.
Disclosure of Invention
The application provides a semiconductor device and a preparation method thereof, which are used for solving the problem of ensuring the performance of the device when a memory unit and a peripheral circuit are formed through a patterning process and other multiple processes in the related art.
According to an aspect of the present application, there is provided a semiconductor device including: a substrate including a cell region and a peripheral region; a plurality of bit lines on the cell region; a plurality of gate structures located on the peripheral region; a first dielectric layer located between adjacent gate structures; a plurality of connectors within the first dielectric layer connected to the substrate; a plurality of storage node contact structures located between adjacent bit lines; a plurality of capacitor structures located on the storage node contact structures; a hard mask layer covering the top surface of the connection member; and a second dielectric layer including a first portion over the hard mask layer and a second portion over the storage node contact structure, the apex of the first portion of the second dielectric layer being at a different level than the apex of the second portion.
According to another aspect of the present application, there is provided a semiconductor device comprising: a substrate including a cell region and a peripheral region; a plurality of bit lines on the cell region; a plurality of gate structures located on the peripheral region; a first dielectric layer located between adjacent gate structures; a plurality of connectors within the first dielectric layer connected to the substrate; a plurality of storage node contact structures located between adjacent bit lines; a plurality of capacitor structures located on the storage node contact structures; a hard mask layer covering the top surface of the connection member; a second dielectric layer covers the hard mask layer and directly contacts the top surface of the connection and the sidewalls of the capacitor structure.
Optionally, the apex of the first portion of the second dielectric layer is higher than the apex of the second portion.
Optionally, the hard mask layer has a vertex that is higher than a vertex of the second portion of the second dielectric layer.
Optionally, the hard mask layer includes a first sub-mask covering the connection and a second sub-mask covering the storage node contact structure, the first sub-mask having a vertex higher than a vertex of the second sub-mask.
Optionally, the hard mask layer is completely isolated from the top surface of the storage node contact structure.
Optionally, the semiconductor device further includes a third dielectric layer over the gate structure and between adjacent connectors, an apex of the third dielectric layer being lower than an apex of the hard mask layer.
Optionally, the hard mask layer directly contacts the top surface of the connection and the sidewalls of the capacitor structure.
According to another aspect of the present application, there is also provided a method of manufacturing a semiconductor device, comprising: providing a substrate, wherein the substrate comprises a cell area and a peripheral area: forming a plurality of bit lines on the cell region, forming a plurality of gate structures on the peripheral region, and forming a first dielectric layer between adjacent gate structures; forming a plurality of connectors within the first dielectric layer; forming a plurality of storage node contact structures between adjacent bit lines; forming a hard mask layer covering the top surface of the connecting piece; and forming a second dielectric layer and a capacitor structure, wherein the capacitor structure is positioned on the storage node contact structure, the second dielectric layer covers the hard mask layer, and the second dielectric layer comprises a first part positioned above the hard mask layer and a second part positioned above the storage node contact structure, and the vertexes of the first part and the vertexes of the second part of the second dielectric layer are positioned at different levels.
Optionally, the preparation method further comprises: forming a conductive material covering the bit line and the gate structure; forming a patterned hard mask on the surface of the conductive material; partially removing the conductive material to form an electrical connection and a storage node contact structure; the patterned hard mask over the storage node contact structure is completely removed, forming a hard mask layer covering the top surface of the connection.
Optionally, the preparation method further comprises: forming a conductive material covering the bit line and the gate structure; forming a patterned hard mask on the surface of the conductive material; partially removing the conductive material to form an electrical connection and a storage node contact structure; the patterned hard mask is partially removed to form a first sub-mask covering the connection and a second sub-mask covering the storage node contact structure, the first sub-mask having vertices higher than the vertices of the second sub-mask.
Optionally, the preparation method further comprises: a third dielectric layer is formed such that the third dielectric layer is located over the gate structure and between adjacent connectors.
By the application, the semiconductor device comprises a substrate, a bit line, a gate structure, a first dielectric layer, a connecting piece, a hard mask layer, a second dielectric layer, a storage node contact structure and a capacitor structure, wherein the hard mask layer covers the top surface of the connecting piece, the second dielectric layer comprises a first part positioned above the hard mask layer and a second part positioned above the storage node contact structure, the peaks of the first part and the peaks of the second part of the second dielectric layer are positioned at different levels, the hard mask layer is formed by residual hard mask material in the process of forming the connecting piece, the hard mask material is deposited in the memory area and the surrounding area at the same time, grooves are formed in the peripheral area through a patterning process and an etching process so as to separate a plurality of connecting pieces, the grooves are also formed in the memory area by synchronous etching, the depth of the grooves formed in the memory area is larger than that of the grooves in the peripheral area due to the difference of materials, and if the depth of the grooves in the memory area is larger, the grooves can be over-etched to the bit lines to cause short circuit.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
Fig. 1 is a schematic partial cross-sectional view of a semiconductor device provided in accordance with an embodiment of the present application;
fig. 2 is a schematic cross-sectional view of a first connection member and a second connection member in a semiconductor device according to an embodiment of the present application;
Fig. 3 is a schematic partial cross-sectional view of another semiconductor device provided in accordance with an embodiment of the present application;
Fig. 4 is a process flow diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application;
Fig. 5 is a schematic partial cross-sectional view of a substrate after forming a bit line and a gate structure on the substrate in a method for manufacturing a semiconductor device according to an embodiment of the present application;
FIG. 6 is a schematic partial cross-sectional view of the substrate after forming a contact hole in the gate structure shown in FIG. 5;
FIG. 7 is a schematic partial cross-sectional view of the substrate shown in FIG. 6 after depositing a conductive material and a masking material thereon;
FIG. 8 is a schematic partial cross-sectional view of the substrate after etching the mask material shown in FIG. 7 to form the link and hard mask layer;
FIG. 9 is a schematic partial cross-sectional view of the substrate after covering the dielectric material on the connector shown in FIG. 8;
FIG. 10 is a schematic partial cross-sectional view of the substrate after etching the dielectric material shown in FIG. 9;
fig. 11 is a schematic partial cross-sectional view of the substrate after forming the second dielectric layer and the third dielectric layer from the dielectric material shown in fig. 10.
Wherein the above figures include the following reference numerals:
10. A substrate; 210. a gate structure; 211. a first semiconductor layer; 212. a first metal layer; 213. a first patterned mask; 220. a bit line; 221. a second semiconductor layer; 222. a second metal layer; 223. a second patterned mask; 30. a barrier layer; 410. a first side wall; 411. a first insulating layer; 412. a second insulating layer; 413. a third insulating layer; 420. a second side wall; 421. a fourth insulating layer; 422. a fifth insulating layer; 423. a sixth insulating layer; 50. shallow trench isolation structures; 610. a contact opening; 620. a storage node contact opening; 70. a semiconductor structure; 80. a connecting piece; 801. a first connector; 802. a second connector; 810. a storage node contact structure; 820. a contact pad; 821. a conductive material; 811. a first connection portion; 812. a second connecting portion; 90. a hard mask layer; 910. a mask material; 100. a first dielectric layer; 101. a dielectric material; 120. a second dielectric layer; 130. a capacitor structure; 140. a support layer; 150. and (5) conducting wires.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
According to an embodiment of the present application, there is provided a semiconductor device, and fig. 1 is a schematic structural view of the semiconductor device according to the embodiment of the present application.
As shown in fig. 1, the semiconductor device includes a substrate 10, a plurality of bit lines 220, a plurality of gate structures 210, a first dielectric layer 100, a plurality of connectors 80, a plurality of storage node contact structures 810, a plurality of capacitor structures 130, a hard mask layer 90, and a second dielectric layer 120, wherein: the substrate 10 includes a cell region and a peripheral region; a plurality of bit lines 220 are located on the cell region; a plurality of gate structures 210 are located on the peripheral region; the first dielectric layer 100 is located between adjacent gate structures 210; a plurality of connectors 80 are located within the first dielectric layer 100 and connected to the substrate; the plurality of storage node contact structures 810 are located between adjacent bit lines 220; a plurality of capacitive structures 130 are located on the storage node contact structure 810; the hard mask layer 90 covers the top surface of the connection member; the second dielectric layer 120 includes a first portion over the hard mask layer 90 and a second portion over the storage node contact structure 810, with the vertices of the first portion and the vertices of the second portion of the second dielectric layer 120 being at different levels.
In the semiconductor device of the embodiment of the present application, as shown in fig. 1, since the hard mask layer 90 covers the top surface of the connection member 80, and the second dielectric layer includes a first portion located above the hard mask layer 90 and a second portion located above the storage node contact structure, the peaks of the first portion and the peaks of the second portion of the second dielectric layer 120 are located at different levels, the hard mask layer 90 is formed by residual hard mask material during the formation of the connection member 80, and during the formation of the connection member 80, the hard mask material is simultaneously deposited in the memory region and the peripheral region, and grooves are formed in the peripheral region by patterning and etching processes to space out the plurality of connection members 80, and the depth of the grooves formed in the memory region is larger than the depth of the grooves in the peripheral region due to the difference of the material.
In addition, the hard mask layer 90 may be formed by patterning the storage node contact structure 810 and the connection member 80 while the hard mask material remains on the top surface of the connection member 80 during the fabrication process of the semiconductor device, so that no additional process steps are required, and the technical effect of improving the performance of the semiconductor device without increasing the process time and the process cost is achieved.
In the semiconductor device according to the embodiment of the present application, as shown in fig. 1, the semiconductor structure includes a substrate 10, and a peripheral area B and a memory area a are defined on the substrate 10.
The substrate 10 may have Shallow Trench Isolation (STI) 50 formed therein to define a plurality of active regions (active regions) of memory cells in the memory region a of the substrate 10 and a plurality of active regions of semiconductor devices in the peripheral region B of the substrate 10. The substrate 10 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, and embodiments of the present application are not particularly limited.
The peripheral area B may be provided with peripheral circuits for controlling operations and input/output of memory cells in the memory area a, for example, a driver, a buffer, an amplifier, and a decoder, and may further include circuits for repairing abnormal memory cells, for example, fuse circuits, and embodiments of the present application are not limited in detail. Memory area a may be provided with an array of memory cells, such as DRAM cells. According to an embodiment of the present application, the semiconductor devices of the peripheral circuits in the peripheral region B and the DRAM cells in the memory region a are prepared on the substrate 10 by the same manufacturing process.
In the semiconductor device according to the embodiment of the application, as shown in fig. 1, the plurality of bit lines 220 may be arranged on the memory area a at intervals along the x direction, the plurality of gate structures 210 may be arranged on the peripheral area B at intervals along the x direction, and the plurality of gate structures 210 formed on the peripheral area B and the plurality of bit lines 220 formed on the memory area a may be prepared by the same process steps. Illustratively, a semiconductor material layer, a metal material layer, and a hard mask material layer are sequentially formed on the peripheral region B and the memory region a of the substrate 10, and a patterning process is performed on the hard mask material layer to obtain a patterned mask, and then the metal material layer and the semiconductor material layer are sequentially etched with the patterned mask as a mask to transfer the pattern of the patterned hard mask material into the semiconductor material layer, thereby obtaining the gate structure 210 and the bit line 220.
The gate structure 210 may include a first semiconductor layer 211, a first metal layer 212, and a first patterning mask 213 sequentially stacked in a direction away from the substrate 10, and the bit line 220 may include a second semiconductor layer 221, a second metal layer 222, and a second patterning mask 223 sequentially stacked in a direction away from the substrate 10, respectively, wherein materials of the first semiconductor layer 211 and the second semiconductor layer 221 may include polysilicon; the materials of the first and second metal layers 212 and 222 may include low resistivity metal materials such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium aluminum alloy (TiAl), etc.; the materials of the first and second patterned masks 213 and 223 may include any one or more of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN), and may further include other dielectric materials, and the embodiments of the present application are not particularly limited with respect to the above material types.
It should be noted that a gate oxide layer (not shown) may be further disposed between the substrate 10 and the first semiconductor layer 211 of the gate structure 210, and the gate oxide layer may be made of silicon oxide (SiO 2).
In the semiconductor device according to the embodiment of the present application, as shown in fig. 1, the first dielectric layer 100 is located between the adjacent gate structures 210, and the semiconductor device according to the embodiment of the present application may further include a barrier layer 30 located on the gate structures 210 and the first dielectric layer 100. The materials of the first dielectric layer 100 and the barrier layer 30 may include any one or more of silicon oxide (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN), and may further include other kinds of dielectric materials, and embodiments of the present application are not limited in detail.
As shown in fig. 1, the semiconductor device according to the embodiment of the present application may further include first sidewalls 410 located at both sides of the gate structure 210. The first sidewall 410 includes a first insulating layer 411, a second insulating layer 412, and a third insulating layer 413 sequentially covering sidewalls of the gate structure 210 from inside to outside.
As shown in fig. 1, the semiconductor device according to the embodiment of the present application may further include second sidewalls 420 located at both sides of the bit line 220. The second sidewall 420 includes a fourth insulating layer 421, a fifth insulating layer 422, and a sixth insulating layer 423, which cover the sidewalls of the bit line 220 and the barrier layer 30 in this order from the inside to the outside.
The first sidewall 410 and the second sidewall 420 may be manufactured by the same process steps, and the materials of the insulating layers in the first sidewall 410 and the second sidewall 420 may be conventional insulating materials in the prior art, such as silicon oxide (SiO 2), which is not particularly limited in the embodiment of the present application.
In the semiconductor device according to the embodiment of the present application, as shown in fig. 2, the connection member 80 may include a plurality of first connection members 801 and at least one second connection member 802, each connection member 80 includes a first connection portion 811 and a second connection portion 812, the first connection portion 811 is located between at least one gate structure 210 and an adjacent first dielectric layer 100, the second connection portion 812 is located on a side of the first connection portion 811 facing away from the substrate 10, and a surface of the second connection portion 812 facing away from the first connection portion 811 in the second connection member 802 is a first surface. The material of the connector 80 may include a metal, such as tungsten (W).
In the semiconductor device according to the embodiment of the present application, as shown in fig. 1, a plurality of storage node contact structures 810 are located between adjacent bit lines 220, the storage node contact structures 810 include a semiconductor structure 70 located between the adjacent bit lines 220 and a contact pad 820 located on the semiconductor structure 70, the material of the semiconductor structure 70 may include polysilicon, and the material of the contact pad 820 may include metal, such as tungsten (W). Illustratively, semiconductor structure 70 fills the bottom of storage node contact openings 620 between adjacent bit lines 220, a portion of contact pads 820 fills above semiconductor structure 70, and another portion of contact pads 820 is located outside of the storage node contact openings, covering a portion of the bit line top surface.
In the semiconductor device according to the embodiment of the present application, as shown in fig. 1, the second dielectric layer 120 includes a first portion located above the hard mask layer 90 and a second portion located above the storage node contact structure 810, and the top points of the first portion and the second portion of the second dielectric layer 120 are located at different levels, where the hard mask layer 90 may be formed by removing the hard mask material on the top surface of the storage node contact structure 810 during the patterning process in the manufacturing process of the semiconductor device while remaining the hard mask material on the top surface of the connection member. The material of the second dielectric layer 120 may include any one or more of silicon oxide (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON) and silicon carbonitride (SiCN), and may further include other kinds of dielectric materials, and embodiments of the present application are not limited in detail.
In some alternative embodiments of the present application, as shown in fig. 1, the second dielectric layer 120 includes a first portion over the hard mask layer and a second portion over the storage node contact structure 810, wherein the first portion has a higher peak than the second portion. The grooves are formed in the peripheral area B by simultaneously depositing the hard mask material in the memory area a and the peripheral area B and sequentially performing the patterning process and the etching process, and the grooves are formed in the peripheral area B by simultaneously etching the plurality of connecting pieces 80 at intervals, wherein the depth of the grooves formed in the memory area a is larger than the depth of the grooves in the peripheral area B due to the difference of materials, and if the depth of the grooves in the memory area a is larger, the grooves may be over-etched to the bit lines 220 to cause short circuit.
Illustratively, as shown in fig. 1, the plurality of connection members 80 includes a first connection member 801 and a second connection member 802, a top surface size of the first connection member 801 is larger than a top surface size of the second connection member 802, the hard mask layer 90 is positioned on the top surface of the first connection member 801, a bottom surface size of the hard mask layer 90 contacting the top surface of the first connection member 801 is W3, and a height of the hard mask layer 90 is H3. Specifically, the hard mask layer 90 is formed by leaving a hard mask material on at least the top surface of the second connection member 802 while forming the storage node contact structure 810 and the connection member 80 using patterning process in the manufacturing process of the semiconductor device, at which time the hard mask material on the top surface of the second connection member 802 and the top surface of the storage node contact structure 810 may be removed.
In another example, as shown in fig. 1, the hard mask layer 90 is further located on top of the contact pad 820 in the at least one storage node contact structure 810, the bottom surface of the hard mask layer 90 in contact with the top surface of the contact pad 820 has a dimension W1, and the height of the hard mask layer 90 is H1. Specifically, in the fabrication process of the semiconductor device, the hard mask material remains on the top surface of the second connection member 802 and the top surface of at least one storage node contact structure 810 while the storage node contact structures 810 and the connection members 80 are formed using patterning, and the hard mask material on the top surfaces of the second connection member 802 and the top surfaces of the other storage node contact structures 810 is removed.
In another example, as shown in fig. 1, the hard mask layer 90 is further located on the top surface of the second connection member 802, the bottom surface of the hard mask layer 90 in contact with the top surface of the first connection member 801 has a size W2, and the height of the hard mask layer 90 is H2. In the fabrication process of the semiconductor device, the storage node contact structure 810 and the connection members 80 are formed using patterning, and in addition to the hard mask material remaining on the top surfaces of the first connection members 801 and the top surfaces of the at least one storage node contact structure 810, the hard mask material remains on the top surfaces of the at least one second connection member 802, and the remaining hard mask material forms the hard mask layer 90. Since the top surface size of the first connection member 801 is larger than the top surface size of the second connection member 802, the size of the hard mask layer 90 on the top surface of the first connection member 801 is larger than the hard mask layer 90 on the top surface of the second connection member 802, wherein the bottom surface size of the hard mask layer 90 in contact with the top surface of the first connection member 801 is larger than the bottom surface size of the hard mask layer 90 in contact with the top surface of the second connection member 802, and the height of the hard mask layer 90 on the top surface of the first connection member 801 is also larger than the height of the hard mask layer 90 on the top surface of the second connection member 802.
In some alternative embodiments of the present application, as shown in FIG. 1, the hard mask layer 90 includes a first sub-mask covering the connection 80 and a second sub-mask covering the storage node contact structure 810, the first sub-mask having a higher vertex than the second sub-mask. The first sub-mask is disposed on the top surface of at least one connection member 80, the second sub-mask is disposed on the top surface of at least one storage node contact structure 810, and the first sub-mask and the second sub-mask may be formed by patterning the storage node contact structure 810 and the connection member 80 while leaving a hard mask material on the top surface of the connection member 80 during a process for manufacturing a semiconductor device.
In some alternative embodiments of the present application, the hard mask layer is completely isolated from the top surface of the storage node contact structure. At this time, the hard mask layer is formed by removing the hard mask material on the top surface of the storage node contact structure in the patterning process and simultaneously leaving the hard mask material on the top surface of at least one connection member in the manufacturing process of the semiconductor device.
As shown in fig. 3, the hard mask layer 90 may also directly contact the top surface of the storage node contact structure 810 and the sidewalls of the capacitor structure 130, and after the conductive line 150 (the first connection element 801, the second connection element 802) is connected above the connection element 80, the hard mask layer 90 contacts the sidewalls of the conductive line 150.
In the semiconductor device according to the embodiment of the present application, as shown in fig. 1 and 3, a plurality of capacitor structures 130 are located on the storage node contact structure 810, and each capacitor structure 130 is connected to at least one adjacent capacitor structure 130 through the support layer 140.
The plurality of capacitor structures 130 are disposed above the substrate 10 at intervals, and are connected to the contact pads 820 in the storage node contact structure 810 in a one-to-one correspondence.
There is further provided, in accordance with an embodiment of the present application, a semiconductor device, as shown in fig. 3, which is a schematic structural view of the semiconductor device according to the embodiment of the present application.
As shown in fig. 3, the semiconductor device includes a substrate 10, a plurality of bit lines 220, a plurality of gate structures 210, a first dielectric layer 100, a plurality of connectors 80, a plurality of storage node contact structures 810, a plurality of capacitor structures 130, a hard mask layer 90, and a second dielectric layer 120, wherein: the substrate 10 includes a cell region and a peripheral region; a plurality of bit lines 220 are located on the cell region; a plurality of gate structures 210 are located on the peripheral region; the first dielectric layer 100 is located between adjacent gate structures 210; a plurality of connectors 80 are located within the first dielectric layer 100 and connected to the substrate; the plurality of storage node contact structures 810 are located between adjacent bit lines 220; a plurality of capacitive structures 130 are located on the storage node contact structure 810; the hard mask layer 90 covers the top surface of the connection member; the second dielectric layer 120 covers the hard mask layer 90 and directly contacts the top surface of the connection 80 and the sidewalls of the capacitor structure 130.
In the semiconductor device of the embodiment of the present application, as shown in fig. 3, the hard mask layer 90 may be formed by removing the hard mask material on the top surface of the storage node contact structure 810 in the patterning process while the hard mask material remains on the top surface of the connection member in the manufacturing process of the semiconductor device, specifically, the hard mask material is simultaneously deposited in the memory region a and the peripheral region B, and the patterning process and the etching process are sequentially performed to form the recess in the peripheral region B to space the plurality of connection members 80, the recess is also formed by etching simultaneously in the memory region a, and due to the difference of materials, the depth of the recess formed in the memory region a may be greater than the depth of the recess in the peripheral region B, and if the depth of the recess in the memory region a is greater, the hard mask material may remain on the surface of the second connection member 802, so that the depth of the recess formed in the memory region a may be prevented from being excessively large, thereby avoiding the risk of overetching, and improving the reliability of the device.
In the semiconductor device according to the embodiment of the present application, the positional relationship and materials of the substrate 10, the bit line 220, the gate structure 210, the first dielectric layer 100, the connection member 80, the storage node contact structure 810, the capacitor structure 130 and the hard mask layer 90 may be the same as those of the semiconductor device according to the previous embodiment, and the embodiments of the present application are not repeated.
According to an embodiment of the present application, there is further provided a method for manufacturing a semiconductor device, and fig. 4 is a process flow chart of the method for manufacturing a semiconductor device according to the embodiment of the present application.
As shown in fig. 4 to 11, the manufacturing method of the semiconductor device includes the steps of:
Providing a substrate 10, the substrate 10 including a cell region and a peripheral region:
forming a plurality of bit lines 220 on the cell region, forming a plurality of gate structures 210 on the peripheral region, and forming a first dielectric layer 100 between adjacent gate structures 210;
Forming a plurality of connection members 80 within the first dielectric layer 100;
Forming a plurality of storage node contact structures 810 between adjacent bit lines 220;
Forming a hard mask layer 90 covering the top surface of the connection member 80;
A second dielectric layer 120 and a capacitance structure 130 are formed, the capacitance structure 130 being located on the storage node contact structure 810, the second dielectric layer 120 overlying the hard mask layer 90, wherein the second dielectric layer 120 comprises a first portion located above the hard mask layer 90 and a second portion located above the storage node contact structure 810, an apex of the first portion of the second dielectric layer 120 being located at a different level than an apex of the second portion.
In the method for manufacturing the semiconductor device according to the embodiment of the present application, since the hard mask layer 90 covering the top surface of the connection member 80 is formed, and the second dielectric layer includes the first portion located above the hard mask layer 90 and the second portion located above the storage node contact structure, the top point of the first portion and the top point of the second portion of the second dielectric layer 120 are located at different levels, the hard mask layer 90 is formed by the residual hard mask material during the formation of the connection member 80, and the hard mask material is simultaneously deposited in the memory region a and the peripheral region B during the formation of the connection member 80, the grooves are formed in the peripheral region B by the patterning process and the etching process to space out the plurality of connection members 80, the grooves are also simultaneously etched in the memory region a, and the depth of the grooves formed in the memory region a is greater than the depth of the grooves in the peripheral region B due to the material difference, and if the depth of the grooves in the memory region a is greater, the grooves may be over-etched to the bit line 220, and the excessive etching of the surface of the second connection member 802 is avoided, thereby avoiding the excessive etching of the residual hard mask material in the memory region a and the excessive etching of the peripheral region.
In addition, the hard mask layer 90 may be formed by patterning the storage node contact structure 810 and the connection member 80 while the hard mask material remains on the top surface of the connection member 80 during the fabrication process of the semiconductor device, so that no additional process steps are required, and the technical effect of improving the performance of the semiconductor device without increasing the process time and the process cost is achieved.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
First, as shown in fig. 5, a substrate 10 is provided, the substrate 10 including a cell region and a peripheral region.
The substrate 10 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, and embodiments of the present application are not particularly limited.
In some alternative embodiments, shallow trench isolation Structures (STI) 50 are formed in substrate 10 to define a plurality of active regions (active regions) of memory cells in memory region a of substrate 10 and a plurality of active regions of semiconductor devices in peripheral region B of substrate 10.
After the substrate 10 is provided, as shown in fig. 5, a plurality of bit lines 220 are formed on the cell region, a plurality of gate structures 210 are formed on the peripheral region, and a first dielectric layer 100 is formed between adjacent gate structures 210.
In some alternative embodiments, as shown in fig. 5, the plurality of gate structures 210 located on the peripheral region B and the plurality of bit lines 220 located on the memory region a are formed by the same process steps. Illustratively, a semiconductor material layer, a metal material layer, and a hard mask material layer are sequentially formed on the peripheral region B and the memory region a of the substrate 10, and a patterning process is performed on the hard mask material layer to obtain a patterned mask, and then the metal material layer and the semiconductor material layer are sequentially etched with the patterned mask as a mask to transfer the pattern of the patterned hard mask into the semiconductor material layer, thereby obtaining the gate structure 210 and the bit line 220.
The gate structure 210 may include a first semiconductor layer 211, a first metal layer 212, and a first patterning mask 213 sequentially stacked in a direction away from the substrate 10, and the bit line 220 may include a second semiconductor layer 221, a second metal layer 222, and a second patterning mask 223 sequentially stacked in a direction away from the substrate 10, respectively, wherein materials of the first semiconductor layer 211 and the second semiconductor layer 221 may include polysilicon; the materials of the first and second metal layers 212 and 222 may include low resistivity metal materials such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium aluminum alloy (TiAl), etc.; the materials of the first and second patterned masks 213 and 223 may include any one or more of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN), and may further include other dielectric materials, and the embodiments of the present application are not particularly limited with respect to the above material types.
It should be noted that a gate oxide layer (not shown) may also be formed on the substrate 10 prior to the step of forming the gate structure 210, such that the gate oxide layer is located between the substrate 10 and the semiconductor portion 22 of the gate structure 210, and the gate oxide layer may be made of silicon oxide (SiO 2).
After the step of forming the gate structures 210, as shown in fig. 5, the first dielectric layer 100 located between adjacent gate structures 210 is formed, and after the step of forming the first dielectric layer 100, as shown in fig. 5, the preparation method provided by the embodiment of the present application may further include: a barrier layer 30 is formed over the gate structure 210 and the first dielectric layer 100. The materials of the first dielectric layer 100 and the barrier layer 30 may include any one or more of silicon oxide (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN), and may further include other kinds of dielectric materials, and embodiments of the present application are not limited in detail.
As shown in fig. 5, the preparation method provided by the embodiment of the present application may further include: forming first sidewalls 410 on both sides of the gate structure 210; second sidewalls 420 are formed on both sides of the bit line 220.
The first sidewall 410 includes a first insulating layer 411, a second insulating layer 412, and a third insulating layer 413 sequentially covering sidewalls of the gate structure 210 from inside to outside, and the second sidewall 420 includes a fourth insulating layer 421, a fifth insulating layer 422, and a sixth insulating layer 423 sequentially covering sidewalls of the bit line 220 and the barrier layer 30 from inside to outside.
The first sidewall 410 and the second sidewall 420 may be manufactured by the same process steps, and the materials of the insulating layers in the first sidewall 410 and the second sidewall 420 may be conventional insulating materials in the prior art, such as silicon oxide (SiO 2), which is not particularly limited in the embodiment of the present application.
After the step of forming the first dielectric layer 100, as shown in fig. 6 and 7, a plurality of connection members 80 located within the first dielectric layer 100 are formed.
In some alternative embodiments, the step of forming the connector 80 includes: as shown in fig. 6, contact openings 610 are formed on both sides of at least one gate structure 210, the contact openings 610 extending from both sides of the gate structure 210 into the substrate 10; as shown in fig. 7, a conductive material 821 is deposited on the substrate 10 such that a portion of the conductive material 821 fills into the contact opening 610 to form a first connection 811 as shown in fig. 2, the remaining conductive material 821 forming a conductive layer on the gate structure 210 and on a side of the first dielectric layer 100 facing away from the substrate 10; as shown in fig. 8 and 9, a mask material 910 is deposited on the surface of the conductive layer, and the mask material is patterned to form a patterned mask, and then the conductive layer is etched through the patterned mask to form the conductive layer into the second connection portion 812 as shown in fig. 2, thereby obtaining the first connection member 801 and the second connection member 802.
In the above-described alternative embodiment, as shown in fig. 6, storage node contact openings 620 between adjacent bit lines 220 may be formed at the same time as the contact openings 610 are formed, as shown in fig. 7, conductive material 821 may be simultaneously deposited into the peripheral region B and the memory region a, a portion of the conductive material 821 deposited into the peripheral region B fills into the contact openings 610, a portion of the conductive material 821 deposited into the memory region a fills into the storage node contact openings 620, as shown in fig. 8, a mask material 910 deposited on the surface of the conductive layer also covers the surface of the conductive material 821 in the memory region a, and after the mask material is formed into a patterned hard mask, the conductive material 821 is etched through the patterned hard mask located in the memory region a to form the contact pads 820.
In some alternative embodiments, the conductive material covering the bit lines and gate structures is formed first, the patterned hard mask is formed on the surface of the conductive material, then the conductive material is partially removed to form the connection and storage node contact structures, and then the patterned hard mask on the storage node contact structures is completely removed to form a hard mask layer covering the top surfaces of the connection.
In the above alternative embodiment, the hard mask material on the top surface of the storage node contact structure is completely removed in the patterning process, and at the same time, part of the hard mask material remains on the top surface of the connection member to form a hard mask layer, so that the depth of the groove formed by etching in the memory region a can be avoided, the risk of over etching is avoided, and the reliability of the device is improved.
In other alternative embodiments, as shown in fig. 7 and 8, a conductive material 821 is formed overlying the bit line 220 and the gate structure 210; forming a patterned hard mask on a surface of the conductive material 821; partially removing conductive material 821 to form connection 80 and storage node contact structure 810; the partial removal of the patterned hard mask forms a first sub-mask covering the connection 80 and a second sub-mask covering the storage node contact structure 810, the vertices of the first sub-mask being higher than the vertices of the second sub-mask.
In the above alternative embodiment, the first sub-mask is disposed on the top surface of at least one connection member 80, the second sub-mask is disposed on the top surface of at least one storage node contact structure 810, the first sub-mask and the second sub-mask may be formed by patterning the storage node contact structure 810 and the connection member 80 while the hard mask material remains on the top surface of the connection member 80 during the process of manufacturing the semiconductor device, the etching process is performed after the patterning process to form a groove in the peripheral region B, a plurality of connection members 80 are spaced apart by the groove, the groove is also etched synchronously in the memory region a, the depth of the groove formed in the memory region a is greater than the depth of the groove in the peripheral region B due to the difference of materials, if the depth of the groove in the memory region a is greater, the hard mask material remains on the top surface of the connection member 80 is greater than the height of the hard mask material remains on the top surface of the storage node contact structure, thereby preventing the deep overetching of the groove formed in the memory region a from being greater than the hard mask material remains on the top surface of the storage node contact structure, and thus the risk of overetching the device is avoided.
After the step of forming the connection 80 and the storage node contact structure 810, as shown in fig. 9, the preparation method provided in the embodiment of the present application may further include: dielectric material 101 is deposited over substrate 10 to cover connection 80, storage node contact structures 810, and hard mask layer 90 and to fill between adjacent storage node contact structures 810 and between adjacent connection 80, as shown in fig. 10, the portions of dielectric material 101 that cover connection 80, storage node contact structures 810, and hard mask layer 90 are removed.
After the step of forming the dielectric material 101, as shown in fig. 11, a second dielectric layer 120 is formed, where the second dielectric layer 120 includes a first portion located above the hard mask layer 90 and a second portion located above the storage node contact structure 810, and the peaks of the first portion and the peaks of the second portion of the second dielectric layer 120 are located at different levels, so that the depth of the recess formed by etching in the memory region a can be prevented from being excessively large, thereby avoiding the risk of over-etching, and improving the device reliability.
In addition, the hard mask layer 90 may be formed by patterning the storage node contact structure 810 and the connection member 80 while the hard mask material remains on the top surface of the connection member 80 during the fabrication process of the semiconductor device, so that no additional process steps are required, and the technical effect of improving the performance of the semiconductor device without increasing the process time and the process cost is achieved.
After the step of forming the second dielectric layer 120, as shown in fig. 1, a capacitance structure 130 is formed, the capacitance structure 130 being located on the storage node contact structure 810.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.

Claims (12)

1. A semiconductor device, comprising:
a substrate including a cell region and a peripheral region;
a plurality of bit lines on the cell region;
a plurality of gate structures located on the peripheral region;
a first dielectric layer located between adjacent gate structures;
a plurality of connectors within the first dielectric layer connected to the substrate;
a plurality of storage node contact structures located between adjacent bit lines;
A plurality of capacitor structures located on the storage node contact structures;
a hard mask layer covering the top surface of the connection member;
A second dielectric layer including a first portion over the hard mask layer and a second portion over the storage node contact structure, an apex of the first portion of the second dielectric layer being at a different level than an apex of the second portion.
2. A semiconductor device, comprising:
a substrate including a cell region and a peripheral region;
a plurality of bit lines on the cell region;
a plurality of gate structures located on the peripheral region;
a first dielectric layer located between adjacent gate structures;
a plurality of connectors within the first dielectric layer connected to the substrate;
a plurality of storage node contact structures located between adjacent bit lines;
A plurality of capacitor structures located on the storage node contact structures;
a hard mask layer covering the top surface of the connection member;
and a second dielectric layer covering the hard mask layer and directly contacting the top surface of the connection member and the sidewall of the capacitor structure.
3. The semiconductor device of claim 1, wherein an apex of the first portion of the second dielectric layer is higher than an apex of the second portion.
4. The semiconductor device of claim 1, wherein an apex of the hard mask layer is higher than an apex of the second portion of the second dielectric layer.
5. The semiconductor device of claim 1 or 2, wherein the hard mask layer comprises a first sub-mask covering the connection and a second sub-mask covering the storage node contact structure, the first sub-mask having a vertex higher than a vertex of the second sub-mask.
6. The semiconductor device of claim 1 or 2, wherein the hard mask layer is completely isolated from a top surface of the storage node contact structure.
7. The semiconductor device of claim 1 or 2, further comprising a third dielectric layer over the gate structure and between adjacent the connectors, an apex of the third dielectric layer being lower than an apex of the hard mask layer.
8. The semiconductor device of claim 5, wherein the hard mask layer directly contacts a top surface of the connection and a sidewall of the capacitor structure.
9. A method of manufacturing a semiconductor device, comprising:
Providing a substrate comprising a cell region and a peripheral region:
Forming a plurality of bit lines on the cell region, forming a plurality of gate structures on the peripheral region, and forming a first dielectric layer between adjacent gate structures;
forming a plurality of connectors within the first dielectric layer;
Forming a plurality of storage node contact structures between adjacent bit lines;
Forming a hard mask layer covering the top surface of the connecting piece;
A second dielectric layer and a capacitance structure are formed, the capacitance structure is located on the storage node contact structure, the second dielectric layer covers the hard mask layer, wherein the second dielectric layer comprises a first portion located above the hard mask layer and a second portion located above the storage node contact structure, and the vertex of the first portion of the second dielectric layer and the vertex of the second portion are located at different levels.
10. The method of manufacturing according to claim 9, further comprising:
Forming a conductive material covering the bit line and the gate structure;
forming a patterned hard mask on the surface of the conductive material;
partially removing conductive material to form the connection and the storage node contact structure;
And completely removing the patterned hard mask on the storage node contact structure to form a hard mask layer covering the top surface of the connecting piece.
11. The method of manufacturing according to claim 9, further comprising:
Forming a conductive material covering the bit line and the gate structure;
forming a patterned hard mask on the surface of the conductive material;
partially removing conductive material to form the connection and the storage node contact structure;
And partially removing the patterned hard mask to form a first sub-mask covering the connection and a second sub-mask covering the storage node contact structure, wherein the vertex of the first sub-mask is higher than that of the second sub-mask.
12. The production method according to any one of claims 9 to 11, characterized by further comprising:
A third dielectric layer is formed such that the third dielectric layer is located over the gate structure and between adjacent ones of the connectors.
CN202410832178.6A 2024-06-25 2024-06-25 Semiconductor device and method for manufacturing the same Pending CN118555830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410832178.6A CN118555830A (en) 2024-06-25 2024-06-25 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410832178.6A CN118555830A (en) 2024-06-25 2024-06-25 Semiconductor device and method for manufacturing the same

Publications (1)

Publication Number Publication Date
CN118555830A true CN118555830A (en) 2024-08-27

Family

ID=92450480

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202410832178.6A Pending CN118555830A (en) 2024-06-25 2024-06-25 Semiconductor device and method for manufacturing the same

Country Status (1)

Country Link
CN (1) CN118555830A (en)

Similar Documents

Publication Publication Date Title
CN108389861B (en) Semiconductor element and forming method thereof
CN110581103B (en) Semiconductor element and manufacturing method thereof
CN108346660B (en) Semiconductor device and method for forming the same
CN110634869A (en) Memory array and method of manufacturing the same
US11737257B2 (en) Semiconductor device and manufacturing method thereof
US6261937B1 (en) Method for forming a semiconductor fuse
US6255224B1 (en) Method of forming contact for semiconductor device
CN109427786B (en) Semiconductor memory device and manufacturing process thereof
KR100444115B1 (en) Semiconductor device with capacitor electrodes and method of manufacturing thereof
US6642135B2 (en) Method for forming semiconductor memory device having a fuse
US7411240B2 (en) Integrated circuits including spacers that extend beneath a conductive line
JP2004140361A (en) Semiconductor device using damascene process and its manufacturing method
CN114068552A (en) Semiconductor device and method of manufacturing the same
KR20020091950A (en) Semiconductor memory device and method for fabricating the same
CN215600368U (en) Semiconductor structure
CN215600367U (en) Semiconductor structure
US7074725B2 (en) Method for forming a storage node of a capacitor
CN118555830A (en) Semiconductor device and method for manufacturing the same
CN100390985C (en) Semiconductor with column cap layer and manufacture thereof
CN113437067B (en) Semiconductor structure and manufacturing method thereof
US20230298999A1 (en) Semiconductor memory device
CN216563127U (en) Semiconductor memory device with a plurality of memory cells
KR100906646B1 (en) Semiconductor memory device and method for manufacturing the same
CN110718549A (en) Dynamic random access memory and manufacturing, writing and reading method thereof
US20240306372A1 (en) Dynamic random access memory and method of fabricating the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination