CN118538753A - SOI-LDMOS structure and preparation method thereof - Google Patents

Abstract

The application belongs to the technical field of semiconductors, and particularly relates to an SOI-LDMOS structure and a preparation method thereof. The application discloses an SOI-LDMOS structure, which comprises a substrate, a buried oxide layer and a top silicon layer which are sequentially arranged along the thickness direction, wherein the top silicon layer is provided with a source region and a drain region which are arranged at intervals, the drain region is provided with a drain plug which penetrates through the top silicon layer along the thickness direction, and the drain plug is made of at least one of metal or N-type doped polysilicon. The embodiment of the application also provides a preparation method of the SOI-LDMOS structure, which comprises the following steps: providing an initial SOI-LDMOS structure, wherein the initial SOI-LDMOS structure comprises a substrate, a buried oxide layer and a top silicon layer which are sequentially arranged along the thickness direction; forming a fifth through hole penetrating through the top silicon layer in the thickness direction on the initial SOI-LDMOS structure; and depositing at least one material of metal or N-type doped polysilicon in the fifth through hole to form a drain plug.

Description

SOI-LDMOS structure and preparation method thereof

Technical Field

The application belongs to the technical field of semiconductors, and particularly relates to an SOI-LDMOS structure and a preparation method thereof.

Background

The top silicon layer of the SOI-LDMOS (Silicon On Insulator, laternal Double-diffused Metal Oxide Semiconductor, silicon-insulator Lateral Double-diffusion metal oxide semiconductor) device is thinner, and the device is easy to generate strong impact ionization at the edge of a strong N-type doped region of the drain under high voltage of the drain, so that the robustness of the device is seriously affected.

Disclosure of Invention

The embodiment of the application provides an SOI-LDMOS structure, which can reduce collision ionization at the drain electrode.

The embodiment of the application provides an SOI-LDMOS structure, which comprises a substrate, an oxygen-buried layer and a top silicon layer which are sequentially arranged along the thickness direction, wherein the top silicon layer is provided with a source region and a drain region which are arranged at intervals, the drain region is provided with a drain plug penetrating through the top silicon layer along the thickness direction, and the drain plug is made of at least one of metal or N-type doped polysilicon.

According to an embodiment of the first aspect of the present application, the semiconductor device further comprises a dielectric layer located on a side of the top silicon layer away from the buried oxide layer, and the drain plug extends from the top silicon layer to the dielectric layer.

According to an embodiment of the first aspect of the present application, the drain plug comprises a first portion and a second portion connected to each other, at least part of the first portion is located on the top silicon layer, the second portion is located on the dielectric layer, and in a thickness direction, an orthographic projection of the second portion on the buried oxide layer is larger than an orthographic projection of the first portion on the buried oxide layer, or the orthographic projection of the second portion on the buried oxide layer overlaps with the orthographic projection of the first portion on the buried oxide layer.

According to an embodiment of the first aspect of the present application, at least part of the first portion is located in the dielectric layer, and the second portion is spaced apart from the top silicon layer in a thickness direction.

According to an embodiment of the first aspect of the present application, the semiconductor device further comprises a first metal layer and a second metal layer located on a side of the dielectric layer away from the top silicon layer, wherein the first metal layer and the second metal layer are arranged at intervals; the dielectric layer is provided with a first through hole and a second through hole, the first through hole is communicated with the source region and the first metal layer, and the second through hole is communicated with the drain plug and the second metal layer.

According to an embodiment of the first aspect of the present application, a body contact region is further provided in the top silicon layer, and the body contact region is connected to the first metal layer through a via hole.

According to an embodiment of the first aspect of the present application, the semiconductor device further comprises a gate electrode located on a side of the top silicon layer away from the buried oxide layer, and a gate dielectric layer is disposed between the gate electrode and the top silicon layer.

On the other hand, the embodiment of the application also provides a preparation method of the SOI-LDMOS structure, which comprises the following steps: providing an initial SOI-LDMOS structure, wherein the initial SOI-LDMOS structure comprises a substrate, a buried oxide layer and a top silicon layer which are sequentially arranged along the thickness direction; forming a fifth through hole penetrating through the top silicon layer in the thickness direction on the initial SOI-LDMOS structure; and depositing at least one material of metal or N-type doped polysilicon in the fifth through hole to form a drain plug.

According to an embodiment of the second aspect of the present application, the step of forming a fifth via hole penetrating the top silicon layer in the thickness direction on the initial SOI-LDMOS structure comprises: forming a dielectric layer on one side of the top silicon layer, which is away from the oxygen buried layer; forming a fifth through hole penetrating through the top silicon layer and the dielectric layer in the thickness direction on the initial SOI-LDMOS structure; depositing at least one material of metal or N-type doped polysilicon in the fifth through hole to form a drain plug, comprising: and depositing at least one material of metal or N-type doped polysilicon in the fifth through hole to form a drain plug, wherein the drain plug comprises a first part and a second part which are connected with each other, at least part of the first part is positioned on the top silicon layer, the second part is positioned on the dielectric layer, and the orthographic projection of the second part on the oxygen-buried layer is larger than the orthographic projection of the first part on the oxygen-buried layer in the thickness direction, or the orthographic projection of the second part on the oxygen-buried layer overlaps with the orthographic projection of the first part on the oxygen-buried layer.

The SOI-LDMOS structure comprises a substrate, an oxygen buried layer and a top silicon layer which are sequentially arranged along the thickness reverse direction, wherein a source region and a drain region which are arranged at intervals are arranged in the top silicon layer, drain plugs penetrating through the top silicon layer along the thickness direction are arranged on the drain region, and the drain plugs are made of at least one of metal or N-type doped polysilicon; by adopting the drain plug to replace the drain contact layer, the wider current path of the drain plug can greatly improve the saturation current and on-resistance of the device, effectively improve the electric field/current concentration at the edge of the drain, reduce collision ionization and improve the robustness; due to the existence of the buried oxide layer, electric leakage from the drain electrode to the substrate does not occur even under the condition that the drain electrode is connected with high voltage, and the reliability of the device is further improved.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings that are needed to be used in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.

Fig. 1 is a schematic structural diagram of an SOI-LDMOS structure according to an embodiment of the first aspect of the present application;

FIG. 2 is a schematic diagram of another SOI-LDMOS structure;

Fig. 3 is a flow chart of a method for fabricating an SOI-LDMOS structure according to an embodiment of the second aspect of the present application;

FIG. 4 is a flow chart of another method of fabricating an SOI-LDMOS structure;

FIG. 5 is a process flow diagram of yet another method of fabricating an SOI-LDMOS structure;

Fig. 6 is a schematic structural diagram of the SOI-LDMOS structure illustrated in fig. 4 at the end of step S011;

Fig. 7 is a schematic structural diagram of the SOI-LDMOS structure illustrated in fig. 4 at the end of step S012;

fig. 8 is a schematic structural diagram of the SOI-LDMOS structure of fig. 4 at the end of step S022;

fig. 9 is a schematic structural diagram of the SOI-LDMOS structure illustrated in fig. 4 at the end of step S03;

fig. 10 is a schematic structural diagram of the SOI-LDMOS structure illustrated in fig. 4 at the end of step S04.

Reference numerals:

10. A substrate; 20. an oxygen burying layer; 30. a top silicon layer; 31. a source region; 32. a drain region; 321. a drain plug; 3211. a first portion; 3212. a second portion; 33. a body contact region; 34. a body region; 35. a drift region; 36. a drift region field plate; 40. a first metal layer; 41. a second metal layer; 50. a first through hole; 51. a second through hole; 52. a third through hole; 53. a fourth through hole; 54. a fifth through hole; 60. a gate;

x, thickness direction.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the particular embodiments described herein are meant to be illustrative of the application only and not limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The applicant finds that in the prior art, the thickness of the top silicon layer of the SOI-LDMOS device is thinner, the device is easy to generate strong impact ionization at the edge of a strong N-type doped region of the drain under the high voltage of the drain, and the robustness of the device is seriously affected.

In view of the above, the applicant proposes an SOI-LDMOS structure comprising a substrate, a buried oxide layer and a top silicon layer arranged in sequence in a thickness direction, the top silicon layer having a source region and a drain region arranged at intervals therein, the drain region being provided with a drain plug penetrating the top silicon layer in the thickness direction, the drain plug being made of at least one of metal or N-doped polysilicon.

The SOI-LDMOS structure comprises a substrate, a buried oxide layer and a top silicon layer which are sequentially arranged along the thickness reverse direction, wherein a source region and a drain region which are arranged at intervals are arranged in the top silicon layer, drain plugs penetrating through the top silicon layer along the thickness direction are arranged on the drain region, and the drain plugs are made of at least one of metal or N-type doped polysilicon; by adopting the drain plug to replace the drain contact layer, the wider current path of the drain plug can greatly improve the saturation current and on-resistance of the device, effectively improve the electric field/current concentration at the edge of the drain, reduce collision ionization and improve the robustness; due to the existence of the buried oxide layer, electric leakage from the drain electrode to the substrate does not occur even under the condition that the drain electrode is connected with high voltage, and the reliability of the device is further improved.

The following describes a video substrate provided by an embodiment of the present application with reference to the accompanying drawings. In this description, the thickness direction of the SOI-LDMOS structure is the x-direction in the drawings. In the drawings, the dimensions in the drawings are not necessarily to scale with real dimensions for convenience in drawing.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an SOI-LDMOS structure according to an embodiment of the present application.

As shown in fig. 1, an embodiment of the first aspect of the present application provides an SOI-LDMOS structure, which includes a substrate 10, a buried oxide layer 20 and a top silicon layer 30 sequentially arranged along a thickness direction (x direction in the drawing), wherein the top silicon layer 30 has a source region 31 and a drain region 32 that are disposed at intervals, the drain region 32 is provided with a drain plug 321 penetrating through the top silicon layer 30 along the thickness direction x, and the drain plug 321 is made of at least one of metal or N-type doped polysilicon.

Alternatively, the SOI-LDMOS structure can be prepared and formed through an oxygen injection isolation process, a bonding thinning process and an intelligent stripping process. Taking an example of an oxygen implantation isolation process, the buried oxide layer 20 is formed in silicon by high energy, high dose oxygen implantation, and the oxygen ion implantation is performed to a depth below the surface of the silicon wafer by high energy implantation. And after ion implantation, forming a layer of embedded silicon dioxide in the silicon wafer by high-temperature annealing. The buried oxide layer 20 divides the wafer into two parts, the upper thin layer of silicon (i.e., top silicon layer 30) is used as the device, and the lower substrate 10.

Alternatively, the metal material forming the drain plug 321 may be tungsten. The polysilicon forming the drain plug 321 is subjected to high N-type doping, so that a strong N-type doped region is formed around the drain plug 321 by an annealing diffusion process, which is very beneficial to forming ohmic contacts. Compared with the strong N-type ion implantation process of the drain electrode, the method has the advantages that a deep N junction can be formed, the semiconductor capacitance is increased, the shallow junction is easy to form due to thermal diffusion, the output capacitance of the device can be effectively improved, and the device efficiency is improved.

The SOI-LDMOS structure of the embodiment of the present application includes a substrate 10, a buried oxide layer 20 and a top silicon layer 30 sequentially arranged along a thickness direction x, wherein the top silicon layer 30 has a source region 31 and a drain region 32 which are arranged at intervals, the drain region 32 is provided with a drain plug 321 penetrating the top silicon layer 30 along the thickness direction x, and the drain plug 321 is made of at least one of metal or N-type doped polysilicon. By adopting the drain plug 321 to replace a drain contact layer, the wider current path of the drain plug 321 can greatly improve the saturation current and on-resistance of the device, effectively improve the electric field/current concentration at the edge of the drain, reduce collision ionization and improve the robustness; due to the presence of the buried oxide layer 20, no drain-to-substrate 10 leakage occurs even at high drain voltage, further improving device reliability.

In some alternative embodiments, a dielectric layer (not shown) is further included on a side of the top silicon layer 30 remote from the buried oxide layer 20, and a drain plug 321 extends from the top silicon layer 30 to the dielectric layer.

Alternatively, the dielectric layer is not limited to a single level, nor is it limited to one-shot. Dielectric layers include, but are not limited to, planarizing layers and interlayer dielectrics that function as spacers, and the like. The dielectric layer can be formed at one time or formed and overlapped for multiple times.

In some alternative embodiments, drain plug 321 includes a first portion 3211 and a second portion 3212 that are connected to each other, at least a portion of first portion 3211 being located in top silicon layer 30 and second portion 3212 being located in a dielectric layer. In the thickness direction x, the orthographic projection of the second portion 3212 on the buried oxide layer 20 is larger than the orthographic projection of the first portion 3211 on the buried oxide layer 20.

Optionally, at least part of the first portion 3211 is located in the dielectric layer, and the second portion 3212 is spaced apart from the top silicon layer 30 in the thickness direction x.

Alternatively, the materials of the first portion 3211 and the second portion 3212 may be the same or different. In the thickness direction x, the orthographic projection of the first portion 3211 onto the buried oxide layer 20 is located within the orthographic projection of the second portion 3212 onto the buried oxide layer 20. The second portion 3212 is prepared by an etching process.

According to the SOI-LDMOS structure provided by the embodiment of the application, the orthographic projection of the second part 3212 on the buried oxide layer 20 is larger than that of the first part 3211 on the buried oxide layer 20, the mushroom-shaped drain plug 321 can adjust the electric field at the drain edge, the second part 3212 extends out of the field plate with high potential to influence the electric field distribution, so that the high electric field point at the PN edge is far away from the surface, the high electric field at the surface near the drain of the device under breakdown voltage is further improved, and the reliability of the device is further improved.

Referring to fig. 2, fig. 2 is a schematic diagram of another SOI-LDMOS structure.

As shown in fig. 2, in some alternative embodiments, in the thickness direction x, the orthographic projection of the first portion 3211 on the buried oxide layer 20 overlaps with the orthographic projection of the second portion 3212 on the buried oxide layer 20, i.e., the drain plug 321 has a columnar shape.

In the SOI-LDMOS structure of the embodiment of the present application, by overlapping the orthographic projection of the first portion 3211 on the buried oxide layer 20 and the orthographic projection of the second portion 3212 on the buried oxide layer 20, compared with the mushroom-shaped drain plug 321, a photolithography plate is saved during the preparation, the preparation process is simplified, and the production cost is reduced.

With continued reference to fig. 1, in some alternative embodiments, the SOI-LDMOS structure may further include a first metal layer 40 and a second metal layer 41 on a side of the dielectric layer remote from the top silicon layer 30, the first metal layer 40 and the second metal layer 41 being spaced apart. The dielectric layer is provided with a first through hole 50 and a second through hole 51, the first through hole 50 is communicated with the source region 31 and the first metal layer 40, and the second through hole 51 is communicated with the drain plug 321 and the second metal layer 41.

Alternatively, the first metal layer 40 is spaced apart from the second metal layer 41 means that there is no electrical connection between the first metal layer 40 and the second metal layer 41. The first metal layer 40 and the second metal layer 41 may be at the same level in the thickness direction x.

In some alternative embodiments, the SOI-LDMOS structure may further comprise a third via 52 penetrating the substrate 10, the buried oxide layer 20, the top silicon layer 30 and the dielectric layer, the third via 52 being in communication with the first metal layer 40. The first metal layer 40 is connected to the surface of the substrate 10 opposite to the buried oxide layer 20 through a third via 52 to realize the source-to-ground connection of the transistor.

Alternatively, an end of the third via 52 facing away from the first metal layer 40 may also be provided inside the substrate 10.

In some alternative embodiments, a body contact region 33 may also be provided in the top silicon layer 30, the body contact region 33 being in communication with the first metal layer 40 through the first via 50.

Optionally, a body region 34 and a drift region 35 may be further disposed in the top silicon layer 30, where the source region 31, the body region contact region 33, the body region 34 and the drift region 35 are all made by an ion implantation doping process, and the source region 31 and the body region contact region 33 are heavily doped, and the body region 34 and the drift region 35 are lightly doped. Specifically, the same region of the top silicon layer 30 is implanted twice with different species, such as arsenic and boron. The implantation is followed by a high temperature drive-in process, which creates a channel with a concentration gradient, i.e., body region 34, due to the difference in diffusion rates of the two species.

Optionally, a drift region 35 is located between the source region 31 and the drain region 32 in order to increase the breakdown voltage, and when the device is connected to a high voltage, the drift region 35 can withstand a higher voltage due to the high resistance.

In some alternative embodiments, a drift region field plate 36 may be further disposed in the top silicon layer 30, and in the thickness direction x, an orthographic projection of the drift region field plate 36 on the buried oxide layer 20 at least partially overlaps an orthographic projection of the drift region 35 on the buried oxide layer 20. A fourth through hole 53 is disposed between the drift region field plate 36 and the first metal layer 40, and the fourth through hole 53 is used for communicating the drift region field plate 36 and the first metal layer 40.

Optionally, the first through hole 50, the second through hole 51, the third through hole 52 and the fourth through hole 53 are filled with a conductive material.

According to the SOI-LDMOS structure provided by the embodiment of the application, the surface electric field of the drift region 35 is regulated through the drift region field plate 36, so that the coupling capacitance between the grid electrode and the drain electrode is reduced, and the breakdown voltage of the structure is improved.

In some alternative embodiments, the SOI-LDMOS structure further comprises a gate 60 on a side of the top silicon layer 30 remote from the buried oxide layer 20, a gate dielectric layer (not shown) being provided between the gate 60 and the top silicon layer 30.

Optionally, the gate 60 is made of metal or polysilicon. The gate dielectric layer is silicon dioxide with very thin thickness.

Referring to fig. 3, fig. 3 is a flowchart illustrating a method for fabricating an SOI-LDMOS structure according to a second embodiment of the present application.

As shown in fig. 3, an embodiment of the second aspect of the present application further provides a method for preparing an SOI-LDMOS structure, including:

In step S01, an initial SOI-LDMOS structure is provided, which comprises a substrate 10, a buried oxide layer 20 and a top silicon layer 30, which are arranged in sequence in a thickness direction x.

In step S02, a fifth via 54 is formed through the top silicon layer 30 in the thickness direction x on the initial SOI-LDMOS structure.

In step S03, at least one material of metal or N-doped polysilicon is deposited in the fifth via 54 to form the drain plug 321.

Optionally, the fifth via 54 is prepared by an etching process, and the fifth via 54 uses the buried oxide layer 20 as an etching stop. The fifth via 54 is located at the drain region 32.

Referring to fig. 4,6 and 7, fig. 4 is a flow chart of another method for manufacturing an SOI-LDMOS structure, and fig. 6 is a schematic structural diagram at the end of step S011 in the method for manufacturing an SOI-LDMOS structure shown in fig. 4; fig. 7 is a schematic structural diagram of the SOI-LDMOS structure shown in fig. 4 at the end of step S012.

As shown in fig. 4, 6 and 7, in some alternative embodiments, before step S02, the method further includes:

In step S011, a gate 60 is formed on a side of the top silicon layer 30 facing away from the buried oxide layer 20, and a gate dielectric layer is disposed between the gate 60 and the top silicon layer 30.

In step S012, a source region 31, a body contact region 33, a body region 34, and a drift region 35 are formed on the top silicon layer 30.

Alternatively, the source region 31, the body contact region 33, the body region 34, and the drift region 35 are prepared by an ion implantation process.

Referring to fig. 4, 8 and 9, fig. 8 is a schematic structural diagram of the SOI-LDMOS structure illustrated in fig. 4 at the end of step S022; fig. 9 is a schematic structural diagram of the SOI-LDMOS structure shown in fig. 4 at the end of step S03.

As shown in fig. 4, 8, and 9, in some alternative embodiments, step S02 includes:

in step S021, a dielectric layer is formed on the side of the top silicon layer 30 facing away from the buried oxide layer 20. This dielectric layer serves to protect the gate 60 in order to prevent subsequent deposition of drain plug 321 material onto the gate 60.

In step S022, a fifth via 54 is formed through the top silicon layer 30 and the dielectric layer in the thickness direction x on the initial SOI-LDMOS structure.

Step S03 includes: at least one material of metal or N-doped polysilicon is deposited in the fifth via 54 to form a drain plug 321, the drain plug 321 comprising a first portion 3211 and a second portion 3212 connected to each other, at least part of the first portion 3211 being located in the top silicon layer 30 and the second portion 3212 being located in the dielectric layer, the orthographic projection of the second portion 3212 onto the buried oxide layer 20 being larger than the orthographic projection of the first portion 3211 onto the buried oxide layer 20 in the thickness direction x.

Alternatively, the drain plug 321 is formed by a deposition-then-etching-then-annealing process, and the drain plug 321 can form a good ohmic contact by a thermal annealing process after deposition and etching. The mushroom drain plug 321 needs to be prepared by using a photoresist, a mask plate and other process equipment.

According to the preparation method of the SOI-LDMOS structure, the orthographic projection of the second part 3212 on the buried oxide layer 20 is larger than that of the first part 3211 on the buried oxide layer 20, the mushroom-shaped drain plug 321 can adjust the electric field at the edge of the drain, the second part 3212 extends out of a field plate with high potential to influence the electric field distribution, so that the high electric field point at the PN edge is far away from the surface, the high electric field at the surface near the drain of the device under breakdown voltage is further improved, and the reliability of the device is further improved.

Referring to fig. 5, fig. 5 is a flowchart illustrating a method for fabricating an SOI-LDMOS structure.

As shown in fig. 5, in some alternative embodiments, step S03 includes: at least one material of metal or N-doped polysilicon is deposited in the fifth via 54 to form a drain plug 321, the drain plug 321 comprising a first portion 3211 and a second portion 3212 connected to each other, at least part of the first portion 3211 being located in the top silicon layer 30 and the second portion 3212 being located in the dielectric layer, an orthographic projection of the second portion 3212 onto the buried oxide layer 20 overlapping an orthographic projection of the first portion 3211 onto the buried oxide layer 20 in the thickness direction x.

According to the preparation method of the SOI-LDMOS structure, the orthographic projection of the first part 3211 on the buried oxide layer 20 is overlapped with the orthographic projection of the second part 3212 on the buried oxide layer 20, so that compared with the mushroom-shaped drain plug 321, one photoetching plate is saved during preparation, the preparation process is simplified, and the production cost is reduced.

Referring to fig. 1, 4 and 10, fig. 10 is a schematic structural diagram of the SOI-LDMOS structure illustrated in fig. 4 at the end of step S04.

As shown in fig. 1, 4 and 10, in some alternative embodiments, the method for fabricating the SOI-LDMOS structure further includes, after step S3:

In step S04, a second dielectric layer (not shown) is formed on a side of the dielectric layer away from the top silicon layer 30, a metal material is deposited on a side of the second dielectric layer away from the first dielectric layer, and the metal material is etched to form the drift region field plate 36.

In step S05, a third dielectric layer (not shown) is formed on the side of the second dielectric layer facing away from the top silicon layer 30, the third dielectric layer is planarized, the first via hole 50, the second via hole 51, the third via hole 52 and the fourth via hole 53 are formed by etching, the conductive material is filled in each via hole, and the first metal layer 40 and the second metal layer 41 are formed on the side of the third dielectric layer facing away from the top silicon layer 30 (as shown in fig. 1).

The SOI-LDMOS structure comprises a substrate 10, a buried oxide layer 20 and a top silicon layer 30 which are sequentially arranged along a thickness reverse x, wherein the top silicon layer 30 is provided with a source region 31 and a drain region 32 which are arranged at intervals, the drain region 32 is provided with a drain plug 321 penetrating through the top silicon layer 30 along the thickness direction x, and the drain plug 321 is made of at least one of metal or N-type doped polysilicon. By adopting the drain plug 321 to replace a drain contact layer, the wider current path of the drain plug 321 can greatly improve the saturation current and on-resistance of the device, effectively improve the electric field/current concentration at the edge of the drain, reduce collision ionization and improve the robustness; due to the presence of the buried oxide layer 20, no drain-to-substrate 10 leakage occurs even at high drain voltage, further improving device reliability.

In the foregoing, only the specific embodiments of the present application are described, and it will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein. It should be understood that the scope of the present application is not limited thereto, and any equivalent modifications or substitutions can be easily made by those skilled in the art within the technical scope of the present application, and they should be included in the scope of the present application.

Claims (9)

1. The SOI-LDMOS structure is characterized by comprising a substrate, an oxygen-buried layer and a top silicon layer which are sequentially arranged along the thickness direction, wherein a source region and a drain region which are arranged at intervals are arranged in the top silicon layer, a drain plug penetrating through the top silicon layer along the thickness direction is arranged on the drain region, and the drain plug is made of at least one of metal or N-type doped polysilicon.

2. The SOI-LDMOS structure of claim 1 further comprising a dielectric layer on a side of the top silicon layer remote from the buried oxide layer, the drain plug extending from the top silicon layer to the dielectric layer.

3. The SOI-LDMOS structure of claim 2, wherein the drain plug comprises a first portion and a second portion that are connected to each other, at least a portion of the first portion being located in the top silicon layer, the second portion being located in the dielectric layer, an orthographic projection of the second portion on the buried oxide layer being greater than an orthographic projection of the first portion on the buried oxide layer or an orthographic projection of the second portion on the buried oxide layer overlapping an orthographic projection of the first portion on the buried oxide layer in the thickness direction.

4. The SOI-LDMOS structure of claim 3, wherein at least a portion of the first portion is located in the dielectric layer and the second portion is spaced apart from the top silicon layer in the thickness direction.

5. The SOI-LDMOS structure of claim 2, further comprising a first metal layer and a second metal layer on a side of the dielectric layer remote from the top silicon layer, the first metal layer and the second metal layer being spaced apart; the dielectric layer is provided with a first through hole and a second through hole, the first through hole is communicated with the source region and the first metal layer, and the second through hole is communicated with the drain plug and the second metal layer.

6. The SOI-LDMOS structure of claim 5, wherein a body contact is further provided in the top silicon layer, the body contact being in communication with the first metal layer through the via.

7. The SOI-LDMOS structure of claim 1 further comprising a gate electrode on a side of the top silicon layer remote from the buried oxide layer, a gate dielectric layer being disposed between the gate electrode and the top silicon layer.

8. The preparation method of the SOI-LDMOS structure is characterized by comprising the following steps of:

providing an initial SOI-LDMOS structure, wherein the initial SOI-LDMOS structure comprises a substrate, a buried oxide layer and a top silicon layer which are sequentially arranged along the thickness direction;

Forming a fifth through hole penetrating through the top silicon layer along the thickness direction on the initial SOI-LDMOS structure;

and depositing at least one material of metal or N-type doped polysilicon in the fifth through hole to form a drain plug.

9. The method of fabricating a SOI-LDMOS structure according to claim 8, wherein the step of forming a fifth via through the top silicon layer in the thickness direction on the initial SOI-LDMOS structure comprises:

forming a dielectric layer on one side of the top silicon layer, which is away from the oxygen-buried layer;

Forming a fifth through hole penetrating through the top silicon layer and the dielectric layer along the thickness direction on the initial SOI-LDMOS structure;

The step of depositing at least one material of metal or N-type doped polysilicon in the fifth through hole to form a drain plug comprises the following steps:

And depositing at least one material of metal or N-type doped polysilicon in the fifth through hole to form a drain plug, wherein the drain plug comprises a first part and a second part which are connected with each other, at least part of the first part is positioned on the top silicon layer, the second part is positioned on the dielectric layer, and the orthographic projection of the second part on the buried oxide layer is larger than that of the first part on the buried oxide layer or the orthographic projection of the second part on the buried oxide layer overlaps with that of the first part on the buried oxide layer in the thickness direction.