CN118523777A - Shaping algorithm suitable for SDADC modulator capacitance mismatch - Google Patents

Abstract

The invention relates to a shaping algorithm suitable for SDADC modulator capacitance mismatch, which comprises a loop filter, an overflow detection unit, a full sequencing circuit and a comparator to form a basic circuit, and comprises a two-stage integration stage, an overflow detection stage and a sequencing comparison stage. Therefore, a full-ordering algorithm can be introduced, and a second-order mismatch shaping algorithm which can be flexibly applied to a Sigma-Delta modulator adopting an odd number of DAC feedback capacitors is realized. The overflow detection circuit is introduced, so that the risk of overflow of the digital code in actual engineering application of the second-order mismatch shaping algorithm is avoided.

Description

Shaping algorithm suitable for SDADC modulator capacitance mismatch

Technical Field

The invention relates to a mismatch shaping algorithm, in particular to a shaping algorithm applicable to SDADC modulator capacitor mismatch.

Background

Along with the continuous development of the current informatization and intelligence directions, the Sigma-Delta ADC is also widely applied to the fields of precision measurement, industrial measurement, energy exploration, high-fidelity audio, sensor monitoring and the like.

The matching degree of the feedback capacitor in the Sigma-Delta ADC is one of key factors influencing the conversion accuracy of the feedback capacitor. The traditional design at present adopts simple methods of dynamic element matching, data weight averaging and the like to solve the mismatch problem of the feedback capacitor. However, in some high-precision application scenarios, the conventional mismatch shaping algorithm cannot meet the requirements of high-precision analog-to-digital conversion on the signal-to-noise ratio and linearity of the Sigma-Delta ADC. For this reason, a more complex higher-order mismatch shaping algorithm is required to handle the mismatch of the feedback capacitance.

Aiming at the high-precision requirement commonly adopted at present, the principle block diagram of a high-order shaping algorithm based on a selection vector is shown in fig. 9. The choice of the higher order shaping algorithm structure in the design process depends on whether the number of unit cell DACs is odd or even. In a Sigma-Delta modulator with a low order, even numbers of DAC feedback capacitances will generate idle tones when the input signal is zero, i.e. asymmetric quantization levels will introduce non-ideal tones in the frequency spectrum after passing through the modulator, so the DAC feedback capacitances in a Sigma-Delta modulator with a low order are usually all odd numbers. Also, in designs where the number of DAC feedback capacitors is even, a partial ordering algorithm is typically employed to reduce the overhead of the digital circuit, as shown in FIG. 10.

However, the conventional mismatch shaping algorithm of the prior art cannot be applied to Sigma-Delta modulators employing an odd number of DAC feedback capacitances. Meanwhile, the structure has the risk of overflowing the digital codes in practical engineering application. For this reason, the current conventional mismatch shaping algorithm does not work well for SDADC modulator capacitance mismatch.

In view of the above-mentioned drawbacks, the present inventors have actively studied and innovated to create a shaping algorithm suitable for SDADC modulator capacitor mismatch, so as to make the shaping algorithm more industrially useful.

Disclosure of Invention

In order to solve the technical problem, the invention aims to provide a shaping algorithm suitable for SDADC modulator capacitor mismatch.

The invention relates to a shaping algorithm suitable for SDADC modulator capacitance mismatch, wherein: the basic circuit is composed of a loop filter, an overflow detection unit, a full sequencing circuit and a comparator, and comprises the following steps,

Step one, in a two-stage integration stage, a control signal of a DAC of a unit element is integrated twice through a loop filter, so that second-order mismatch shaping is realized;

and step two, in the overflow detection stage, the output of each level of integrator in the loop filter is monitored in real time through an overflow detection unit, and compared with a set measuring range, and corresponding operation is executed according to the preset.

And step three, in the sequencing comparison stage, the second-stage integral output result of the loop filter passing through the overflow detection unit is completely sequenced through a full sequencing circuit, and the weight vector signal is processed through a digital comparator to obtain a DAC control signal in the current period, and the DAC control signal is used for switching the capacitor DAC array.

Further, in the first step, the 7-bit DAC control signal is applied to the capacitor mismatch shaping algorithm of SDADC modulatorsAs input to a loop filterObtaining a first-stage integral resultAnd second-stage integration resultsThe two-stage integral output is sent to the overflow detection unit of the later stage for detection, so that the integral result does not exceed the measuring range limited by the digital code word length.

Further, the above-mentioned shaping algorithm for SDADC modulator capacitor mismatch, wherein in the first step, the following stepsAssuming that the output of the system, the transfer function F (z) and the mismatch noise transfer function MNTF (z) obtained by the loop filter are respectively:

further, in the second step, the overflow detection unit outputs the output of each integrator in the loop filter to the second step of the shaping algorithm suitable for the capacitor mismatch of the SDADC modulator And output ofAnd carrying out real-time monitoring, and if the monitoring result exceeds the preset maximum value, completing the self-subtraction operation in the same clock period, so that the output swing of each integrator does not exceed the given bit width.

Further, the above-mentioned shaping algorithm for capacitor mismatch of SDADC modulator, wherein in the third step, the second stage of the loop filter passing through the overflow detecting unit is integrated by the full sequencing circuit

Outputting the resultPerforming complete sorting to obtain a group of weight vector signals sorted from high to low

Weight vector signal by digital comparatorComparing with the output thermometer code Dout [ n ] of quantizer in Sigma-Delta modulator in current period to obtain DAC control signal in current periodFor switching of the capacitive DAC array.

By means of the scheme, the invention has at least the following advantages:

1. by introducing a full-ordering algorithm, a second-order mismatch shaping algorithm which can be flexibly applied to a Sigma-Delta modulator adopting an odd number of DAC feedback capacitors is realized.

2. The overflow detection circuit is introduced, so that the risk of overflow of the digital code in actual engineering application of the second-order mismatch shaping algorithm is avoided.

3. The circuit generated by the invention has simple structure and easy implementation.

The foregoing description is only an overview of the present invention, and is intended to provide a better understanding of the present invention, as it is embodied in the following description, with reference to the preferred embodiments of the present invention and the accompanying drawings.

Drawings

Fig. 1 is a schematic diagram of the operating region (in dashed boxes) of a basic circuit constructed using the algorithm of the present invention in a two-stage integration stage.

Fig. 2 is a schematic diagram of the operating area (in dashed boxes) of a basic circuit constructed using the algorithm of the present invention in the overflow detection phase.

Fig. 3 is a schematic diagram of the operating region (in dashed boxes) of a basic circuit constructed using the algorithm of the present invention in the rank comparison stage.

Fig. 4 is a schematic diagram of the structure of a loop filter during the implementation of the present invention.

Fig. 5 is a schematic block diagram of a fourth order Sigma-Delta modulator to which the second order shaping algorithm of the present invention is applied.

Fig. 6 is a graph of the simulated fourth order Sigma-Delta modulator output spectrum without using the shaping algorithm.

Fig. 7 is a graph of the output spectrum of a fourth order Sigma-Delta modulator simulated using a first order shaping algorithm.

FIG. 8 is a graph of the output spectrum of a fourth order Sigma-Delta modulator simulated using the present invention.

Fig. 9 is a schematic block diagram of a conventional high-order shaping algorithm based on a selection vector.

Fig. 10 is a schematic diagram of a partial ordering algorithm employed in a design where the number of DAC feedback capacitances is even.

Detailed Description

The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.

The shaping algorithm applicable to SDADC modulator capacitance mismatch as in fig. 1 to 8 is distinguished in that: the circuit comprises a loop filter, an overflow detection unit, a full sequencing circuit and a comparator, and comprises the following steps:

First, as shown in fig. 1, a two-stage integration phase is performed. The control signal of the DAC of the unit element is integrated twice through the loop filter to realize second-order mismatch shaping, and the circuit structure is shown in figure 4. Specifically, 7-bit DAC control signals As input to a loop filterThus, the first-stage integral result can be obtainedAnd second-stage integration resultsAnd then, the two-stage integral output is sent to an overflow detection unit of a later stage for detection, so that the integral result does not exceed the measuring range limited by the digital code word length.

During actual implementation, willAssuming that the output of the system, the transfer function F (z) and the mismatch noise transfer function MNTF (z) obtained by the loop filter are respectively:

It can be seen that the mismatch noise transfer function MNTF (z) exhibits high-pass characteristics and has a second-order shaping effect on the capacitance mismatch error.

Thereafter, as shown in fig. 2, the overflow detection stage. During implementation, the output of each integrator in the loop filter is detected by the overflow detection unitAnd output ofAnd (5) performing real-time monitoring. If the monitoring result exceeds the preset maximum value, the self-subtraction operation is completed in the same clock period. Therefore, the output swing of each stage of integrator can not exceed the given bit width under the condition of not influencing the whole working time sequence. In this way, stability problems that may occur with second order mismatch shaping algorithms can be avoided.

Next, as shown in fig. 3, the comparison phase is ordered. The second-stage integral output result of the loop filter passing through the overflow detection unit (i.e. meeting the preset range) is outputted through the full sequencing circuitPerforming complete sorting to obtain a group of weight vector signals sorted from high to lowThe weight vector signal is then passed through a digital comparatorComparing with the output thermometer code Dout [ n ] of quantizer in Sigma-Delta modulator in current period to obtain DAC control signal in current periodFor switching of the capacitive DAC array.

The working principle of the invention is as follows:

Taking a fourth order Sigma-Delta modulator as an example, the second order mismatch shaping algorithm of the present invention is used, as shown in fig. 5, which shows the basic circuit structure framework after the present invention is applied.

In order to demonstrate the shaping effect of the invention on the capacitance mismatch, the fourth order Sigma-Delta modulator model was simulated in MATLAB software, the capacitance mismatch was set to a normal distributed random amount with a standard deviation of 2%, OSR was set to 32, sampling frequency was set to 20MHz, input signal frequency was set to 5.1879882813khz, and fft point number was set to 65536.

As seen in connection with fig. 6, which is a fourth order obtained by MATLAB simulation without using a shaping algorithm, it matches the Sigma-Delta modulator output spectrum. FIG. 7 is a graph of the output spectrum of a fourth order Sigma-Delta modulator simulated by MATLAB using a first order shaping algorithm. Fig. 8 is a graph of the output spectrum of a fourth order Sigma-Delta modulator obtained by MATLAB simulation using the present invention.

From this, it is apparent that when any error shaping is not employed, the signal-to-quantization noise distortion ratio (SQNR) is 53.5dB, and the effective number of bits (ENOB) is 8.59 bits. After first-order shaping is used, the SQNR is 88.0dB, the 34.5dB is improved, the ENOB is 14.32bit, and the 5.73bit is improved. After the scheme of the invention is adopted, the SQNR is 94.6dB, which is improved by 6.6dB compared with the first-order shaping, the ENOB is 15.42bit, which is improved by 1.1bit compared with the first-order shaping.

Meanwhile, as can be found by comparing fig. 7 and fig. 8, the shaping effect of the mismatch noise in the middle and low frequency bands is improved by 20dB/dec by adopting the simulation result of the invention, and the second-order shaping effect of the capacitor mismatch is realized.

As can be seen from the above text expressions and the accompanying drawings, the invention has the following advantages:

1. by introducing a full-ordering algorithm, a second-order mismatch shaping algorithm which can be flexibly applied to a Sigma-Delta modulator adopting an odd number of DAC feedback capacitors is realized.

2. The overflow detection circuit is introduced, so that the risk of overflow of the digital code in actual engineering application of the second-order mismatch shaping algorithm is avoided.

3. The circuit generated by the invention has simple structure and easy implementation.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and it should be noted that it is possible for those skilled in the art to make several improvements and modifications without departing from the technical principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims (5)

1. The shaping algorithm suitable for SDADC modulator capacitance mismatch is characterized in that: the basic circuit is composed of a loop filter, an overflow detection unit, a full sequencing circuit and a comparator, and comprises the following steps,

Step one, in a two-stage integration stage, a control signal of a DAC of a unit element is integrated twice through a loop filter, so that second-order mismatch shaping is realized;

Step two, in the overflow detection stage, the output of each level of integrator in the loop filter is monitored in real time through an overflow detection unit, and compared with a set measuring range, and corresponding operation is executed according to the preset;

And step three, in the sequencing comparison stage, the second-stage integral output result of the loop filter passing through the overflow detection unit is completely sequenced through a full sequencing circuit, and the weight vector signal is processed through a digital comparator to obtain a DAC control signal in the current period, and the DAC control signal is used for switching the capacitor DAC array.

2. The shaping algorithm for SDADC modulator capacitance mismatch as claimed in claim 1, wherein: in the first step, a 7-bit DAC control signal is usedAs input to a loop filterObtaining a first-stage integral resultAnd second-stage integration resultsThe two-stage integral output is sent to the overflow detection unit of the later stage for detection, so that the integral result does not exceed the measuring range limited by the digital code word length.

3. The shaping algorithm for SDADC modulator capacitance mismatch as claimed in claim 2, wherein: in the first stepAssuming that the output of the system, the transfer function F (z) and the mismatch noise transfer function MNTF (z) obtained by the loop filter are respectively:

4. the shaping algorithm for SDADC modulator capacitance mismatch as claimed in claim 1, wherein: in the second step, the overflow detection unit outputs the output of each stage of integrator in the loop filter And output ofAnd carrying out real-time monitoring, and if the monitoring result exceeds the preset maximum value, completing the self-subtraction operation in the same clock period, so that the output swing of each integrator does not exceed the given bit width.

5. The shaping algorithm for SDADC modulator capacitance mismatch as claimed in claim 1, wherein: in the third step, the second-stage integration output result of the loop filter passing through the overflow detection unit is outputted through the full sequencing circuitPerforming complete sorting to obtain a group of weight vector signals sorted from high to low

Weight vector signal by digital comparatorComparing with the output thermometer code Dout [ n ] of quantizer in Sigma-Delta modulator in current period to obtain DAC control signal in current periodFor switching of the capacitive DAC array.