CN118507366A - Packaging technology of semiconductor integrated circuit - Google Patents
Packaging technology of semiconductor integrated circuit Download PDFInfo
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- CN118507366A CN118507366A CN202410869638.2A CN202410869638A CN118507366A CN 118507366 A CN118507366 A CN 118507366A CN 202410869638 A CN202410869638 A CN 202410869638A CN 118507366 A CN118507366 A CN 118507366A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000012536 packaging technology Methods 0.000 title description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 156
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 156
- 239000010703 silicon Substances 0.000 claims abstract description 156
- 238000004806 packaging method and process Methods 0.000 claims abstract description 34
- 238000003466 welding Methods 0.000 claims abstract description 28
- 238000012858 packaging process Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000005496 eutectics Effects 0.000 claims abstract description 13
- 238000005520 cutting process Methods 0.000 claims abstract description 8
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 238000012360 testing method Methods 0.000 claims description 35
- 238000001746 injection moulding Methods 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 31
- 238000004140 cleaning Methods 0.000 claims description 27
- 238000001514 detection method Methods 0.000 claims description 20
- 238000006243 chemical reaction Methods 0.000 claims description 12
- 239000000428 dust Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 238000000465 moulding Methods 0.000 claims description 8
- 238000005070 sampling Methods 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000003344 environmental pollutant Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 4
- 239000004519 grease Substances 0.000 claims description 4
- 229910000765 intermetallic Inorganic materials 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 claims description 4
- 230000010355 oscillation Effects 0.000 claims description 4
- 231100000719 pollutant Toxicity 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 238000011056 performance test Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 238000007689 inspection Methods 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 109
- 230000009286 beneficial effect Effects 0.000 description 11
- 230000005856 abnormality Effects 0.000 description 3
- 238000009954 braiding Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000009659 non-destructive testing Methods 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012372 quality testing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/607—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of mechanical vibrations, e.g. ultrasonic vibrations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/6715—Apparatus for applying a liquid, a resin, an ink or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dicing (AREA)
Abstract
The invention belongs to the technical field of integrated circuit packaging, and provides a packaging process of a semiconductor integrated circuit, which comprises the following steps: thinning the back surface of the silicon wafer to ensure that the silicon wafer reaches the thickness required by packaging, and obtaining the thinned silicon wafer; cutting the thinned silicon wafer by using a slicing machine to obtain a cut silicon wafer; fixing the cut silicon wafer on a welding plate in the middle of a packaging substrate in a eutectic crystal fixing mode to obtain a fixed silicon wafer; welding the fixed silicon wafer by using a lead bonding mode to obtain a welded silicon wafer; and (5) carrying out plastic packaging on the welded silicon wafer. The invention can effectively package the silicon chip into the integrated circuit, thereby not only improving the automation level of the packaging process, but also ensuring the stability and reliability of the finished product of the integrated circuit and improving the production quality of the integrated circuit.
Description
Technical Field
The present invention relates to the field of integrated circuit packaging technology, and in particular, to a packaging process for a semiconductor integrated circuit.
Background
Semiconductor integrated circuits are manufactured by semiconductor technology from the same semiconductor material as the components of electronic circuits (resistors, capacitors, inductors, etc.) and device transistor sensors, etc., and are interconnected together to form complete circuits and systems with independent functions.
The packaging technology is an important link for ensuring the normal operation of the electronic components, the packaging quality is high and low, the insulation problem of the components is related, and the size, the heat dissipation and the cost of the whole components are influenced.
The patent with application number CN202110146035.6 discloses a packaging process of a semiconductor integrated circuit, wherein grinding is started from the back of a wafer, the wafer is ground to a proper packaging thickness, a blue film is used for pasting to protect a circuit part on the surface of the wafer before dicing, then crystal grains of the wafer are removed through dicing, an adhesive is used for bonding the crystal grains on a welding plate in the middle of a substrate, then a metal electrode on a die is connected with an outer lead on a packaging base through a fine metal wire, ultrasonic welding, hot press welding and metal ball welding are commonly used, a pouring gate is injected into a die cavity in the whole process, the die temperature is kept at about 170 ℃ to 180 ℃, pins are bent to a certain shape through a secondary procedure, the requirement of assembly is met, and then a non-removable word is printed on the packaged substrate, so that the identification and the tracking are convenient; in the technical scheme, the packaging technology of conductive adhesive bonding is adopted, and the packaged semiconductor integrated circuit is poor in thermal stability, easy to deteriorate at high temperature and poor in reliability.
Therefore, it is necessary to provide a packaging process for a semiconductor integrated circuit.
Disclosure of Invention
The invention provides a packaging process of a semiconductor integrated circuit, which can effectively package a silicon chip into the integrated circuit, thereby improving the automation level of the packaging process, ensuring the stability and reliability of the finished product of the integrated circuit and improving the production quality of the integrated circuit.
The invention provides a packaging process of a semiconductor integrated circuit, which comprises the following steps:
thinning the back surface of the silicon wafer to ensure that the silicon wafer reaches the thickness required by packaging, and obtaining the thinned silicon wafer;
Cutting the thinned silicon wafer by using a slicing machine to obtain a cut silicon wafer;
Fixing the cut silicon wafer on a welding plate in the middle of a packaging substrate in a eutectic crystal fixing mode to obtain a fixed silicon wafer;
Welding the fixed silicon wafer by using a lead bonding mode to obtain a welded silicon wafer;
and (5) carrying out plastic packaging on the welded silicon wafer.
Further, the method for fixing the package substrate on the solder board in the middle of the package substrate by utilizing the eutectic die bonding mode comprises the following steps:
Based on a full-automatic die bonder, ultrasonic oscillation is utilized to generate high temperature of about 400-500 degrees, so that a gold-tin alloy layer at the bottom of a pre-obtained eutectic wafer is melted, and a silicon wafer is bonded and fixed on a welding plate in the middle of a packaging substrate.
Further, the welding by using a wire bonding mode comprises the steps of using a high-purity gold wire, copper wire or aluminum wire based on a wire bonding machine, and adopting the wire bonding mode to weld an external contact of a circuit on a silicon chip with a connection point on a lead frame; wherein, the wire bonding mode is thermal ultrasonic bonding.
Further, the method also comprises the step of carrying out quality test on the welded silicon wafer, and specifically comprises the following steps: based on a high-precision push-pull force tester, respectively testing the pull force of the neck part and the tail part of the lead; testing the lead arc height and the thickness of the welding ball based on an optical 3D tester; the intermetallic compounds were subjected to compositional testing based on a grain seedling spectroradiometer.
Further, the welded silicon wafer is subjected to plastic packaging based on an injection molding machine, and the method specifically comprises the following steps:
Placing the frame provided with the welded silicon wafer into an injection molding machine;
Dust collection is carried out on the frame based on dust collection control keys in the injection molding machine;
performing injection molding treatment on the frame subjected to dust collection treatment based on injection molding control keys in the injection molding machine;
and (3) removing leftover materials from the frame after injection molding based on the leftover material removing control key in the injection molding machine, and obtaining the silicon wafer after plastic encapsulation.
Further, the method also comprises the step of molding the plastic packaged silicon wafer based on the rib cutting molding machine to obtain the molded silicon wafer.
Further, the method also comprises the steps of sorting, lettering and braiding the formed silicon wafer based on a full-automatic sorting machine to obtain the packaged integrated circuit.
Further, the method further comprises nondestructive testing of thinned silicon wafers, cut silicon wafers, fixed silicon wafers and welded silicon wafers based on X-ray detection equipment; anomalies or failures in the implementation of the package are monitored based on a scanning electron microscope.
Further, the method further comprises the step of testing the working performance of the packaged integrated circuit, specifically:
the method comprises the steps of configuring a controller, a test power supply, a sampling circuit and an analog-to-digital conversion circuit by using a set test platform; providing constant current for the packaged integrated circuit package pins by using a test power supply;
measuring the pin voltage of the packaged integrated circuit by using the sampling circuit;
acquiring a digital signal corresponding to the pin voltage conversion by using an analog-to-digital conversion circuit;
And the controller is used for judging and comparing the digital signal with the set standard value of the digital signal so as to judge whether the working performance of the integrated circuit is normal or not.
Further, the method further comprises the step of carrying out plasma cleaning on the fixed silicon wafer and the welded silicon wafer to obtain the silicon wafer meeting the requirements, and specifically comprises the following steps:
carrying out plasma cleaning on the fixed silicon wafer and the welded silicon wafer based on plasma cleaning equipment to obtain a silicon wafer to be cleaned;
Scanning to obtain an original image of the silicon wafer to be tested by utilizing a scanning electron microscope and combining a high-definition camera;
Performing target detection of pollutants, greasy dirt or grease based on a set YOLOv target detection model by using a processor in a set test platform to obtain a detection result of cleaning the silicon wafer to be tested; if the detection result meets the cleaning standard set by plasma cleaning, the method is transferred to the subsequent process step.
Compared with the prior art, the invention has the following advantages and beneficial effects: through the packaging technology, the silicon chip can be effectively packaged into the integrated circuit, so that the automation level of the packaging technology is improved, the stability and reliability of the finished product of the integrated circuit are ensured, and the production quality of the integrated circuit is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is a schematic diagram of the steps of a semiconductor integrated circuit packaging process;
FIG. 2 is a schematic diagram showing the steps of performing quality testing on a silicon wafer after being welded;
fig. 3 is a schematic diagram of a step of plastic packaging a bonded silicon wafer.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
The invention provides a packaging process of a semiconductor integrated circuit, as shown in fig. 1, comprising the following steps:
thinning the back surface of the silicon wafer to ensure that the silicon wafer reaches the thickness required by packaging, and obtaining the thinned silicon wafer;
Cutting the thinned silicon wafer by using a slicing machine to obtain a cut silicon wafer;
Fixing the cut silicon wafer on a welding plate in the middle of a packaging substrate in a eutectic crystal fixing mode to obtain a fixed silicon wafer;
Welding the fixed silicon wafer by using a lead bonding mode to obtain a welded silicon wafer;
and (5) carrying out plastic packaging on the welded silicon wafer.
The working principle of the technical scheme is as follows: in order to realize the encapsulation of the semiconductor integrated circuit, firstly, thinning the back surface of the silicon wafer to ensure that the silicon wafer reaches the thickness required by encapsulation, and obtaining the thinned silicon wafer; cutting the thinned silicon wafer by using a slicing machine to obtain a cut silicon wafer; fixing the cut silicon wafer on a welding plate in the middle of a packaging substrate in a eutectic crystal fixing mode to obtain a fixed silicon wafer; then welding the fixed silicon wafer by using a lead bonding mode to obtain a welded silicon wafer; and finally, carrying out plastic packaging on the welded silicon wafer.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the silicon chip can be effectively packaged into the integrated circuit through the packaging process, so that the automation level of the packaging process is improved, the stability and the reliability of the finished product of the integrated circuit are ensured, and the production quality of the integrated circuit is improved.
In one embodiment, the method for fixing the solder bump on the solder board in the middle of the package substrate by using eutectic die bonding comprises the following steps:
Based on a full-automatic die bonder, ultrasonic oscillation is utilized to generate high temperature of about 400-500 degrees, so that a gold-tin alloy layer at the bottom of a pre-obtained eutectic wafer is melted, and a silicon wafer is bonded and fixed on a welding plate in the middle of a packaging substrate.
The working principle of the technical scheme is as follows: in order to fix the silicon chip on the welding plate in the middle of the packaging substrate, the invention is based on a full-automatic die bonder, and ultrasonic oscillation is utilized to generate high temperature of about 400-500 degrees, so that the gold-tin alloy layer at the bottom of the pre-obtained eutectic wafer is melted, and the silicon chip is adhered and fixed on the welding plate in the middle of the packaging substrate.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the full-automatic die bonder is fixed on the welding plate in the middle of the packaging substrate in a eutectic die bonding mode, so that the firmness of silicon chip fixation can be ensured.
In one embodiment, the bonding is performed by using a wire bonding mode, including, based on a wire bonding machine, using high-purity gold wires, copper wires or aluminum wires, and adopting the wire bonding mode to bond external contacts of a circuit on a silicon chip with connection points on a lead frame; wherein, the wire bonding mode is thermal ultrasonic bonding.
The working principle of the technical scheme is as follows: in order to realize the welding of the silicon chip, the invention utilizes a lead bonding mode to weld, specifically, based on a wire bonding machine, utilizes a high-purity gold wire, a copper wire or an aluminum wire to weld an external contact of a circuit on the silicon chip with a connection point on a lead frame in a lead bonding mode; wherein, the wire bonding mode is thermal ultrasonic bonding.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the welding quality and the firmness can be ensured by utilizing the wire bonding mode for welding.
In one embodiment, as shown in fig. 2, the method further comprises the step of performing quality test on the welded silicon wafer, specifically: based on a high-precision push-pull force tester, respectively testing the pull force of the neck part and the tail part of the lead; testing the lead arc height and the thickness of the welding ball based on an optical 3D tester; the intermetallic compounds were subjected to compositional testing based on a grain seedling spectroradiometer.
The working principle of the technical scheme is as follows: in order to ensure that the quality of the welded silicon wafer meets the requirements, the invention also carries out quality test on the welded silicon wafer, and specifically comprises the following steps: based on a high-precision push-pull force tester, respectively testing the pull force of the neck part and the tail part of the lead; testing the lead arc height and the thickness of the welding ball based on an optical 3D tester; the intermetallic compounds were subjected to compositional testing based on a grain seedling spectroradiometer.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the quality of the welded silicon wafer can be tested by utilizing a plurality of test instruments.
In one embodiment, the welded silicon wafer is subjected to plastic packaging based on an injection molding machine, as shown in fig. 3, specifically:
Placing the frame provided with the welded silicon wafer into an injection molding machine;
Dust collection is carried out on the frame based on dust collection control keys in the injection molding machine;
performing injection molding treatment on the frame subjected to dust collection treatment based on injection molding control keys in the injection molding machine;
and (3) removing leftover materials from the frame after injection molding based on the leftover material removing control key in the injection molding machine, and obtaining the silicon wafer after plastic encapsulation.
The working principle of the technical scheme is as follows: in order to realize plastic packaging of the welded silicon wafer, the invention is carried out by using an injection molding machine, and specifically comprises the following steps: placing the frame provided with the welded silicon wafer into an injection molding machine; dust collection is carried out on the frame based on dust collection control keys in the injection molding machine; performing injection molding treatment on the frame subjected to dust collection treatment based on injection molding control keys in the injection molding machine; and (3) removing leftover materials from the frame after injection molding based on the leftover material removing control key in the injection molding machine, and obtaining the silicon wafer after plastic encapsulation.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the plastic packaging of the silicon chip is realized by using the operation of the injection molding machine, so that the quality of the silicon chip after plastic packaging can be ensured.
In one embodiment, the method further comprises the step of forming the plastic packaged silicon wafer based on a rib cutting forming machine to obtain the formed silicon wafer.
The working principle of the technical scheme is as follows: in order to realize the molding treatment of the plastic packaged silicon wafer, the invention is based on a rib cutting molding machine, and the molding treatment is carried out on the plastic packaged silicon wafer to obtain the molded silicon wafer.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the molding machine is utilized to mold the silicon wafer after plastic encapsulation, so that the molded silicon wafer is obtained, and the molding quality of the silicon wafer can be ensured.
In one embodiment, the method further comprises the steps of sorting, lettering and taping the formed silicon wafers based on a full-automatic sorting machine to obtain the packaged integrated circuits.
The working principle of the technical scheme is as follows: in order to realize the processing of sorting, lettering and braiding of the formed silicon wafers, the invention utilizes a full-automatic sorting machine to carry out the full-automatic processing of sorting, lettering and braiding of the formed silicon wafers, so as to obtain the packaged integrated circuit.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the fully-automatic sorting machine is utilized to sort, carve and braid the formed silicon wafers, so that the packaged integrated circuit can be obtained.
In one embodiment, the method further comprises nondestructive testing of the thinned silicon wafer, the cut silicon wafer, the fixed silicon wafer and the welded silicon wafer based on X-ray detection equipment; anomalies or failures in the implementation of the package are monitored based on a scanning electron microscope.
The working principle of the technical scheme is as follows: in order to ensure effective monitoring of abnormality or fault in the packaging implementation process, the invention carries out nondestructive detection on thinned silicon wafers, cut silicon wafers, fixed silicon wafers and welded silicon wafers based on X-ray detection equipment; anomalies or failures in the implementation of the package are monitored based on a scanning electron microscope.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the abnormality and the fault can be found in time by effectively monitoring the abnormality or the fault in the packaging implementation process, and the packaging quality is improved.
In one embodiment, the method further comprises the step of performing a performance test on the packaged integrated circuit, specifically:
the method comprises the steps of configuring a controller, a test power supply, a sampling circuit and an analog-to-digital conversion circuit by using a set test platform; providing constant current for the packaged integrated circuit package pins by using a test power supply;
measuring the pin voltage of the packaged integrated circuit by using the sampling circuit;
acquiring a digital signal corresponding to the pin voltage conversion by using an analog-to-digital conversion circuit;
And the controller is used for judging and comparing the digital signal with the set standard value of the digital signal so as to judge whether the working performance of the integrated circuit is normal or not.
The working principle of the technical scheme is as follows: in order to test the working performance of the packaged integrated circuit so as to ensure that the working performance of the integrated circuit meets the requirements, the invention utilizes a set test platform to configure a controller, a test power supply, a sampling circuit and an analog-to-digital conversion circuit; providing constant current for the packaged integrated circuit package pins by using a test power supply; measuring the pin voltage of the packaged integrated circuit by using the sampling circuit; acquiring a digital signal corresponding to the pin voltage conversion by using an analog-to-digital conversion circuit; and the controller is used for judging and comparing the digital signal with the set standard value of the digital signal so as to judge whether the working performance of the integrated circuit is normal or not.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the working performance of the integrated circuit can be ensured to meet the requirements by carrying out the working performance test on the integrated circuit which is packaged.
In one embodiment, the method further comprises the step of performing plasma cleaning on the fixed silicon wafer and the welded silicon wafer to obtain the silicon wafer meeting the requirements, specifically comprising the following steps:
carrying out plasma cleaning on the fixed silicon wafer and the welded silicon wafer based on plasma cleaning equipment to obtain a silicon wafer to be cleaned;
Scanning to obtain an original image of the silicon wafer to be tested by utilizing a scanning electron microscope and combining a high-definition camera;
Performing target detection of pollutants, greasy dirt or grease based on a set YOLOv target detection model by using a processor in a set test platform to obtain a detection result of cleaning the silicon wafer to be tested; if the detection result meets the cleaning standard set by plasma cleaning, the method is transferred to the subsequent process step.
The working principle of the technical scheme is as follows: in order to obtain the silicon wafer meeting the requirements, the invention carries out plasma cleaning on the fixed silicon wafer and the welded silicon wafer, and specifically comprises the following steps: carrying out plasma cleaning on the fixed silicon wafer and the welded silicon wafer based on plasma cleaning equipment to obtain a silicon wafer to be cleaned; scanning to obtain an original image of the silicon wafer to be tested by utilizing a scanning electron microscope and combining a high-definition camera; performing target detection of pollutants, greasy dirt or grease based on a set YOLOv target detection model by using a processor in a set test platform to obtain a detection result of cleaning the silicon wafer to be tested; if the detection result meets the cleaning standard set by plasma cleaning, the method is transferred to the subsequent process step.
The beneficial effects of the technical scheme are as follows: by adopting the scheme provided by the embodiment, the fixed silicon wafer and the welded silicon wafer are subjected to plasma cleaning based on the plasma cleaning equipment, and the cleaned silicon wafer to be detected is detected, so that the cleaning effect can be ensured.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A packaging process of a semiconductor integrated circuit, comprising:
thinning the back surface of the silicon wafer to ensure that the silicon wafer reaches the thickness required by packaging, and obtaining the thinned silicon wafer;
Cutting the thinned silicon wafer by using a slicing machine to obtain a cut silicon wafer;
Fixing the cut silicon wafer on a welding plate in the middle of a packaging substrate in a eutectic crystal fixing mode to obtain a fixed silicon wafer;
Welding the fixed silicon wafer by using a lead bonding mode to obtain a welded silicon wafer;
and (5) carrying out plastic packaging on the welded silicon wafer.
2. The packaging process of a semiconductor integrated circuit according to claim 1, wherein the fixing on the solder plate in the middle of the package substrate by eutectic die bonding comprises:
Based on a full-automatic die bonder, ultrasonic oscillation is utilized to generate high temperature of about 400-500 degrees, so that a gold-tin alloy layer at the bottom of a pre-obtained eutectic wafer is melted, and a silicon wafer is bonded and fixed on a welding plate in the middle of a packaging substrate.
3. The packaging process of a semiconductor integrated circuit according to claim 1, wherein the bonding by wire bonding comprises bonding external contacts of a circuit on a silicon wafer with connection points on a lead frame by wire bonding using a high-purity gold wire, a copper wire or an aluminum wire based on a wire bonding machine; wherein, the wire bonding mode is thermal ultrasonic bonding.
4. The packaging process of a semiconductor integrated circuit according to claim 1, further comprising performing a quality test on the bonded silicon wafer, specifically: based on a high-precision push-pull force tester, respectively testing the pull force of the neck part and the tail part of the lead; testing the lead arc height and the thickness of the welding ball based on an optical 3D tester; the intermetallic compounds were subjected to compositional testing based on a grain seedling spectroradiometer.
5. The packaging process of a semiconductor integrated circuit according to claim 1, wherein the plastic packaging of the welded silicon wafer is performed based on an injection molding machine, specifically:
Placing the frame provided with the welded silicon wafer into an injection molding machine;
Dust collection is carried out on the frame based on dust collection control keys in the injection molding machine;
performing injection molding treatment on the frame subjected to dust collection treatment based on injection molding control keys in the injection molding machine;
and (3) removing leftover materials from the frame after injection molding based on the leftover material removing control key in the injection molding machine, and obtaining the silicon wafer after plastic encapsulation.
6. The packaging process of a semiconductor integrated circuit according to claim 1, further comprising molding the plastic-packaged silicon wafer based on a dicing saw to obtain a molded silicon wafer.
7. The packaging process of the semiconductor integrated circuit according to claim 1, further comprising the step of carrying out full-automatic processing of sorting, lettering and taping on the formed silicon wafer based on a full-automatic sorting machine to obtain the packaged integrated circuit.
8. The packaging process of a semiconductor integrated circuit according to claim 1, further comprising performing nondestructive inspection on the thinned silicon wafer, the cut silicon wafer, the fixed silicon wafer, and the soldered silicon wafer based on an X-ray inspection apparatus; anomalies or failures in the implementation of the package are monitored based on a scanning electron microscope.
9. The process of claim 1, further comprising performing a performance test on the packaged integrated circuit, in particular:
the method comprises the steps of configuring a controller, a test power supply, a sampling circuit and an analog-to-digital conversion circuit by using a set test platform; providing constant current for the packaged integrated circuit package pins by using a test power supply;
measuring the pin voltage of the packaged integrated circuit by using the sampling circuit;
acquiring a digital signal corresponding to the pin voltage conversion by using an analog-to-digital conversion circuit;
And the controller is used for judging and comparing the digital signal with the set standard value of the digital signal so as to judge whether the working performance of the integrated circuit is normal or not.
10. The packaging process of a semiconductor integrated circuit according to claim 9, further comprising plasma cleaning the fixed silicon wafer and the soldered silicon wafer to obtain a silicon wafer meeting the requirements, specifically:
carrying out plasma cleaning on the fixed silicon wafer and the welded silicon wafer based on plasma cleaning equipment to obtain a silicon wafer to be cleaned;
Scanning to obtain an original image of the silicon wafer to be tested by utilizing a scanning electron microscope and combining a high-definition camera;
Performing target detection of pollutants, greasy dirt or grease based on a set YOLOv target detection model by using a processor in a set test platform to obtain a detection result of cleaning the silicon wafer to be tested; if the detection result meets the cleaning standard set by plasma cleaning, the method is transferred to the subsequent process step.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410869638.2A CN118507366A (en) | 2024-07-01 | 2024-07-01 | Packaging technology of semiconductor integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410869638.2A CN118507366A (en) | 2024-07-01 | 2024-07-01 | Packaging technology of semiconductor integrated circuit |
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