CN118444843A

CN118444843A - Memory management method, electronic device and storage medium

Info

Publication number: CN118444843A
Application number: CN202311517250.8A
Authority: CN
Inventors: 车晓男; 杨刚强; 连登科
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2023-11-13
Filing date: 2023-11-13
Publication date: 2024-08-06

Abstract

The present application relates to the field of memory technologies, and in particular, to a memory management method, an electronic device, and a storage medium. The method can judge the used capacity of each rank in the memory when the electronic equipment containing the memories of a plurality of ranks (such as double ranks, four ranks and the like) is in a specific state (such as a screen-off state, a standby state and a low-power state). And after the judgment result is that the transfer condition is met, transferring the data in at least one rank in the plurality of ranks to the rest of ranks, and stopping the access to the ranks without data storage, thereby reducing the total power supply amount required by the whole memory and the refreshing times of the memory chips.

Description

Memory management method, electronic device and storage medium

Technical Field

The present application relates to the field of memory technologies, and in particular, to a memory management method, an electronic device, and a storage medium.

Background

In the existing electronic devices, synchronous dynamic random access memory (synchronous dynamic random access memory, SDRAM) is generally used as a memory to store codes and data required for running a data processing system such as a central processing unit (central processing unit, CPU). SDRAM has larger capacity and higher read-write speed, and can better meet the requirement of a data processing system on the memory. However, since SDRAM uses capacitive storage, in order to ensure that data is not lost, continuous power supply and refresh are required to be ensured at the time of operation, and thus a large amount of power consumption is generated, which leads to an increase in power consumption of the entire data processing system.

Disclosure of Invention

The embodiment of the application provides a memory management method, electronic equipment and a storage medium, which can solve the problem of larger power consumption during memory operation in electronic equipment such as mobile phones and the like.

In a first aspect, an embodiment of the present application provides a memory management method, applied to an electronic device, where the electronic device includes a memory, and the memory includes a plurality of memory ranks; and the method comprises the following steps: acquiring the used capacity of each memory column in a plurality of memory columns; determining whether the memory meets a transfer condition based on the used capacity and the use threshold of each memory column; if the memory is determined to meet the transfer condition, transferring the data stored in the first memory array in the plurality of memory arrays to the second memory array in the plurality of memory arrays, and limiting access to the first memory array.

The memory refers to a double rate synchronous dynamic random access memory, referred to as DDR for short, and the memory array refers to a plurality of memory chips/particles connected to the same chip select signal (CHIP SELECT) for short, a rank.

It will be appreciated that DDR is typically made up of at least one rank. The larger the number of rank in DDR, the greater the power consumption that DDR consumes. Based on this, in the memory management method according to the embodiment of the present application, when the DDR includes a plurality of ranks, the electronic device determines whether the DDR satisfies a transfer condition based on a size relationship between a used capacity of each rank and a use threshold, and transfers data in at least one rank (first rank) of the plurality of ranks to the remaining ranks (second rank) when it is determined that the transfer condition is satisfied, and then turns off a power supply of the rank (first rank) without data storage to stop access to the rank (first rank) without data storage. Therefore, data transfer is performed under the condition that the DDR meets the transfer condition, the number of the rank used for data storage in the DDR can be reduced, the electric quantity consumed by the DDR is further reduced, the refreshing frequency of the memory chip in the DDR is reduced, and finally the power consumption of the DDR can be reduced and the heating condition of the electronic equipment is relieved.

In addition, in the case where the DDR does not satisfy the transfer condition, the electronic device may start timing, and when the timing satisfies the preset duration, determine whether the used capacity of each rank satisfies the transfer condition based on the usage threshold again. Or under the condition that the DDR does not meet the transfer condition, the electronic device can also detect the battery electric quantity. When the battery power is detected to be smaller than the first power or the battery power is detected to be reduced by the second power, a judgment is made again as to whether the used capacity of each rank satisfies the transfer condition based on the use threshold. The preset duration may be set according to the actual application, and may be, for example, minutes, seconds, milliseconds, or the like. The first power level may be any power level that characterizes the electronic device as being in a low power state, such as 30%,20%,10%, etc., as the application is not limited in this regard. The second electrical quantity may be 3%,5%,10% or any other value, which is not limited by the present application. Therefore, the electronic equipment continues to detect the time or the battery power under the condition that the DDR does not meet the transfer condition, and can ensure that data can be transferred in time when the DDR meets the transfer condition.

In some implementations of the first aspect described above, the usage threshold includes a first usage threshold, and the transfer condition includes that a sum of used capacities of the memory ranks is less than the first usage threshold.

It is understood that when determining whether the DDR satisfies the transfer condition based on the magnitude relation between the used capacity of each rank and the use threshold value, it may be determined whether the sum of the used capacities of each rank is smaller than the first use threshold value, and then it may be determined whether the DDR satisfies the transfer condition based on the determination result. If the sum of the used capacities of the ranks is smaller than the first use threshold, determining that the DDR meets the transfer condition, and after the transfer is completed, completing the data storage task by using fewer ranks. If the used capacity of each rank is larger than or equal to the first use threshold, the current data processing capacity is larger, all ranks in the DDR are needed to store data, and the number of ranks cannot be reduced. The first usage threshold may be set in advance according to the number of ranks in the actual DDR and the memory capacity of each rank. The number of first usage thresholds may be one or more, determined according to the number of rank in the actual DDR.

Thus, when the used capacity of each rank is judged to be smaller, the number of the ranks is reduced, and the data storage task can be completed with less or even single rank memory capacity, so that unnecessary power consumption waste can be reduced.

In some implementations of the first aspect, in a case where the memory capacities of the memory columns are the same, the first usage threshold includes a preset duty ratio of the memory capacities of a first number of memory columns, and the first number is any value smaller than the total number of memory columns.

It is understood that, for the case that the memory capacity of each rank is the same, the first usage threshold may be a preset duty ratio of the memory capacity of the first number of ranks. The preset duty ratio may be any value between 0 and 100%, which is not limited by the present application.

Taking the example that the DDR includes two ranks, where the memory capacities of the two ranks are the same, the first usage threshold may include a preset duty ratio (e.g., 80%) of the memory capacity of the single rank, and at this time, the first number is 1; accordingly, the transfer condition may include that the sum of the used capacities of the two ranks is less than 80% of the memory capacity of the single rank.

Taking DDR as an example, where the four ranks have the same memory capacity, the first usage threshold may include a preset duty cycle (e.g., 80%) of the single rank memory capacity, 80% of the sum of the two ranks memory capacities, and 80% of the sum of the three ranks memory capacities, where the first number is 1,2,3; accordingly, the transfer condition may include three sub-conditions: the sum of the used capacities of the four ranks is less than 80% of the memory capacity of the single rank, the sum of the used capacities of the four ranks is less than 80% of the sum of the memory capacities of the two ranks, and the sum of the used capacities of the four ranks is less than 80% of the sum of the memory capacities of the three ranks; at least one of the three sub-conditions is satisfied, and the DDR is considered to satisfy the transfer condition.

The benefit of setting the preset duty ratio is that the security of the data can be ensured. Specifically, when the used capacity of each rank reaches the preset duty ratio of the memory capacity, the transfer is performed, so that even if the data in one rank is completely transferred to the other rank, the data amount in the other rank is not too large, and the transfer is prevented from being performed when the used capacity of each rank reaches 100% of the memory capacity, and the other rank may be caused to automatically delete part of the data due to the excessively large stored data amount, so that the data loss is caused.

For the case that the memory capacities of the memory columns are not identical, the first usage threshold may be a preset duty ratio of the memory capacity of any rank of the at least two ranks, where any rank may include one rank or a combination of multiple ranks. It is understood that the memory capacity of each rank is not identical, which means that the memory capacities of at least two ranks are not identical.

In some implementations of the first aspect, in a case where the memory capacities of the memory ranks are not identical, the first usage threshold includes a preset duty ratio of a first second number of larger memory capacities in the plurality of memory ranks, and the second number is any value smaller than the total number of memory ranks in the plurality of memory ranks.

It can be appreciated that, for the case that the memory capacities of the ranks are not identical, the first usage threshold may be a preset duty ratio of the first second number of larger memory capacities in the ranks. Wherein the preset duty cycle may be any value between 0 and 100%.

Taking the example that the DDR includes two ranks, where the memory capacities of the two ranks are different, the first usage threshold may be a preset duty ratio (e.g., 80%) of the larger memory capacity in the two ranks, where the second number is 1; accordingly, the transfer condition may include that the sum of the used capacities of the two ranks is less than 80% of the larger memory capacity.

Taking DDR as an example, the four ranks are not identical in memory capacity, the first usage threshold may include a preset duty cycle (e.g., 80%) of the maximum memory capacity, 80% of the sum of the two larger memory capacities, and 80% of the sum of the three larger memory capacities, where the second number is 1,2,3; accordingly, the transfer condition may include three sub-conditions: the sum of the used capacities of the four ranks is less than 80% of the maximum memory capacity, the sum of the used capacities of the four ranks is less than 80% of the sum of the two larger memory capacities, and the sum of the used capacities of the four ranks is 80% of the sum of the larger memory capacities of the three ranks; as long as at least one of the above three sub-conditions is satisfied, DDR can be considered to satisfy the transfer condition.

Therefore, the first use threshold is a preset duty ratio of the first second number of larger memory capacities in the plurality of ranks, that is, the first use threshold is relatively larger, so that the sum of the used capacities of the ranks can more easily meet the transfer condition, thereby ensuring that DDR can timely transfer data and reducing DDR power consumption to the greatest extent.

Furthermore, in some implementations of the first aspect, the first usage threshold may be a fixed value or a dynamically changing value. For example, the first usage threshold may dynamically change according to an actual amount of power, the smaller the actual amount of power, the larger the first usage threshold.

In some implementations of the first aspect, the usage threshold includes a second usage threshold, and the transfer condition includes that a used capacity of each memory rank is respectively smaller than the second usage threshold.

It is understood that when determining whether the DDR satisfies the transfer condition based on the magnitude relation between the used capacity of each rank and the use threshold value, it may be determined whether the used capacity of each rank is smaller than the second use threshold value, and then it may be determined whether the DDR satisfies the transfer condition based on the determination result. If the used capacity of each rank is smaller than the second use threshold value, determining that the DDR meets the transfer condition, and after the transfer is completed, the DDR can complete the data processing task with fewer ranks. If the used capacity of each rank is determined to be greater than or equal to the second use threshold, the used capacity of at least one rank is determined to be greater than or equal to the second use threshold, which indicates that the current data processing capacity is greater, all ranks in the DDR are required to store the data, and the number of ranks cannot be reduced. The second usage threshold may be set according to the number of ranks in the actual DDR and the memory capacity of each rank.

In some implementations of the first aspect, where the memory capacities of the memory ranks are the same, the second usage threshold includes a third number of sub-thresholds, and the sub-thresholds range from a preset duty cycle of the memory capacities of the individual memory ranksWherein N is the total number of memory ranks in the plurality of memory ranks, and the third number is any number less than the total number of memory ranks in the plurality of memory ranks.

It will be appreciated that for the case where the memory capacity of each rank is the same, the second usage threshold may include a third number of sub-thresholds ranging from a preset duty cycle of the memory capacity of a single rankHere, the preset duty ratio may be any value between 0 and 100%.

Taking the example that the DDR includes two ranks, where the memory capacities of the two ranks are the same, the second usage threshold may include 1 sub-threshold, where the range of the sub-threshold is 1/2 of the preset duty ratio (e.g., 80%) of the memory capacity of the single rank, and at this time, the third number is 1; correspondingly, the transfer condition may include that the sum of the used capacities of the two ranks is less than 40% (80% by 0.5) of the memory capacity of the single rank.

Taking the example that DDR includes four ranks with the same memory capacity, the second threshold may include two sub-thresholds, the range of which is the preset duty cycle (e.g., 80%) of the memory capacity of a single rankFor example, the two sub-thresholds may be 20% (80% ×0.25) and 40% (80% ×0.5) of the single rank memory capacity; at this time, the third number is 2; accordingly, the transfer conditions may include: the used capacity of the four ranks is less than 20% of the single rank memory capacity or 40% of the single rank memory capacity, respectively.

It is understood that DDR is considered to satisfy the transfer condition when the used capacity of each rank is smaller than any one of the third number of sub-thresholds, respectively. Wherein each rank may be less than a different sub-threshold.

In addition, for the case that the memory capacities of the respective ranks are not identical, the second usage threshold may be a preset duty ratio of the memory capacity of any rank of the plurality of ranksHere, any rank may include one rank or a combination of a plurality of ranks. In particular, the second usage threshold may be a preset duty cycle of the maximum memory capacity

Thus, when the second usage threshold is the preset duty ratio of the middle single rank or the maximum memory capacityIn this case, it is ensured that at least one rank of data can be completely transferred to the rank with the maximum memory capacity. When the second usage threshold is single rank or the preset duty ratio of the maximum memory capacityIn this case, the data of N-1 rank can be stored in one rank, so as to reduce the memory power consumption to the greatest extent.

In some implementations of the first aspect described above, the preset duty cycle is 80%.

It will be appreciated that 80% is a value summarized according to practical experience, and in different applications, the preset duty ratio may be greater or less than 80%, for example, the preset duty ratio may be 85% or 75% to achieve the effect of guaranteeing the integrity and safety of the data in the DDR.

In some implementations of the first aspect, after the DDR finishes transferring the data, the first memory array is in a closed state, and if the electronic device detects new data to be stored, the first memory array may be restarted to store the new data to be stored; or the electronic equipment can also determine whether to restart the first memory array based on the judgment of the DDR residual capacity and the battery electric quantity; or the electronic equipment can also carry out cold-hot separation on stored data in the DDR, delete cold gate data in the stored data, and then store new data to be stored, so that the storage requirement of the new data is met, the first memory array is not required to be restarted, and the increase of DDR power consumption can be avoided.

In addition, if the data transfer of the DDR is forcibly triggered, for example, the data transfer of the DDR is triggered based on a response to a user operation, even if the electronic device detects new data to be stored, the electronic device may directly discard the new data to be stored without saving, so as to preferentially implement the user operation and ensure user experience.

In some implementations of the first aspect, the memory includes two memory ranks, and the memory management method further includes: one of the two memory rows is randomly used as a first memory row, and the other memory row is used as a second memory row.

It will be appreciated that if the electronic device determines that the DDR satisfies the transfer condition, the data in at least one rank (first rank) may be transferred to the remaining ranks (second ranks). Here, the first memory rank refers to a memory rank transmitting transfer data, and the second memory rank refers to a memory rank receiving transfer data. Taking the example that the DDR includes two ranks, the electronic device may randomly use any one rank of the two ranks as a first memory rank, use the other rank as a second memory rank, and then transfer the data in the any one rank to the other rank.

In this way, the data transfer can be accomplished quickly and easily in a random manner.

In some implementations of the first aspect, the memory includes two memory ranks, and the memory management method further includes: according to the size relation of the used capacity of each memory column, the memory column with smaller used capacity of the two memory columns is used as a first memory column, and the memory column with larger used capacity of the two memory columns is used as a second memory column.

It can be understood that the electronic device may transfer the data in the rank with smaller used capacity to the rest of the ranks according to the size of the used capacity of each rank. Taking the DDR as an example, the electronic device may take the rank of the two ranks that has used the smaller capacity as the first memory rank, take the rank of the two ranks that has used the larger capacity as the second memory rank, and then transfer the data in the first memory rank to the second memory rank. Thus, the data quantity to be transferred can be reduced, and the data transfer risk is reduced.

In some implementations of the first aspect, the memory includes two or more memory ranks, and the memory management method further includes: a second memory rank is determined based on a sum of the used capacities of the memory ranks and based on a magnitude relationship between the memory capacities of the memory ranks.

It will be appreciated that, in the case where the DDR includes a plurality of ranks, when performing data transfer, the electronic device may determine which rank is used as the first memory rank and which rank is used as the second memory rank according to the sum of the used capacities of the ranks and the size relationship between the memory capacities based on the ranks.

In some implementations of the first aspect, the memory includes four memory ranks, and the size relationship between the memory capacities of the memory ranks includes the memory capacities of each of the four memory ranks arranged in order from small to large; determining a second memory rank based on a sum of the used capacities of the memory ranks and based on a magnitude relationship between the memory capacities of the memory ranks, comprising: if the sum of the used capacities of the memory columns is smaller than the memory capacity of the first bit of the sequence, selecting one memory column from the four memory columns as a second memory column; or if the sum of the used capacities of the memory columns is greater than or equal to the memory capacity of the first bit of the sequence and is smaller than the sum of the memory capacities of the first two bits of the sequence, selecting two memory columns from the four memory columns as a second memory column; or if the sum of the used capacities of the memory columns is greater than or equal to the sum of the capacities of the first two bits of the sequence and is smaller than the sum of the capacities of the first three bits of the sequence, selecting three memory columns from the four memory columns as a second memory column.

It will be appreciated that, taking the DDR as an example, the electronic device may sort the memory capacities of the ranks from small to large, and then compare the sum of the used capacities of the ranks with the memory capacity of the first rank, the sum of the memory capacities of the first two ranks, and the sum of the memory capacities of the first three ranks in order. If the sum of the used capacities of the ranks is smaller than the memory capacity of the first bit of the sequence, which means that the current data size is smaller, and a single rank can finish the data storage task, one rank is selected from the four ranks as a second memory row, and the other three ranks can be all used as the first memory row, so that DDR only works by using a single rank, and DDR power consumption can be reduced to the greatest extent. If the sum of the used capacities of the ranks is greater than or equal to the memory capacity of the first rank and less than the sum of the memory capacities of the two ranks before ranking, two memory ranks are selected from the four ranks as the second memory ranks, and the other two ranks are used as the first memory ranks, namely, the data in the two ranks is transferred to the other two ranks. Or if the sum of the used capacities of the ranks is greater than or equal to the sum of the memory capacities of the first two digits and is smaller than the sum of the memory capacities of the first three digits, selecting three ranks from the four ranks as a second memory rank, and the other rank as a first memory rank, namely transferring the data in only one rank; thus, under the condition that the DDR memory capacity can meet the data storage requirement, the DDR can work with double rank or three ranks so as to reduce the DDR power consumption.

In some implementations of the first aspect, acquiring a used capacity of each of a plurality of memory ranks includes: detecting that the electronic equipment is in a transfer state, and acquiring the used capacity of each memory column in a plurality of memory columns; the transition state comprises at least one of a screen-off state, a low-power state and a standby state.

It can be understood that when the electronic device is in a specific state such as a screen-off state, a standby state, or a low-power state, the general data processing task is less, the required data amount to be stored is smaller, and the memory capacity of a single rank can be satisfied. Therefore, the electronic device can detect whether the device is in the transition state, and when the device is detected to be in the transition state, the used capacity of each rank can be acquired, and then the used capacity of each rank is judged. Therefore, the electronic equipment can timely reduce the number of the rank used for data storage in the DDR under the condition of smaller memory capacity requirement, so that the power consumption of the whole machine is reduced.

It can be understood that, in addition to the screen-off state, the standby state, and the low-power state, the electronic device can be considered to be in the transition state if the electronic device is in a state with less demand for memory capacity and a need for saving power consumption.

In some implementations of the first aspect, the memory management method further includes: detecting a first instruction for indicating data transfer to the memory, transferring data stored in a first memory array in a plurality of memory arrays to a second memory array in the plurality of memory arrays, and restricting access to the first memory array.

It will be appreciated that the electronic device may also in some specific cases force the triggering of the data transfer process. For example, the electronic device may respond to the first instruction triggered by the user to force data transfer, that is, directly transfer the data in the first memory array to the second memory array, without determining whether the transfer condition is satisfied. The first instruction includes, but is not limited to, a first voice instruction, a first touch instruction or an instruction triggered by a user through other operation modes, and the specific form can be flexibly adjusted according to practical application.

In some implementations of the first aspect, the memory management method further includes: and detecting that the battery power of the electronic equipment is lower than a power threshold, transferring data stored in a first memory array in the plurality of memory arrays to a second memory array in the plurality of memory arrays, and limiting access to the first memory array.

As previously mentioned, the electronic device may also in some specific cases force the triggering of the data transfer process. Here, the electronic device may detect the battery power in real time, and when the battery power is detected to be lower than the power threshold, the electronic device may force data transfer, that is, directly transfer the data in the first memory array to the second memory array, without determining whether the transfer condition is satisfied. The power threshold may be any power value that characterizes the electronic device in a low power state, such as 30%,20%,10%, etc., as the application is not limited in this regard. Therefore, in the low-power state, DDR power consumption can be reduced by forcibly transferring data, so that the endurance time of the electronic equipment is prolonged.

In a second aspect, an embodiment of the present application provides an electronic device, including: one or more processors; one or more memories; the one or more memories store one or more programs that, when executed by the one or more processors, cause the electronic device to perform the memory management method of the first aspect described above.

In a third aspect, an embodiment of the present application provides a computer readable storage medium, where instructions are stored, which when executed on a computer, cause the computer to perform the memory management method of the first aspect.

Drawings

FIG. 1A is a schematic diagram of a first DDR structure provided in an embodiment of the application;

FIG. 1B is a schematic diagram of a second DDR configuration provided in an embodiment of the application;

FIG. 1C is a schematic diagram of a single rank memory according to an embodiment of the present application;

FIG. 1D is a schematic diagram of a dual rank memory according to an embodiment of the present application;

fig. 2 is a schematic diagram of a hardware structure of a mobile phone according to an embodiment of the present application;

FIG. 3 is a flow chart of a memory management method according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a third DDR configuration provided in accordance with an embodiment of the application;

FIG. 5 is a first embodiment of a memory management method according to an embodiment of the present application;

FIG. 6 is a diagram illustrating a second embodiment of a memory management method according to an embodiment of the present application;

FIG. 7 is a third embodiment of a memory management method according to an embodiment of the present application;

FIG. 8 is a fourth embodiment of a memory management method according to an embodiment of the present application;

fig. 9 is a schematic diagram of a display page in an electronic device according to an embodiment of the present application;

Fig. 10 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Illustrative embodiments of the application include, but are not limited to, memory management methods, electronic devices, and storage media, embodiments of which are described in further detail below with reference to the accompanying drawings.

For a clearer understanding of the aspects of the present application, related art terms to which the present application relates will be explained first.

Random access memory (random access memory, RAM): RAM may be used as an internal memory, also called main memory, for directly exchanging data with the CPU. It can be read and written at any time, but is fast, usually as a temporary data storage medium for an operating system or other running program. RAM can be divided into static random access memory and dynamic random access memory (dynamic random access memory, DRAM). The DRAM further includes SDRAM and double rate synchronous dynamic random access memory (doubledata rate synchronous dynamic random access memory, DDR SDRAM) and the like.

Among them, the DRAM can hold data only for a short time. The DRAM uses a capacitor to store data, and since the capacitor gradually leaks, the capacitor must be refreshed once at intervals, the refresh is to recharge the capacitor stored 1 for a given period to supplement the leaked charge, and the expression refresh is to periodically perform a read-out and a write-in operation on the capacitor. If the memory cell is not refreshed, the stored information is lost.

The SDRAM can keep the same clock frequency as the system clock of the front-end bus of the CPU, the CPU can send out a clock signal in each clock period, and the SDRAM can respond on the rising edge or the falling edge of the clock signal to read or write data.

DDR SDRAM: hereinafter referred to as DDR. Compared with SDRAM, DDR SDRAM can only transmit data once in one clock period, DDR can transmit data twice in one clock period, and data are transmitted once in rising edge and falling edge respectively, so that double data rate can be realized without increasing clock frequency.

DDR is physically soldered onto a circuit board from a number of memory chips/particles (e.g., DRAM chips), where the memory chips/particles connected to the same chip select signal (CHIP SELECT) belong to the same rank (rank). rank is also known as physical Bank (P-Bank). Currently, the DDR may be single rank DDR, double rank DDR, quad rank DDR, etc. according to the different numbers of ranks.

The bit width of a single rank is equal to the sum of the bit widths of all memory chips in the rank. And, the bit width of a single rank needs to be consistent with the bit width of the CPU so that the CPU can access each rank independently. When the CPU accesses each rank, all memory chips in the rank can be accessed simultaneously.

Taking a 64-bit (bit) CPU as an example, in order to fully utilize the processing performance of the CPU, the bit width of the data/control bus between the CPU and the DDR is also 64 bits, that is, the CPU can send or read 64 bits of data to or from the DDR in one clock cycle, and correspondingly, the bit width of each rank should also be 64 bits. If the bit width of a single memory chip is less than 64 bits, for example, the bit width of the single memory chip is only 4 bits, 8 bits, 16 bits or 32 bits currently, a plurality of memory chips need to be connected in parallel to form a data set with the bit width of 64 bits, so as to form a rank to interact data with the CPU. For example, for a 16bit memory chip, 4 16bit memory chips need to be connected in parallel to meet the operation of a 64bit CPU (16 bit×4=64 bit), and these 4 memory chips are called rank together in parallel.

In order to ensure communication with the CPU, each DDR at least comprises a rank, and each rank comprises a plurality of memory chips. Fig. 1A and 1B exemplarily provide two DDR structures, each of which is exemplified by 64 bits per rank. Fig. 1A shows a single rank memory, where each memory chip in fig. 1A is 8 bits, and a rank is formed by connecting 8 memory chips (i.e. chip0, chip1, chip2 … … chip 7) in parallel on a circuit board, and the bit width of the rank is 8×8bit,64bit. Fig. 1B shows a dual rank memory. Specifically, the DDR shown in fig. 1B is composed of 8 16-bit memory chips, wherein the upper layer 4 memory chips (i.e., chip8, chip9, chip10, chip 11) are connected in parallel to form rank0, and the lower layer 4 memory chips (i.e., chip12, chip13, chip14, chip 15) are connected in parallel to form rank1, where the bit widths of rank0 and rank1 are both 4×16bit, i.e., 64bit, and the bit width of the entire DDR is the sum of the bit widths of two ranks of rank0 and rank1, i.e., 128bit. However, since the data channel between the DDR and the CPU is only 64 bits wide, the CPU can only access one rank in the dual ranks at a time, for example, the CPU can only access the rank0 or rank1 at a time.

The following describes the operation modes of the above-mentioned single rank memory and dual rank memory with reference to fig. 1C and 1D, respectively. As shown in fig. 1C, the single rank memory includes only one rank a, and only one chip select signal (signal cs_a) is required to control the rank a. When the CPU sends out the chip select signal cs_a, which indicates that rank a is selected, the CPU may access the total nominal capacity of the memory through the data/control bus, where the total nominal capacity of the memory is the memory capacity of rank a. As shown in fig. 1D, the dual rank memory requires two chip select signals (signal cs_a and signal cs_b) to control two ranks (rank a and rank B), respectively. When the chip selection signal sent by the CPU is a signal CS_a, the chip selection signal represents that the rank A is selected, the memory capacity of the rank A can be used at the moment, and the CPU can access the rank A; when the chip selection signal sent by the CPU is a signal CS_b, the selected rank B is indicated, the memory capacity of the rank B can be used at the moment, and the CPU can access the rank B; that is, the CPU can only access the memory capacity of rank a or the memory capacity of rank B through the data/control bus at a time. Here, the sum of the memory capacities of rank a and rank B is equal to the total nominal capacity of the memory. Currently, in order to ensure a certain memory capacity, electronic devices such as mobile phones and tablet computers often employ dual rank memory as shown in fig. 1B.

As described above, DDR is mostly used as a memory in electronic devices to store codes and data required for CPU operation, and dual rank is mostly used in current memory. Although the dual rank can increase the nominal capacity of the memory in the electronic device, the number of memory chips is increased, or the bit width of a single memory chip is increased, the increase of the number of memory chips directly leads to the increase of power supply and refresh times, and the increase of the bit width of the single memory chip also leads to the increase of the refresh bit number, thereby increasing the memory power consumption and exacerbating the heating condition of the electronic device. Taking a mobile phone as an example, the power consumption of the dual-rank memory in the whole machine is relatively large and is about 10% -20%, so that it is highly desirable to reduce the power consumption of the memory in the electronic devices such as the mobile phone.

Based on this, the embodiment of the application provides a memory management method. The method judges the used capacity of each rank in the memory when the electronic equipment containing the memories of a plurality of ranks (such as double ranks, four ranks and the like) is in a specific state (such as a screen-off state, a standby state and a low-power state). And after the judgment result is that the transfer condition is met, transferring the data in at least one rank in the plurality of ranks to the rest of ranks, and stopping the access to the ranks without data storage, thereby reducing the total power supply amount required by the whole memory and the refreshing times of the memory chips.

It is understood that in some embodiments, the transfer condition may be that the sum of the used capacities of the ranks in the memory is smaller than the first usage threshold, or that the used capacity of at least N ranks in the memory is smaller than the second usage threshold. The transfer condition may also be a combination of one or more of the above.

The first usage threshold and the second usage threshold need to be determined based on the memory capacity of each rank, which is specifically described below and not described herein.

Take an electronic device with dual rank memory as an example. When the electronic equipment enters a specific state such as a screen-off state, a standby state, a low-power state and the like, the used capacity of each of the first rank and the second rank in the double ranks is detected, and the used capacity of the first rank and the second rank is judged. After the judgment result satisfies the first transfer condition that the sum of the used capacity of the first rank and the used capacity of the second rank is smaller than the first use threshold value, and/or the second transfer condition that both the used capacity of the first rank and the used capacity of the second rank are smaller than the second use threshold value, the data in the first rank may be transferred to the second rank, or the data in the second rank may be transferred to the first rank. For example, assuming that the memory capacity of the first rank and the memory capacity of the second rank are the same and are both 8GB, the first usage threshold and the second usage threshold may be 8GB by 0.8, i.e., 6.4GB. Taking the case of transferring the data in the first rank to the second rank as an example, after the data transfer is completed, the access to the first rank is stopped, and the power supply of the first rank is disconnected. Thus, the dual-rank memory can work in a single-rank memory working mode, the rank number is reduced under the scene of small memory capacity requirement, namely low bandwidth, the number of used memory chips is reduced, the total power supply amount required by the whole memory and the refresh times of the memory chips are further reduced, and the power consumption of the memory can be obviously reduced.

It can be understood that, in addition to the above-mentioned electronic device being capable of automatically transferring data based on the determination result of the used capacity of each rank in a specific state, the electronic device may also be capable of transferring data in at least one rank of the plurality of ranks in any state in response to the first instruction triggered by the user. That is, in some embodiments, the transfer condition may also be detection of a first instruction indicating a transfer of data to memory.

Before describing the memory management method according to the embodiment of the present application in detail, first, an electronic device mentioned in the embodiment of the present application is described. It can be appreciated that the electronic device in the embodiment of the present application may be an electronic device such as a mobile phone, a computer, a Virtual Reality (VR) device, a tablet computer, a wearable device, an augmented reality (augmented reality, AR) device, a notebook computer, or the like. The form of the electronic device in the embodiment of the application is not particularly limited.

Taking an electronic device as an example of a mobile phone, a schematic diagram of a hardware structure of the mobile phone 10 capable of implementing the method of the present application is described below.

As shown in fig. 2, the mobile phone 10 may include a processor 110, a power module 140, a memory 180, a mobile communication module 130, a wireless communication module 120, a sensor module 190, an audio module 150, a camera 170, an interface module 160, keys 101, a display 102, and the like.

It should be understood that the illustrated structure of the embodiment of the present application is not limited to the specific configuration of the mobile phone 10. In other embodiments of the application, the handset 10 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The processor 110 may include one or more processing units, for example, processing modules or processing circuits that may include a CPU, an image processor (graphics processing unit, GPU), a digital signal processor (DIGITAL SIGNAL processor, DSP), a microprocessor (micro-programmed control unit, MCU), an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor, a programmable logic device (field programmable GATE ARRAY, FPGA), or the like. Wherein the different processing units may be separate devices or may be integrated in one or more processors. A memory unit may be provided in the processor 110 for storing instructions and data. In some embodiments of the present application, the processor 110 may be configured to perform the memory management method of the present application. The memory unit may store instructions related to performing the memory management methods of the present application. The memory 180 may be a dual rank memory, a quad rank memory, or other multi-rank memory.

The power module 140 may include a power source, a power management component, and the like. The power source may be a battery. The power management component is used for managing the charging of the power supply and the power supply supplying of the power supply to other modules. The mobile communication module 130 may include, but is not limited to, an antenna, a power amplifier, a filter, a low noise amplifier (low noise amplify, LNA), and the like. The mobile communication module 130 may provide a solution for wireless communication including 2G/3G/4G/5G, etc. applied to the handset 10. In some embodiments, the mobile communication module 130 and the wireless communication module 120 of the handset 10 may also be located in the same module. The display screen 102 is used for displaying human-computer interaction interfaces, images, videos, and the like. The audio module 150 is used to convert digital audio information into an analog audio signal output, or to convert an analog audio input into a digital audio signal. The audio module 150 may also be used to encode and decode audio signals. The camera 170 is used to capture still images or video.

It should be noted that, the hardware functional components of the mobile phone 10 may be changed according to the needs of the user, and it should be understood that the specific embodiment described above is only one specific implementation manner of the electronic device, and other ways of implementing the embodiments of the present application are also the scope of protection of the present application, which is not repeated herein.

Fig. 3 is a flow chart of a memory management method according to an embodiment of the present application, where the memory management method may be executed by a processor in an electronic device, and a memory of the electronic device includes at least two ranks. As shown in fig. 3, the memory management method may include:

S301: the processor detects a used capacity of each of the at least two ranks.

It may be understood that the memory of the electronic device includes at least two ranks, and the processor needs to detect the used capacity of each rank, where the used capacity of each rank may be the size of the memory that is currently used by each rank, or may be the memory duty cycle that is currently used by each rank.

In some embodiments, as described above, the processor may automatically detect the used capacity of each rank when the electronic device is in a specific state such as a screen-off state, a standby state, or a low-power state, and then determine the used capacity of each rank. In the screen-off state and the standby state, the user does not use the electronic device, the electronic device has less data to be processed or basically has no data to be processed, namely, the processor has less capacity requirement on the memory, usually, the memory capacity of less or even a single rank can be satisfied, and the unnecessary rank only increases unnecessary memory power consumption. In a low-power state, the electronic device is more required to reduce the power consumption of the whole device so as to improve the endurance time of the electronic device.

It can be understood that, in addition to the screen-off state, the standby state, and the low-power state, the processor can automatically detect the used capacity of each rank to execute the subsequent determination under other situations where the capacity requirement of the memory is smaller and power consumption needs to be saved.

In some embodiments, the processor may further perform S301 upon detecting a second instruction triggered by the user. The second instruction is for instructing the processor to detect a used capacity of each of the at least two ranks. The second instruction includes, but is not limited to, a second voice instruction, a second touch instruction, or an instruction triggered by the user through other operation modes. That is, in some embodiments, the transfer condition of the present application may also include detecting a second instruction indicating that the used capacity of each rank in the memory is detected.

302: The processor judges whether the used capacity of each rank in the at least two ranks meets the transfer condition or not, and determines whether the transfer condition is met or not. If the transition condition is satisfied, S303 is executed; otherwise, the flow is ended.

In the embodiment of the present application, the processor may determine the used capacity of each rank in multiple manners, for example, whether the sum of the used capacities of each rank is smaller than the first usage threshold may be determined, or whether the used capacity of each rank is smaller than the second usage threshold may be determined.

The first use threshold and the second use threshold are determined according to the memory capacity of each rank and the number of the ranks.

In some embodiments, if the memory capacity of each rank is the same, the memory capacity of a single rank may be 8gb,12gb,16gb, or the like. The first usage threshold may be a preset duty cycle of the memory capacity of a preset number (first number) of ranks. Wherein, the preset duty ratio can be any value between 0 and 100 percent, and can be particularly 80 percent. Therefore, when 80% of the memory capacity is reached, the data in one rank is not excessively large even if the data in the other rank is completely transferred to the other rank, so that the data can be prevented from being transferred when 100% of the memory capacity is reached, and the data loss caused by the fact that the other rank automatically deletes part of the data due to the excessively large stored data is possibly caused, and therefore, the safety of the data can be ensured by setting the preset duty ratio. The preset number is any number smaller than the rank number in the memory. The second usage threshold may be a preset duty cycle of the memory capacity of a preset number (third number) of ranksWherein, the preset duty ratio is described above, and is not repeated here. N represents the number of rank in the memory, when the second threshold is the preset duty cycle of the single rank memory capacityAnd in the process, the data of at least one rank can be ensured to be transferred to other ranks, so that the memory power consumption is reduced. When the second usage threshold is the preset duty ratio of the single rank memory capacityIn this case, the data of N-1 rank can be stored in one rank, so as to reduce the memory power consumption to the greatest extent.

It will be appreciated that the higher the first and second usage thresholds, the easier the transfer condition is to meet. Based on practical experience, in the dual rank memory, the first use threshold value can be 80% of the memory capacity of a single rank, so that the data security can be ensured, the memory capacity can meet the data processing requirement, and meanwhile, the memory power consumption can not be wasted under the condition of lower used capacity of the dual rank.

In some embodiments, if the memory capacities of the respective ranks are different, the first usage threshold may be a preset duty ratio of the memory capacity of any rank in the at least two ranks, and specifically, the first usage threshold may be a preset duty ratio of the first second number of larger memory capacities in the at least two ranks. The first usage threshold may be a fixed value or a dynamically changing value. For example, the first usage threshold may dynamically change according to an actual amount of power, the smaller the actual amount of power, the larger the first usage threshold. The second threshold value may be a preset duty cycle of the memory capacity of any of the at least two ranksSpecifically, the second usage threshold may be a preset duty ratio of the maximum memory capacity in at least two ranksWhen the second use threshold is the preset duty ratio of the maximum memory capacityIn this case, it is ensured that at least one rank of data can be completely transferred to the rank with the maximum memory capacity. When the second usage threshold is the preset duty ratio of the maximum memory capacityIn this case, the data of N-1 rank can be stored in one rank, so as to reduce the memory power consumption to the greatest extent. The second usage threshold may be a fixed value or a dynamically changing value. For example, the second usage threshold may also be dynamically changed according to the actual electric quantity, and the smaller the actual electric quantity is, the larger the second usage threshold is.

Several different judging modes and the transfer conditions corresponding to each judging mode will be described below, and will not be described in detail here.

In some embodiments, the processor may re-execute S301 after a period of time after ending the flow if the transfer condition is not satisfied. For example, the processor may start timing when the judgment of S302 is no, and again detect the used capacity of each rank when the timing satisfies the preset duration, and judge whether the used capacity of each rank satisfies the transfer condition. Therefore, considering that when the electronic device just enters a specific state such as a screen-off state, a standby state, a low-power state and the like, part of the data processing process is still in progress, the used capacity may still be larger, the transfer condition is not met, and the capacity of the memory can be released after waiting for a period of time, so that the processor can count time when the transfer condition is not met when the processor judges for the first time or continuously for several times, and judge whether the transfer condition is met again when the preset duration is reached. The preset duration may be set according to practical application, and may be, for example, several minutes, several seconds, several milliseconds, etc., which is not limited by the present application.

In some embodiments, if the transfer condition is not satisfied, the processor may further detect a battery level of the electronic device in real time. When the processor detects that the battery power is less than the first power, S301 is re-executed. The first power may be any power value that characterizes a low power state, such as 30%,20%,10%, etc., as the application is not limited in this regard. Or re-executing S301 whenever the processor detects that the battery level decreases by the second level. The second electric quantity may be 3%,5%,10% or any other value, which is not limited by the present application.

S303: the processor controls the memory to transfer data, so that the data in at least one rank is transferred to the rest of the ranks, and the access to the ranks without data storage is stopped.

In the embodiment of the present application, after the processor determines that the used capacity of each rank meets the transfer condition based on the judgment of the used capacity of each rank, the processor may control the memory to transfer data, so that the data in at least one rank is transferred to the rest of the ranks, where there are multiple transfer modes, for example, the processor may control the memory to randomly transfer the data in any rank to the rest of the ranks, or may transfer the data in the rank with a smaller used capacity to the rest of the ranks. The transfer mode will be described below, and is not described in detail here.

It can be understood that, the access to the rank without data storage is stopped, i.e. the power supply of the rank without data storage is disconnected, and the memory chips in the rank do not need to be refreshed periodically, so that the total power supply amount required by the whole memory is reduced, and further, the electric energy of the battery in the power supply module 140 shown in fig. 2 can be saved, and the endurance time of the electronic device is improved.

In addition, as described above, the electronic device may also respond to the first instruction triggered by the user to transfer the data in at least one rank of the plurality of ranks in any state. The first instruction is used for instructing the processor to control the memory to transfer data, so that the data in at least one rank is transferred to the rest of the ranks, and the access to the ranks without data storage is stopped. That is, the processor may directly perform S303 upon detecting the first instruction triggered by the user, without performing S301 and S302 described above. The first instruction may include, but is not limited to, a first voice instruction, a first touch instruction, or an instruction triggered by a user through other operation modes.

In some embodiments, after the processor controls the memory to transfer data, at least one rank in the memory is in a closed state, and if the processor detects new data to be stored, the rank may be restarted to store the new data to be stored. Or the processor may determine whether to re-open the rank based on a size relationship between a data amount of the data to be stored and a remaining capacity of the memory. The remaining capacity of the memory is the sum of the remaining capacities of all the ranks in the on state. Or the processor may determine whether to re-turn on the rank based on a determination of the battery level. When the rank is restarted, 1 or more ranks in the closed state may be started.

For example, when the processor detects new data to be stored, if the remaining capacity of the memory is less than or equal to the data size of the data to be stored, determining the number of the ranks required to be opened according to the data size of the data to be stored; if the residual capacity of the memory is larger than the data quantity of the data to be stored, the rank is not started.

For another example, when the processor detects new data to be stored, if the battery power is smaller than the first power, the rank is not started; if the first electric quantity is larger than or equal to the first electric quantity, determining the number of the rank required to be started according to the data quantity of the data to be stored.

In some embodiments, when the processor detects new data to be stored, the processor may further perform cold-hot separation on the stored data in the memory, delete the cold data in the stored data, and release the memory capacity occupied by the cold data to store the new data to be stored, so that the storage requirement of the new data is satisfied, and the first memory column does not need to be restarted, so that the DDR power consumption can be prevented from being increased.

Specifically, when the processor performs cold-hot separation on the stored data, the stored data can be classified based on indexes such as the use frequency, the storage time, the value and the service requirement of the data, and the data which is low in use frequency, long in storage time, low in value or low in service requirement can be used as cold gate data. It should be noted that the specific cold-hot separation method is not limited in the present application, and in practical application, other data classification manners may be adopted to determine the data to be deleted.

In some embodiments, for the case that the electronic device responds to the first instruction triggered by the user, the memory is controlled to perform data transfer, and at least one rank is in a closed state, even if the electronic device detects new data to be stored, the rank is not restarted, the data to be stored is directly discarded, so that user operation is preferentially realized, and user experience is ensured.

Fig. 4 is a schematic structural diagram of a DDR in an electronic device according to an embodiment of the present application. As shown in fig. 4, the DDR includes 12 memory chips (chip 1, chip 2, chip 3 … … and chip 12), wherein chips 1 to 4 are connected to the same chip select signal (chip select 0 and CS0 shown in the figure), and chips 5 to 12 are connected to the same chip select signal (chip select 1 and CS1 shown in the figure). It will be appreciated that the DDR comprises two ranks, namely a first rank comprising chips 1 through 4 and a second rank comprising chips 5 through 12. The memory capacity of each of the chips 1 to 4 is 16GB, and the bit width is 16 bits, so the bit width of the first rank is 4×16 bits, i.e. 64 bits. The memory capacity of each of the chips 5 to 12 is 16GB and the bit width is 8 bits, so the bit width of the second rank is 8×8 bits, i.e., 64 bits.

The chips of different rank can also be divided into different memory channels, and the different memory channels can be respectively addressed and read and write data by the processor. For example, as shown in fig. 4, chip 1, chip 5 and chip 6 belong to the same memory channel a, chip 2, chip 7 and chip 8 belong to the same memory channel B, chip 3, chip 9 and chip 10 belong to the same memory channel C, and chip 4, chip 11 and chip 12 belong to the same memory channel D. It will be understood that when the CPU selects CS0, chip 1 corresponding to cs0_a, chip 2 corresponding to cs0_b, chip 3 corresponding to cs0_c, and chip 4 corresponding to cs0_d, that is, the chips connecting chip 0 in memory channels a to D, may be accessed at the same time. When the CPU selects CS1, chip 5 and chip 6 corresponding to cs1_a, chip 7 and chip 8 corresponding to cs1_b, chip 9 and chip 10 corresponding to cs1_c, and chip 11 and chip 12 corresponding to cs1_d, that is, the chips connecting chip 1 in memory channels a to D can be accessed at the same time.

In addition, the DDR also comprises other control signals such as a reset signal, a control signal and the like. The reset_n signal in fig. 4, for example, is used to control the RESET of chips 1 through 12. The zq_a_c signal is used to control the calibration of each chip in memory channel a and memory channel C, and the zq_b_d signal is used to control the calibration of each chip in memory channel B and memory channel D. Ck_t_x and ck_c_x are the respective differential clock signals for each memory channel X (X is a/B/C/D). WCK [1:0] _T_X and WCK [1:0] _C_X are the respective write clock signals for each memory channel X. CA [6:0] _X is a respective signal for each memory channel that provides instruction and address inputs. The DQ signal is a respective data signal for each chip, the RDQS signal is a corresponding synchronization signal for a respective read operation for each chip, and the DMI signal is a respective data mask inversion signal for each chip. The specific roles of the above signals can be referred to the related data of the DDR, and the present application will not be described in detail for each signal.

The following describes a specific embodiment of a memory management method according to an embodiment of the present application.

Fig. 5 is a schematic diagram of a memory management method according to an embodiment of the present application. Taking the application to dual rank memory as an example, the memory management method in this embodiment specifically may include:

S501: the processor detects the used capacity of the first rank and the used capacity of the second rank.

Here, S501 may refer to the description of S301 above, and the processor may automatically detect the used capacity of the first rank and the used capacity of the second rank in a specific state such as a screen-off state, a standby state, or a low-power state of the electronic device, or may detect the used capacity of the first rank and the used capacity of the second rank in any state in response to the second instruction.

S502: the processor judges whether the sum of the used capacity of the first rank and the used capacity of the second rank is smaller than a first use threshold. If the sum of the used capacity of the first rank and the used capacity of the second rank is smaller than the first usage threshold, executing S503; otherwise, the flow is ended.

It will be appreciated that the transfer condition here, i.e. the sum of the used capacity of the first rank and the used capacity of the second rank, is smaller than the first usage threshold.

Regarding the setting of the first usage threshold, in some embodiments, in the case where the memory capacities of the first rank and the second rank are the same, the first usage threshold may be 80% of the memory capacity of the single rank. Here, 80% is just one possible example, and as described above, may be any percentage of 0 to 100%. For example, if the memory capacity of a single rank is 8gb,12gb,16gb, etc., the first usage threshold may be 6.4gb,9.6gb,12.8gb, etc.

In some embodiments, in the case where the memory capacities of the first rank and the second rank are different, the first usage threshold may be 80% of the larger memory capacity. Here, 80% is just one possible example, and as described above, may be any percentage of 0 to 100%. The memory capacity of the first rank is 64GB, and the memory capacity of the second rank is 128GB. The first usage threshold may be 128 x 0.8, i.e. 102.4GB.

In some embodiments, the first usage threshold may dynamically change, e.g., the first usage threshold may increase as the actual power of the electronic device decreases, e.g., the first usage threshold may increase linearly or non-linearly as the actual power decreases. Taking the same memory capacity of each rank as an example, the memory capacity of a single rank is 16GB, and at the first moment, the initial value of the first use threshold value can be 0GB, and the actual electric quantity is 100%; at the second moment, the actual electric quantity becomes 80%, and correspondingly, the first use threshold value becomes 3GB; at the nth time, the actual electric power becomes 20%, and correspondingly, the first usage threshold becomes 12.8GB; therefore, the judgment conditions are tightened, and the probability of data transfer is improved, so that the loss generated by the memory can be timely saved in the process of gradually reducing the electric quantity of the electronic equipment.

In some embodiments, if the sum of the used capacity of the first rank and the used capacity of the second rank is greater than or equal to the first usage threshold, the process is ended. After a period of time after the end of the flow, the processor may re-execute S501, either by detecting that the battery power is lower than the first power, or by detecting that the battery power is lower than the second power.

Specifically, the processor may start timing when determining that the sum of the used capacity of the first rank and the used capacity of the second rank is greater than or equal to the first use threshold, and when the timing satisfies the preset duration, the processor detects the used capacity of the first rank and the used capacity of the second rank again, and determines whether the sum of the used capacity of the first rank and the used capacity of the second rank is less than the first use threshold, that is, the steps S501 and S502 are cyclically executed until it is determined that the sum of the used capacity of the first rank and the used capacity of the second rank is less than the first use threshold.

S503: the processor controls the memory to transfer data, so that the data in the first rank is transferred to the second rank, or the data in the second rank is transferred to the first rank, and the access to the rank without data storage is stopped.

In some embodiments, in the case that the memory capacities of the first rank and the second rank are the same, the data in the first rank may be transferred to the second rank, and then access to the first rank is stopped; it is also possible to transfer the data in the second rank to the first rank and then stop the access to the second rank. I.e. randomly transferring data in one rank to another rank. Or transferring the data in the rank with smaller used capacity to another rank according to the used capacity of the first rank and the used capacity of the second rank.

In some embodiments, in the case that the memory capacities of the first rank and the second rank are different, the data transfer manner between the first rank and the second rank is determined based on the magnitude relation between the memory capacity of the first rank and the memory capacity of the second rank based on the sum of the used capacities of the first rank and the second rank.

Specifically, if the sum of the used capacities of the first rank and the second rank is smaller than or equal to the smaller memory capacity in the first rank and the second rank, the data in any rank can be randomly transferred to the other rank; if the sum of the used capacities of the first rank and the second rank is larger than the smaller memory capacity, directly transferring the data in the rank corresponding to the smaller memory capacity to another rank, and stopping the access to the rank corresponding to the smaller memory capacity.

Taking the memory capacity of the first rank as 64GB and the memory capacity of the second rank as 128GB as an example. If the sum of the used capacities (e.g., 60 GB) of the first rank and the second rank is less than or equal to 64GB, the data in the first rank can be transferred to the second rank, then the access to the first rank is stopped, or the data in the second rank can be transferred to the first rank, then the access to the second rank is stopped; if the sum of the used capacities (e.g., 80 GB) of the first rank and the second rank is greater than 64GB, directly transferring the data in the first rank to the second rank, and then stopping the access to the first rank.

It will be appreciated that, since the first rank and the second rank have been determined to satisfy the transfer condition, for example, the sum of the used capacity of the first rank and the used capacity of the second rank is smaller than the first use threshold, when data transfer is performed, the sum of the used capacities of the first rank and the second rank can be directly compared with the memory capacity of the first rank and the memory capacity of the second rank, and no comparison with the preset ratio (e.g., 80%) of the memory capacity of the first rank and the preset ratio of the memory capacity of the second rank is required, so that the determination process can be simplified, the data calculation amount in the data transfer process can be reduced, and the transfer of the memory data can be accelerated.

The embodiments of the memory management method applied to the dual rank memory described above are equally applicable to the quad rank memory or other multi rank memories. Taking a four rank memory as an example, the memory management method of the present application may include the following steps as shown in fig. 6:

S601: the processor detects the used capacity of each of the first, second, third, and fourth ranks.

Here, S601 may refer to the descriptions of S501 and S301 above, and will not be repeated here.

S602: the processor determines whether the sum of the used capacities of the respective ranks is less than a first usage threshold. If the sum of the used capacities of the ranks is smaller than the first usage threshold, S603 is executed; otherwise, the flow is ended.

It will be appreciated that the transfer condition here, i.e. the sum of the used capacities of each of the first, second, third and fourth rank, is less than the first usage threshold.

Regarding the setting of the first usage threshold, in some embodiments, in the case where the memory capacity of each of the first rank, the second rank, the third rank, and the fourth rank is the same, the first usage threshold may include at least one sub-threshold of 80% of the memory capacity of a single rank, 80% of the memory capacity of two ranks, and 80% of the memory capacity of three ranks. Here, 80% is just one possible example, and as described above, may be any percentage of 0 to 100%. For example, if the memory capacity of a single rank is 8GB, taking the example that the first usage threshold includes three sub-thresholds, the three sub-thresholds may be specifically 6.4GB,12.8GB, and 19.2GB.

Taking the example that the first usage threshold includes three sub-thresholds, the transfer condition may be that the sum of the used capacities of the respective ranks is smaller than any one of the three sub-thresholds. The three sub-thresholds are respectively a maximum sub-threshold, a middle sub-threshold and a minimum sub-threshold. That is, the transfer condition includes three sub-conditions, the three sub-conditions being that the sum of the used capacities of the respective ranks is smaller than the minimum sub-threshold, the sum of the used capacities of the respective ranks is equal to or larger than the minimum sub-threshold and smaller than the intermediate sub-threshold, and the sum of the used capacities of the respective ranks is equal to or larger than the intermediate sub-threshold and smaller than the maximum sub-threshold, respectively.

It will be appreciated that in a multi-rank memory, if the memory capacity of each rank is the same, the first usage threshold may include at least one of N-1 sub-thresholds, where N represents the number of ranks. The N-1 sub-thresholds are in turn 80% of the memory capacity of a single rank, 80% … … N-1 rank of the memory capacities of two ranks. Here, 80% is just one possible example, and as described above, may be any percentage of 0 to 100%.

In some embodiments, in the case where the memory capacities of the respective ranks in the first rank, the second rank, the third rank, and the fourth rank are not identical, the first usage threshold may include at least one sub-threshold of 80% of the maximum memory capacity, 80% of the sum of the two larger memory capacities, and 80% of the sum of the three larger memory capacities. Here, 80% is just one possible example, and as described above, may be any percentage of 0 to 100%. For example, if the first rank has a memory capacity of 8GB, the second rank has a memory capacity of 12GB, the third rank has a memory capacity of 16GB, and the fourth rank has a memory capacity of 24GB, and the first usage threshold includes three sub-thresholds, the three sub-thresholds may specifically be 0.8×24GB,0.8×16GB, and 0.8×12GB.

It will be appreciated that in a multi-rank memory, if the memory capacity of each rank is not exactly the same, the first usage threshold may include at least one of N-1 sub-thresholds, where N represents the number of ranks. The N-1 sub-thresholds are in turn 80% of the maximum memory capacity, 80% of the sum of the two larger memory capacities, 80% … … N-1 of the sum of the three larger memory capacities. It should be noted that the N-1 sub-threshold may be 80% of any rank memory capacity, for example, the N-1 sub-thresholds may further include at least one sub-threshold of 80% of the minimum memory capacity, 80% of the sum of two smaller memory capacities, and 80% of the sum of three smaller memory capacities. Here, 80% is just one possible example, and as described above, may be any percentage of 0 to 100%.

In some embodiments, if the sum of the used capacities of the first rank, the second rank, the third rank, and the fourth rank is greater than or equal to the first usage threshold, the process is ended. After a period of time after the end of the flow, the processor may re-execute S601, either by detecting that the battery power is lower than the first power, or by detecting that the battery power is reduced by the second power.

S603: the processor controls the memory to transfer data, so that the data in the other ranks except the target rank are transferred to the target rank, and the access to the rank without data storage is stopped.

The memory capacity of the target rank needs to meet the used capacity of each rank. The target rank of the present application, that is, the second rank of the present application.

In some embodiments, in the case that the memory capacity of each rank in the first rank, the second rank, the third rank, and the fourth rank is the same, the target rank, and the data transfer manner between the ranks are determined based on the sum of the used capacities of the ranks and the memory capacity of the single rank.

Specifically, if the sum of the used capacities of the ranks is smaller than the memory capacity of a single rank, randomly selecting one rank as a target rank, transferring the data in the other three ranks to the target rank, and stopping the access to the three ranks without data storage. And taking the memory capacity of a single rank as 8GB, randomly selecting one rank as a target rank if the sum of the used capacities of the ranks is smaller than 8GB, transferring the data in the three other ranks into the target rank, and stopping the access to the three ranks without data storage.

If the sum of the used capacities of the respective ranks is greater than or equal to the memory capacity of a single rank and is smaller than the memory capacities of two ranks, for example, the sum of the used capacities of the respective ranks (for example, 10 GB) is greater than or equal to 8GB and is smaller than 16GB, then two ranks are randomly used as target ranks, data in the remaining two ranks are transferred to the target ranks, and access to two ranks without data storage is stopped.

If the sum of the used capacities of the respective ranks is greater than or equal to the memory capacities of the two ranks and less than the memory capacities of three ranks, for example, the sum of the used capacities of the respective ranks (for example, 20 GB) is greater than or equal to 16GB and less than 24GB, then three ranks are randomly used as target ranks, data in the remaining one rank is transferred to the target rank, and access to one rank without data storage is stopped.

It will be appreciated that, since the first rank, the second rank, the third rank, and the fourth rank have been determined to satisfy the transfer condition, for example, the sum of the used capacities of each rank in the first rank, the second rank, the third rank, and the fourth rank is smaller than the first usage threshold, when performing data transfer, the sum of the used capacities of each rank can be directly compared with the memory capacity of a single rank, the memory capacities of two ranks, and the memory capacities of three ranks, and there is no need to compare with the preset ratio (e.g., 80%) of the memory capacities of a single rank, the preset ratio of the memory capacities of two ranks, and the preset ratio of the memory capacities of three ranks.

In some embodiments, in the case that the memory capacities of the respective ranks in the first rank, the second rank, the third rank, and the fourth rank are not identical, the target rank and the data transfer manner between the respective ranks are determined based on the sum of the used capacities of the respective ranks and the memory capacities of the respective ranks.

Specifically, the memory capacities of the ranks are sorted from small to large, then the sum of the used capacities of the ranks is sequentially compared with the memory capacity of the first rank, the sum of the memory capacities of the first two ranks and the sum of the memory capacities of the first three ranks, and the target rank is determined according to the comparison result.

Specifically, if the sum of the used capacities of the ranks is smaller than the memory capacity of the first rank, randomly selecting one rank as the target rank, transferring the data in the other three ranks to the target rank, and stopping the access to the three ranks without data storage. Taking the memory capacity of the first rank, the second rank, the third rank and the fourth rank as 8GB,12GB,16GB and 24GB as examples. If the sum of the used capacities of the ranks is less than 8G, randomly selecting one rank as a target rank, transferring the data in the other three ranks to the target rank, and stopping accessing the three ranks without data storage.

If the sum of the used capacities of the ranks is greater than or equal to the memory capacity of the first rank and less than the sum of the memory capacities of the first two ranks, for example, the sum of the used capacities of the ranks (for example, 16 GB) is greater than or equal to 8GB and less than 20B, then two ranks are randomly selected as target ranks, data in the remaining two ranks is transferred to the target ranks, and access to the two ranks without data storage is stopped.

If the sum of the used capacities of each rank is greater than or equal to the sum of the memory capacities of the first two bits and less than the sum of the memory capacities of the first three bits, for example, the sum of the used capacities of each rank (for example, 24 GB) is greater than or equal to 20GB and less than 36GB, then three ranks are randomly used as target ranks, data in the rest of one rank is transferred to the target rank, and access to one rank without data storage is stopped.

It will be appreciated that, since the first rank, the second rank, the third rank, and the fourth rank have been determined to satisfy the transfer condition, for example, the sum of the used capacities of each rank in the first rank, the second rank, the third rank, and the fourth rank is smaller than the first usage threshold, when performing data transfer, the sum of the used capacities of each rank can be directly compared with the sum of the memory capacity of the first rank, the memory capacity of the first two ranks, and the sum of the memory capacity of the first three ranks, and there is no need to compare with the preset duty ratio (e.g., 80%) of the memory capacity of the first rank, the preset duty ratio of the memory capacity of the first two ranks, and the preset duty ratio of the memory capacity of the first three ranks.

It should be noted that, in the above embodiment, a random selection manner is adopted when the target rank is selected, and in other embodiments, a rank with a larger used capacity may be preferentially selected as the target rank, so as to reduce the data transfer amount. The data transfer method applied to the four-rank memory is also applicable to other multi-rank memories, and the application is not repeated.

Fig. 7 is a schematic diagram of another embodiment of a memory management method according to an embodiment of the present application. Taking the application to dual rank memory as an example, the memory management method in this embodiment specifically may include:

s701: the processor detects the used capacity of the first rank and the used capacity of the second rank.

Here, S701 refers to the descriptions of S301 and S501 above, and will not be repeated here.

S702: the processor respectively judges whether the used capacity of the first rank and the used capacity of the second rank are smaller than a second use threshold value. If the used capacity of the first rank and the used capacity of the second rank are both smaller than the second use threshold, S703 is executed; otherwise, the flow is ended.

It will be appreciated that the transfer conditions herein, i.e. the used capacity of the first rank and the used capacity of the second rank, respectively, are smaller than the second usage threshold.

Regarding the setting of the second usage threshold, in some embodiments, where the memory capacity of the first rank and the second rank are the same, the second usage threshold may be 80% of the memory capacity of a single rankSo as to ensure that the data of two ranks can be stored in one rank, and simultaneously ensure the security of the transferred data. Here, 80% is just one possible example, and as described above, may be any percentage of 0 to 100%. For example, if the memory capacity of a single rank is 8gb,12gb,16gb, etc., the second usage threshold may be 3.2gb,4.8gb,6.4gb, etc.

In some embodiments, the second usage threshold may be 80% of the larger memory capacity in the case where the memory capacities of the first rank and the second rank are differentHere, 80% is just one possible example, and as described above, may be any percentage of 0 to 100%. The memory capacity of the first rank is 64GB, and the memory capacity of the second rank is 128GB. The second usage threshold may be 128 x 0.5 x 0.8, i.e. 51.2GB.

In some embodiments, the second usage threshold may be dynamically changed, for example, the second usage threshold may be changed along with the change of the actual power of the electronic device, and in particular, reference may be made to the above embodiment in which the first usage threshold is changed along with the change of the actual power, which is not described herein.

In some embodiments, if the used capacity of the first rank and the used capacity of the second rank are respectively greater than or equal to the second usage threshold, the process is ended. After a period of time after the flow is finished, if the electronic device is still in a specific state such as a screen-off state, a standby state, a low battery, etc., the processor may execute S701 again. That is, the processor may repeatedly perform steps S701 and S702 in a cycle.

Specifically, the processor may start timing when determining that the used capacity of the first rank and the used capacity of the second rank are respectively greater than or equal to the second use threshold, and when the timing satisfies the preset duration, the processor detects the used capacity of the first rank and the used capacity of the second rank again, and determines whether the used capacity of the first rank and the used capacity of the second rank are respectively smaller than the second use threshold, that is, the steps S701 and S702 are performed in a circulating manner until it is determined that the used capacity of the first rank and the used capacity of the second rank are respectively smaller than the second use threshold.

S703: the processor controls the memory to transfer data, so that the data in the first rank is transferred to the second rank, or the data in the second rank is transferred to the first rank, and the access to the rank without data storage is stopped.

Specifically, S703 may refer to the embodiment of S503 above, and will not be described herein.

The embodiments of the memory management method applied to the dual rank memory described above are equally applicable to the quad rank memory or other multi rank memories. Taking a four rank memory as an example, the memory management method of the present application may include the following steps as shown in fig. 8:

S801: the processor detects the used capacity of each of the first, second, third, and fourth ranks.

Here, S801 may refer to the descriptions of S501 and S301 above, and will not be repeated here.

S802: the processor respectively judges whether the used capacity of each rank is smaller than a second use threshold value. If the used capacity of each rank is smaller than the second usage threshold, S803 is executed; otherwise, the flow is ended.

Regarding the setting of the second usage threshold, in some embodiments, where the memory capacity of each of the first, second, third, and fourth ranks is the same, the second usage threshold may comprise 80% of the memory capacity of a single rankAt least one sub-threshold of (a). Here, 80% is just one possible example, and as described above, may be any percentage of 0 to 100%. For example, if the memory capacity of a single rank is 8GB, the second usage threshold may include other sub-thresholds of 8×0.8×4.3GB (2/3) ≡4.3GB, 1.6GB (8×0.8×0.25), and so on.

Taking the example that the second usage threshold includes three sub-thresholds, correspondingly, the above-mentioned transfer condition can be understood that the used capacity of each rank is smaller than any one of the three sub-thresholds. Each rank may be less than a different sub-threshold.

In some embodiments, the second threshold may be 80% of the maximum memory capacity in the case where the memory capacity of each of the first, second, third, and fourth ranks is not exactly the sameHere, 80% is just one possible example, and as described above, may be any percentage of 0 to 100%. For example, if the memory capacity of the first rank is 8GB, the memory capacity of the second rank is 12GB, the memory capacity of the third rank is 16GB, the memory capacity of the fourth rank is 16GB, and the second threshold may be 3.2GB (16×0.8×0.25), 6.4GB (16×0.8×0.5), or other sub-thresholds.

Furthermore, in some embodiments, the second usage threshold may be 80% of the memory capacity of any one of the first, second, third and fourth ranksThe application is not limited in this regard.

In some embodiments, if the used capacity in the first rank, the second rank, the third rank, and the fourth rank is greater than or equal to the second usage threshold, the process is ended. After a period of time after the end of the flow, the processor may re-execute S801, either by detecting that the battery power is lower than the first power, or by detecting that the battery power is reduced by the second power.

S803: the processor controls the memory to transfer data, so that the data in the other ranks except the target rank are transferred to the target rank, and the access to the rank without data storage is stopped.

Specifically, S803 may refer to the embodiment of S603 above, and will not be described herein.

As described above, the electronic device may also transfer the data in at least one rank of the plurality of ranks in any state in response to the first instruction triggered by the user. That is, data stored in a first memory column of the plurality of memory columns is transferred to a second memory column of the plurality of memory columns, and access to the first memory column is restricted.

In some embodiments, the first instruction may be a first touch instruction. An embodiment of transferring data in at least one rank of the plurality of ranks in response to the first touch command is described below with reference to fig. 9.

In addition, in some embodiments, the processor may also transfer data in at least one rank of the plurality of ranks when detecting that the battery level of the electronic device is below the battery level threshold. That is, data stored in a first memory column of the plurality of memory columns is transferred to a second memory column of the plurality of memory columns, and access to the first memory column is restricted.

Fig. 9 is a schematic diagram of a display page 90 in an electronic device according to an embodiment of the present application. In the display page 90, a part of the auxiliary functions (auxiliary function 1, auxiliary function 2 … …) of the electronic device are displayed, and the user can jump through the page by clicking on the option of each auxiliary function, and then set each auxiliary function. Meanwhile, in the display page 90, an option 901 of a low-power single rank mode is further provided, and a corresponding control 901a is provided in the option, so that a user can trigger to generate a first touch instruction by clicking the control 901a, when detecting that the first touch instruction indicates to start the low-power single rank mode, the processor directly controls the memory to enter the low-power single rank mode, does not need to judge the used capacity of each rank, and transfers the data in all the ranks to one rank, thereby realizing the low-power single rank mode. The low power single rank mode uses the rank to interact data with the processor in the memory. It can be understood that the processor does not need to execute S301 to S303, S501 to S503, S601 to S603, S701 to S703, and S801 to S803 in the embodiment when detecting that the first touch instruction indicates that the low power single rank mode is turned on, and may execute S301 to S303, S501 to S503, S601 to S603, S701 to S703, or S801 to S803 when detecting that the first touch instruction indicates that the low power single rank mode is turned off.

Fig. 10 is a block diagram of an electronic device 100 according to an embodiment of the present application, where the electronic device 100 may include two processors (processor 1 and processor 2) and a memory including 4 ranks (rank 1 to rank 4). Each rank has independent clock signal and data processing function, each processor can control the working mode of the four-rank memory through a bus, for example, a Power Down instruction is used for closing a certain rank, a SelfRefresh instruction is used for controlling the rank to carry out self-refreshing operation, and a chip selection signal can be sent through a physical direct connection line through the bus, so that a corresponding memory interface is controlled to wake up a corresponding rank to enter a working state.

Compared with the scheme of reducing DDR power consumption in the related art, the memory management method of the embodiment of the application mainly controls the DDR working mode, such as switching the double-rank working mode to the single-rank working mode, under the specific state of the electronic equipment by limiting the working frequency or the working voltage of the memory, which may affect the data response speed of the memory or cause the memory to lose data, and can reduce the memory power consumption by reducing the number of the used ranks, and is suitable for all the electronic equipment with large-capacity DDR comprising multiple ranks.

Embodiments disclosed for the present application may be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of the application may be implemented as a computer program or program code that is executed on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a DSP, microcontroller, application Specific Integrated Circuit (ASIC), or microprocessor.

The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. Program code may also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described in the present application are not limited in scope by any particular programming language. In either case, the language may be a compiled or interpreted language.

In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on one or more transitory or non-transitory machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer readable media. Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to floppy diskettes, optical disks, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), RAMs, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signal digital signals, etc.) using the internet in an electrical, optical, acoustical or other form of propagated signal. Thus, a machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

In the drawings, some structural or methodological features may be shown in a particular arrangement and/or order. However, it should be understood that such a particular arrangement and/or ordering may not be required. Rather, in some embodiments, these features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of structural or methodological features in a particular figure is not meant to imply that such features are required in all embodiments, and in some embodiments, may not be included or may be combined with other features.

It should be noted that, in the embodiments of the present application, each unit/module mentioned in each device is a logic unit/module, and in physical terms, one logic unit/module may be one physical unit/module, or may be a part of one physical unit/module, or may be implemented by a combination of multiple physical units/modules, where the physical implementation manner of the logic unit/module itself is not the most important, and the combination of functions implemented by the logic unit/module is only a key for solving the technical problem posed by the present application. Furthermore, in order to highlight the innovative part of the present application, the above-described device embodiments of the present application do not introduce units/modules that are less closely related to solving the technical problems posed by the present application, which does not indicate that the above-described device embodiments do not have other units/modules.

It should be noted that in the examples and descriptions of the present application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

While the application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the application.

Claims

1. The memory management method is applied to the electronic equipment and is characterized in that the electronic equipment comprises a memory, and the memory comprises a plurality of memory columns; and

The method comprises the following steps:

Acquiring the used capacity of each memory column in a plurality of memory columns;

Determining whether the memory meets a transfer condition based on the used capacity of each memory column and a use threshold;

And if the memory meets the transfer condition, transferring the data stored in the first memory array in the memory arrays to the second memory array in the memory arrays, and limiting the access to the first memory array.

2. The memory management method of claim 1, wherein the usage threshold comprises a first usage threshold, and the transfer condition comprises a sum of the used capacities of the memory ranks being less than the first usage threshold.

3. The memory management method according to claim 2, wherein the first usage threshold includes a preset duty cycle of the memory capacity of a first number of memory ranks, the first number being any value smaller than the total number of memory ranks, in the case that the memory capacities of the memory ranks are the same.

4. The memory management method according to claim 2, wherein the first usage threshold includes a preset duty cycle of a first second number of larger memory capacities among the plurality of memory ranks, the second number being any value smaller than a total number of memory ranks among the plurality of memory ranks, in a case where the memory capacities of the respective memory ranks are not identical.

5. The memory management method according to any one of claims 1 to 4, wherein the usage threshold includes a second usage threshold, and the transfer condition includes that the used capacity of each memory rank is smaller than the second usage threshold, respectively.

6. The memory management method according to claim 5, wherein the second usage threshold includes a third number of sub-thresholds in a range of a preset duty cycle of the memory capacity of a single memory rank, in a case where the memory capacities of the memory ranks are the sameWherein N is the total number of memory ranks in the plurality of memory ranks, and the third number is any number less than the total number of memory ranks in the plurality of memory ranks.

7. The memory management method according to any one of claims 3,4 and 6, wherein the preset duty cycle is 80%.

8. The memory management method according to claim 2 or 5, wherein the memory includes two memory ranks, the method further comprising:

And randomly taking one memory array of the two memory arrays as the first memory array and the other memory array as the second memory array.

9. The memory management method according to claim 2 or 5, wherein the memory includes two memory ranks, the method further comprising:

and taking the memory column with smaller used capacity of the two memory columns as the first memory column and the memory column with larger used capacity of the two memory columns as the second memory column according to the size relation of the used capacity of each memory column.

10. The memory management method of claim 1, wherein the memory comprises more than two memory ranks, the method further comprising:

The second memory rank is determined based on a sum of the used capacities of the memory ranks and based on a magnitude relationship between the memory capacities of the memory ranks.

11. The memory management method according to claim 10, wherein the memory includes four memory ranks, and the magnitude relation between the memory capacities of the respective memory ranks includes the memory capacities of the respective memory ranks in the four memory ranks arranged in order from small to large;

The determining the second memory rank based on the sum of the used capacities of the memory ranks and based on the magnitude relation between the memory capacities of the memory ranks includes:

if the sum of the used capacities of the memory columns is smaller than the memory capacity of the first bit of the sequence, selecting one memory column from the four memory columns as the second memory column;

or alternatively; if the sum of the used capacities of the memory columns is greater than or equal to the memory capacity of the first bit of the sequence and is smaller than the sum of the memory capacities of the first two bits of the sequence, selecting two memory columns from the four memory columns as the second memory column;

Or alternatively; and if the sum of the used capacities of the memory columns is greater than or equal to the sum of the memory capacities of the first two bits of the sorting and is smaller than the sum of the memory capacities of the first three bits, selecting three memory columns from the four memory columns as the second memory column.

12. The memory management method according to claim 1, wherein the acquiring the used capacity of each of the plurality of memory ranks comprises:

Detecting that the electronic equipment is in a transfer state, and acquiring the used capacity of each memory array in a plurality of memory arrays;

The transition state comprises at least one of a screen-off state, a low-power state and a standby state.

13. The memory management method according to claim 1, wherein the method further comprises:

detecting a first instruction for indicating data transfer to the memory, transferring data stored in a first memory array in the memory arrays to a second memory array in the memory arrays, and limiting access to the first memory array.

14. The memory management method according to claim 1, wherein the method further comprises:

and detecting that the battery power of the electronic equipment is lower than a power threshold, transferring data stored in a first memory array in the memory arrays to a second memory array in the memory arrays, and limiting access to the first memory array.

15. An electronic device, comprising: one or more processors; one or more memories; the one or more memories stores one or more programs that, when executed by the one or more processors, cause the electronic device to perform the memory management method of any of claims 1-14.

16. A computer readable storage medium having stored thereon instructions which, when executed on a computer, cause the computer to perform the memory management method of any of claims 1 to 14.