CN118412381B - Epitaxial design structure, manufacturing method and application of high-performance MOSFET power device - Google Patents
Epitaxial design structure, manufacturing method and application of high-performance MOSFET power device Download PDFInfo
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- CN118412381B CN118412381B CN202410874826.4A CN202410874826A CN118412381B CN 118412381 B CN118412381 B CN 118412381B CN 202410874826 A CN202410874826 A CN 202410874826A CN 118412381 B CN118412381 B CN 118412381B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 238000013461 design Methods 0.000 title claims abstract description 31
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- 229910052698 phosphorus Inorganic materials 0.000 claims description 11
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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Abstract
The invention discloses an epitaxial design structure of a high-performance MOSFET power device, a manufacturing method and application, wherein the epitaxial design structure comprises the following components: doping a first epitaxial layer formed on a substrate with high concentration, wherein the first epitaxial layer blocks diffusion of the substrate; and forming a second epitaxial layer on the first epitaxial layer by ion implantation with a negative slope step-type doping concentration. The high-concentration doping is arsenic doping, and the Rdson of the first epitaxial layer accounts for less than 5% of the total Rdson of the MOSFET power device. The invention adopts the arsenic forming first epitaxial layer and the accurate second epitaxial layer with the negative slope step doping concentration forming, so that the on-resistance of the power MOSFET is reduced while the BV is increased, the DC-DC energy conversion efficiency is improved, the manufacturing cost of the power device is reduced, and the manufacturing method of the second epitaxial layer with the negative slope step doping concentration is compatible with the manufacturing process of the power device, and can be applied to trench type and shielded gate type MOSFET power devices.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to an epitaxial design structure of a high-performance MOSFET power device, a manufacturing method and application.
Background
Power MOSFET devices are commonly used in switching converters and the magnitude of their losses has a direct impact on the performance and efficiency of the switching converter. The loss of the power MOSFET device mainly comprises two parts of conduction loss and switching loss, and the power MOSFET device with the characteristics of low on resistance, low switching loss and the like is usually selected. Low on-resistance results in low on-loss, but for conventional power MOSFET devices, the on-resistance Ron oc BV 2.5 increases simultaneously with a product with a high BV (breakdown voltage).
The doping profile of the epitaxial layer is a critical parameter in determining the performance of the power MOSFET device. Power MOSFET devices typically use a single epitaxial layer, a double epitaxial layer, or even three epitaxial layers, such as trench MOSFET devices and SGT MOSFET devices. N-type MOSFET devices are typically doped using phosphorus as an epitaxial layer. In epitaxial layer designs, a constant doping concentration is typically used for each epitaxial layer.
When a dual epitaxial layer is used in a power MOSFET device, the second grown epitaxial layer is typically part of the drift epitaxial layer in order to further increase the breakdown voltage of the MOSFET. The higher the breakdown voltage, the higher will be the MOSFET Rdson.
Disclosure of Invention
Aiming at the problems, the invention aims to provide a high-performance MOSFET power device epitaxial design structure, a manufacturing method and application thereof, and the MOSFET power device epitaxial design adopts an arsenic-molded first epitaxial layer and a precise negative-slope stepped doping concentration-molded second epitaxial layer, so that the on-resistance of the power MOSFET device is reduced while BV is increased, the DC-DC energy conversion efficiency is improved, and the manufacturing cost of the power device is reduced.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: the epitaxial design structure of the high-performance MOSFET power device is provided with a substrate, wherein a first epitaxial layer and a second epitaxial layer are sequentially arranged on the substrate from inside to outside;
the first epitaxial layer is formed on the substrate in a high-concentration arsenic doping mode, and the first epitaxial layer blocks diffusion of the substrate;
the second epitaxial layer is formed on the first epitaxial layer with a negative slope step doping concentration.
Preferably, the Rdson of the first epitaxial layer is less than 5% of the total Rdson of the MOSFET power device.
A manufacturing method of an epitaxial design structure of a high-performance MOSFET power device comprises the following steps:
S1, sequentially forming a first epitaxial layer doped with high-concentration arsenic, a second epitaxial layer formed by N-type phosphorus ion implantation and a first oxide layer grown on a substrate.
S2, removing the first oxide layer, depositing a hard mask, and etching a groove on the second epitaxial layer.
S3, removing the hard mask, growing a sacrificial oxide layer, and after the sacrificial oxide layer is removed, growing a linear oxide layer on the side wall of the groove and depositing a shielding gate.
S4, depositing a second oxide layer on the shielding gate and etching to form IPO.
And S5, growing a third oxide layer on the side wall of the groove, depositing a control gate, annealing the control gate, and injecting a P-body implant on the surface of the second epitaxial layer and serving as a channel region starting voltage region of the MOSFET power device to form a P-body region.
S6, injecting N+ source implant arsenic to form a source electrode of the device, and depositing a layer of BPSG; and forming a Contact hole in the channel region, connecting the Contact hole with the P-body region through the source electrode, injecting the P-type CT IMPLANT, depositing TI/TIN and metal tungsten as filling contacts to form a Contact hole metal layer, and etching to the surface of the BPSG.
S7, leading the source electrode and the P-body region out to the front source electrode metal layer through Contact, and then forming a back drain electrode metal layer on the back of the MOSFET power device.
Preferably, N-type phosphorus ion implantation with gradually reduced doping concentration is performed on the second epitaxial layer towards the first epitaxial layer, so as to form the second epitaxial layer with the negative slope step-type doping concentration.
The manufacturing method of the epitaxial design structure of the high-performance MOSFET power device is applied to manufacturing of trench type and shielded gate type MOSFET power devices.
The beneficial effects of the invention are as follows: the invention adopts the high-concentration arsenic doped first epitaxial layer and the accurate negative-slope stepped doped second epitaxial layer, so that the on-resistance of the power MOSFET device is reduced while the BV is increased, the DC-DC energy conversion efficiency is improved, and the manufacturing cost of the power device is reduced.
Compared with the structure and the manufacturing process of the conventional epitaxial layer with constant doping concentration, the invention has the following advantages:
1. According to the invention, the arsenic doped buffer layer is used as the first epitaxial layer on the heavily doped N-type substrate of the N-type MOSFET, so that the influence of the change of the heavily doped concentration from the N-type substrate on the second epitaxial layer can be prevented under the condition that the overall on-resistance of the power MOSFET device is basically not influenced, and the stability of the characteristics of the power MOSFET device is ensured.
2. The invention adopts the negative slope step type doping concentration to form the second epitaxial layer, the doping concentration distribution of the second epitaxial layer is accurate, the BV is increased, the Rdson is reduced, and the research and development period is shortened.
3. The epitaxial design structure of the high-performance power MOSFET device is simple in manufacturing process and can be compatible with the traditional power device manufacturing process.
4. The use of highly doped arsenic as the first epitaxial layer reduces the width of the transition region between the first and second epitaxial layers, thereby reducing the contribution of the transition region to the on-resistance of the power MOSFET device.
5. The invention uses the negative slope step doping concentration type doping epitaxial layer as the second layer epitaxial layer of the N-type MOSFET, and compared with the traditional power device, the doping concentration of the channel and the drift region is increased, and the doping concentration of the bottom of the Trench is reduced. The design structure reduces the resistance of the channel and the drift region, and the charge balance is more sufficient due to the low bottom doping concentration, and the increase of the electric field strength results in the increase of the breakdown voltage in the same space charge region.
6. In the bottom region of the trench, the low doping concentration of the second epitaxial layer is beneficial to expansion of the depletion region, so that the output capacitance Coss and the output charge Qoss are reduced, and further, the DC-DC switching efficiency of the power MOSFET device is improved.
7. The invention reduces the on-resistance while increasing BV, and under the same BV, products with the same on-resistance can be designed with smaller chip area, thereby reducing the manufacturing cost of the power device.
8. The manufacturing method of the second epitaxial layer with the negative slope step-type doping concentration disclosed by the invention is compatible with the traditional manufacturing process of the power device, and can be applied to trench type and shielded gate type MOSFET power devices.
Drawings
Fig. 1 is a schematic diagram of a step S1 of a method for manufacturing an epitaxial design structure of a power device according to the present invention.
Fig. 2 is a schematic diagram of step S2 of the method for manufacturing an epitaxial design structure of a power device according to the present invention.
Fig. 3 is a schematic diagram of step S3 of the method for manufacturing an epitaxial design structure of a power device according to the present invention.
Fig. 4 is a schematic diagram of step S4 of the method for manufacturing an epitaxial design structure of a power device according to the present invention.
Fig. 5 is a schematic diagram of step S5 of the method for manufacturing an epitaxial design structure of a power device according to the present invention.
Fig. 6 is a schematic diagram of step S6 of the method for manufacturing an epitaxial design structure of a power device according to the present invention.
Fig. 7 is a schematic diagram of step S7 of the method for manufacturing an epitaxial design structure of a power device according to the present invention.
Fig. 8 is a schematic diagram of step S8 of the method for manufacturing an epitaxial design structure of a power device according to the present invention.
Fig. 9 is an epitaxial doping concentration design diagram of an N-type MOSFET power device according to an embodiment of the invention.
Fig. 10 is a schematic diagram of an N-type MOSFET power device according to an embodiment of the invention.
Fig. 11 is a diagram of an electric field line during breakdown of an N-type MOSFET power device according to an embodiment of the invention.
Fig. 12 is a graph comparing a net doping profile and an electric field profile of a novel epitaxial structure and a conventional epitaxial structure of an N-type MOSFET power device according to an embodiment of the present invention.
In the figure: 1-a first oxide layer; 2-hard mask (hard mask); 3-grooves; 4-linear oxide (liner oxide); 5-shield gate (poly 1 or source poly); 6-IPO (inter poly oxide); 7-a third oxide layer (gate oxide); 8-control gate (gate poly); 9-P-Body (P-Body implant); 10-N+ source implant arsenic; 11-BPSG (Boro-phospho-SILICATE GLASS); 12-P-type CT IMPLANT;13-CT (Contact); 14-front source metal layer (top metal); 15-back drain metal layer (back metal).
Detailed Description
In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
The invention provides a high-performance MOSFET power device epitaxial design structure, which is shown by referring to figures 1-8 and comprises a substrate, wherein a first epitaxial layer and a second epitaxial layer are sequentially arranged on the substrate from inside to outside.
A first epitaxial layer doped with arsenic at a high concentration over the substrate, the arsenic doped first epitaxial layer not being a drift layer for the purpose of blocking diffusion from the heavily doped N-type substrate. The arsenic doping concentration is high enough so that it does not affect the Rdson of the MOSFET power device, and the Rdson of the first epitaxial layer is less than 5% of the total Rdson of the power device.
The first epitaxial layer thickness is determined by the thermal history of the MOSFET fabrication process. Because of the low arsenic diffusion coefficient, the use of highly doped arsenic as the first epitaxial layer reduces the width of the transition region with the second epitaxial layer, described below, thereby reducing the contribution of this transition region to the on-resistance of the device.
The second epitaxial layer is formed on the first epitaxial layer through ion implantation with negative slope step-type doping concentration. Description: the negative slope is a slope in which the doping concentration is gradually reduced toward the first epitaxial layer outside the second epitaxial layer. The second epitaxial layer formed by the negative slope step-type doping concentration can form the required doping concentration morphology by a precise high-energy ion implantation mode so as to achieve high breakdown voltage and low internal resistance (compared with the conventional epitaxial layer with constant doping concentration). The concentration profile of the negative slope stepwise doping concentration is: the doping concentration on the surface of the second epitaxial layer is high, and the doping concentration gradually decreases from the surface of the second epitaxial layer to the inside of the second epitaxial layer until reaching the upper part of the first epitaxial layer. The second epitaxial layer with the negative slope step-type doping concentration has high breakdown voltage, low internal resistance and low output capacitance Coss, meanwhile, the energy conversion efficiency of the MOSFET device in DC-DC is improved, and the chip area design of the same BV product can be smaller due to the low internal resistance, so that the manufacturing cost of a wafer is reduced.
The invention also provides a manufacturing method of the epitaxial design structure of the high-performance MOSFET power device, which comprises the following steps:
S1, as shown in fig. 1-2, sequentially forming a first epitaxial layer doped with high-concentration arsenic, a second epitaxial layer formed by N-type phosphorus ion implantation and a first oxide layer grown on a substrate. Wherein, the arsenic doping is preferably 4e 18-8e18cm-3, and the doping concentration does not affect the Rdson of the MOSFET power device; 250A, the first oxide layer 1 serves as a barrier and protection layer for ion implantation of the second epitaxial layer in step S2, so as not to damage the second epitaxial layer during ion implantation.
S2, ion implantation with the doping concentration gradually reduced is carried out on the second epitaxial layer towards the first epitaxial layer. The ion implantation is P-type phosphorus ion implantation, and the energy is as follows: 300kev to 1Mev; concentration: 1e 12~1e13cm-3.
S3, as shown in FIG. 3, removing the first oxide layer 1, and depositing a hard mask 2 as a barrier layer for etching the subsequent groove 3.
And then determining the position of the trench groove 3 through the photoresist and the hard mask 2, etching the exposed hard mask 2, removing the photoresist, and etching on the epitaxial layer by taking the hard mask 2 as an etching barrier layer to form the trench groove 3.
S4, as shown in FIG. 4, removing the hard mask 2 by wet etching, then growing a sacrificial oxide layer by thermal oxidation, removing the sacrificial oxide layer, forming a clean silicon surface on the side wall of the groove, then growing a linear oxide layer 4 on the side wall of the groove 3 by low-temperature thermal oxidation, and sequentially depositing a shielding gate 5 and etching back by dry etching.
And S5, as shown in FIG. 5, a second oxide layer is continuously deposited above the shielding gate 5 and etched back in a dry etching mode to form the IPO6.
S6, as shown in FIG. 6, a third oxide layer 7 is grown on the side wall of the trench 3, a Chemical Mechanical Polishing (CMP) treatment is performed after a control gate 8 is sequentially deposited, an annealing process is performed on the control gate 8, and a P-body implant is injected on the surface of the second epitaxial layer and used as a channel region opening voltage region of the MOSFET power device to form a P-body region 9, which is preferably boron, and the energy is: 80-300kev; concentration: 1e 12~2e13cm-3.
S7, as shown in FIG. 7, implanting N+ source implant arsenic 10 of N type to form a source electrode of the device; depositing a BPSG11 layer as an isolation layer between the second epitaxial layer surface and metal (front source metal layer 14); a Contact hole is formed in a channel region by using photoresist of a CT mask and is connected with a P-body region 9 through an N+ source implant arsenic 10 region, a P-type CT IMPLANT is formed by high-concentration ion implantation so as to form good ohmic Contact, and then TI/TIN and CT (Contact) 13 are deposited as filling contacts to form a Contact hole metal layer, and then etched to the surface of BPSG11 by a dry etching back mode.
S8, as shown in FIG. 8, the source electrode and the P-body region 9 are led out to the front source electrode metal layer 14 through Contact by utilizing METAL MASK photoresist, and then a back drain electrode metal layer 15 is formed on the back of the device through thinning and back gold processes.
The source and P-body 9 are led out to the front source metal layer 14 by Contact, and then a back drain metal layer 15 is formed on the back of the MOSFET power device by thinning and back gold processes.
In the application, besides the step S2 of performing N-type phosphorus ion injection molding of the second epitaxial layer, preferably, step S2 of performing step phosphorus ion injection and then performing N-type phosphorus ion injection technology with multiple thermal anneals to mold the second epitaxial layer, or step S6 of performing phosphorus element step concentration injection before body implant and then performing body implant and other technologies to form the negative slope step epitaxial layer. The application mainly provides the idea principle of the novel epitaxial layer and a plurality of manufacturing methods thereof, and the rest manufacturing methods are not repeated.
The manufacturing method of the epitaxial design structure of the high-performance MOSFET power device disclosed by the invention can be applied to manufacturing of trench type and shielded gate type MOSFET power devices.
Examples
As shown in fig. 9, an example of the present invention is shown of a first epitaxial layer formed using an arsenic doped buffer layer and a second epitaxial layer formed using a negative slope step doping concentration. An arsenic doped buffer layer is used as the first epitaxial layer on the heavily doped N-type substrate of the N-type MOSFET, the purpose of this layer is to block diffusion from the heavily doped N-type substrate, and the Rdson of this first epitaxial layer is less than 5% of the total Rdson of the power device (for BV 38V devices, the total RSP is 5.28mΩ·mm 2, the arsenic doped epitaxial layer RSP is 0.21mΩ·mm 2, the ratio is about 4% according to the implementation results below). Because the arsenic element has lower diffusion capability, the concentration and thickness of the second layer epitaxial layer cannot be influenced, and meanwhile, the buffer layer can help the second layer epitaxial layer to block diffusion from the heavily doped N-type substrate, so that the stability of the device is ensured. And the high-concentration doped arsenic is used as the first epitaxial layer, so that the width of a transition region between the first epitaxial layer and the second epitaxial layer is reduced, and the contribution of the transition region to the on-resistance of the device is reduced.
The doping of the second epitaxial layer is made into a negative slope step type as shown in fig. 9, and compared with a traditional power device, the doping concentration of a channel and a drift region is increased, and the doping concentration of the bottom of a trench is reduced. The design structure reduces the resistance of the channel and the drift region, and the doping concentration at the bottom of the second epitaxial layer is low, so that the charge balance is more sufficient, the electric field strength of the space charge region is improved, the breakdown voltage is increased, the doping concentration at the bottom of the groove 3 is low, the extension of a depletion layer is facilitated, the output capacitance of the MOSFET is reduced, and the DC-DC energy conversion efficiency of the device is improved.
As shown in fig. 10 to 11, the simulation verification of the present invention is performed to verify the structure of an N-type MOSFET device and the electric field distribution diagram of the device during critical breakdown. Wherein the integrated area under the electric field curve represents the breakdown voltage of this device.
As shown in fig. 12, simulation results of doping concentration and electric field distribution of the novel epitaxial structure designed by the present invention and the conventional epitaxial structure are compared, wherein:
dark solid line: forming a doping curve of the second epitaxial layer by the negative slope step doping concentration;
light solid line: doping profile of constant concentration epitaxial layer;
dark dotted line: forming an electric field distribution curve of the second epitaxial layer by the negative slope step-type doping concentration;
light dotted line: electric field profile of a constant concentration epitaxial layer.
The simulated electric field curves show that the negative slope step epitaxial doping has a higher breakdown voltage than the constant epitaxial doping and that the Rdson of the negative slope step epitaxial doped device is lower because the negative slope step doping concentration profile second epitaxial layer has a higher doping concentration than the constant doped epitaxial layer.
Simulation results show that BV of the negative slope step doped epitaxial layer is 38.2V, and Rsp is 5.27mOhm-mm2; whereas the constant doping epitaxial layer had BV of 36.5V and Rsp of 5.85mOhm-mm2. From simulation results, the negative slope step epitaxial doping was 1.7v higher than the constant epitaxial doping BV, with a 9.9% decrease in rsp, i.e., 9.9% decrease in Rdson. Thus a negative slope stepped epitaxial layer doping profile may provide high BV and low Rdson. A low Rdson means that smaller chip sizes can be designed for the same Rdson device, i.e. reducing the manufacturing costs of the power device.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. The present invention is subject to various changes and modifications without departing from the spirit and scope thereof, and such changes and modifications fall within the scope of the invention as hereinafter claimed.
Claims (4)
1. The epitaxial design structure of the high-performance MOSFET power device is provided with a substrate and is characterized in that a first epitaxial layer and a second epitaxial layer are sequentially arranged on the substrate from bottom to top;
the first epitaxial layer is formed on the substrate in a high-concentration arsenic doping mode, and the first epitaxial layer blocks diffusion of the substrate;
The second epitaxial layer is formed on the first epitaxial layer with a negative slope doping concentration; the negative slope is a slope gradually decreasing in doping concentration from the outer side of the second epitaxial layer towards the first epitaxial layer;
The Rdson of the first epitaxial layer accounts for less than 5% of the total Rdson of the MOSFET power device.
2. The method of fabricating a high performance MOSFET power device epitaxial design structure of claim 1, comprising the steps of:
S1, sequentially forming a first epitaxial layer doped with high-concentration arsenic, a second epitaxial layer formed by N-type phosphorus ion implantation and a first oxide layer grown on a substrate;
s2, removing the first oxide layer, depositing a hard mask, and etching a groove on the second epitaxial layer;
S3, removing the hard mask, growing a sacrificial oxide layer, and after the sacrificial oxide layer is removed, growing a linear oxide layer on the side wall of the groove and depositing a shielding gate;
S4, depositing a second oxide layer on the shielding gate and etching to form IPO;
s5, growing a third oxide layer on the side wall of the groove, depositing a control gate, annealing the control gate, and injecting a P-body implant into the surface of the second epitaxial layer and serving as a channel region starting voltage region of the MOSFET power device to form a P-body region;
S6, injecting N+ source implant arsenic to form a source electrode of the device, and depositing a layer of BPSG; forming a Contact hole in the channel region, connecting the Contact hole with the P-body region through the source electrode, injecting the P-type CT IMPLANT, depositing TI/TIN and metal tungsten as filling contacts to form a Contact hole metal layer, and etching to the surface of BPSG;
s7, leading the source electrode and the P-body region out to the front source electrode metal layer through Contact, and then forming a back drain electrode metal layer on the back of the MOSFET power device.
3. The method for manufacturing the epitaxial design structure of the high-performance MOSFET power device according to claim 2, wherein the method comprises the following steps: and carrying out N-type phosphorus ion implantation with the doping concentration gradually reduced in the direction of the second epitaxial layer towards the first epitaxial layer to form the second epitaxial layer with the negative slope and the step-type doping concentration.
4. Use of a method for manufacturing an epitaxial design structure of a high performance MOSFET power device according to claims 2-3 for manufacturing a trench and a shielded gate MOSFET power device.
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