CN118398492B - Enhanced GaAs HEMT device, manufacturing method thereof and electronic equipment - Google Patents
Enhanced GaAs HEMT device, manufacturing method thereof and electronic equipment Download PDFInfo
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- CN118398492B CN118398492B CN202410852551.4A CN202410852551A CN118398492B CN 118398492 B CN118398492 B CN 118398492B CN 202410852551 A CN202410852551 A CN 202410852551A CN 118398492 B CN118398492 B CN 118398492B
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- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000000151 deposition Methods 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000011265 semifinished product Substances 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910000807 Ga alloy Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention relates to the technical field of semiconductor devices, and provides an enhanced GaAs HEMT device, a manufacturing method thereof and electronic equipment, wherein the method comprises the following steps of: growing an epitaxial layer on a GaAs substrate to form a GaAs epitaxial wafer, wherein the epitaxial layer is of a multi-layer structure, and four layers from top to bottom are a P-type cap layer, a stop layer, a barrier layer and a channel layer respectively, and the GaAs epitaxial wafer is divided into a gate region, a source region and a drain region; etching the P-type cap layer of the source electrode region and the P-type cap layer of the drain electrode region, depositing a medium, and forming a P-type bulge and a medium layer on the gate electrode region, wherein the medium layer covers the top surface and the side wall of the P-type bulge; depositing an N-type cap layer in the source electrode region and the drain electrode region; a gate metal is formed in the gate region over the P-type protrusion.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a manufacturing method of an enhanced GaAs HEMT device, the enhanced GaAs HEMT device and electronic equipment.
Background
As a new generation of microwave devices, gaAs HEMT (High Electron Mobility Transistors, high electron mobility transistor) devices (including GAAS PHEMT (Pseudomorphic High Electron Mobility Transistors, pseudomorphic high electron mobility transistor) devices) have great advantages in terms of frequency, gain, and efficiency.
The enhanced GaAs HEMT device can be used for realizing logic functions on a GaAs microwave monolithic product. The current common manufacturing process flow of the enhanced GaAs HEMT device is to form a thin (for example, 20 nm) low-doped barrier layer region in the gate region by adopting the thicknesses of the Pt metal alloy of the buried layer and the extremely thin GaAlAs barrier layer in the gate region, then form a complex Pt-Ga alloy layer by adopting the buried layer alloy of Pt, further consume the thickness of the barrier layer (the effective thickness is 10nm or less), and the Pt Schottky barrier layer of the gate metal is depleted of 2-dimensional electron gas of a heterojunction channel (GaAlAs/GaInAs) under such small size, so that the threshold voltage of 0.2V can be realized only. Moreover, the process has the major defect that the process window of the device is small, any fluctuation of the Pt metal alloy on the thin barrier layer can cause the drift of the threshold voltage, and for the threshold voltage of 0.2V, the drift is often the error of the digital logic of the chip product and is an important influencing factor of the yield of the final product.
Disclosure of Invention
The invention aims to solve the technical problems, and provides an enhanced GaAs HEMT device, a manufacturing method thereof and electronic equipment, which can obviously increase the threshold voltage and improve the stability of the threshold voltage, thereby greatly improving the yield of the enhanced GaAs HEMT device.
The technical scheme adopted by the invention is as follows:
The manufacturing method of the enhanced GaAs HEMT device comprises the following steps: s1, growing an epitaxial layer on a GaAs substrate to form a GaAs epitaxial wafer, wherein the epitaxial layer is of a multi-layer structure, four layers from top to bottom are a P-type cap layer, a stop layer, a barrier layer and a channel layer respectively, and the GaAs epitaxial wafer is divided into a gate region, a source region and a drain region; s2, etching the P-type cap layers of the source electrode region and the drain electrode region, and depositing a medium, wherein a P-type bulge and a medium layer are formed in the gate electrode region, and the medium layer covers the top surface and the side wall of the P-type bulge; s3, depositing an N-type cap layer on the source electrode region and the drain electrode region; and S4, forming gate metal positioned on the P-type protrusion in the gate region.
The manufacturing method of the enhanced GaAs HEMT device further comprises the following steps: s5, forming source metal and drain metal on the N-type cap layer respectively in the source region and the drain region.
The step S2 specifically comprises the following steps: depositing a dielectric layer on the GaAs epitaxial wafer; etching the dielectric layers and the P-type cap layers of the source electrode region and the drain electrode region, stopping at the stop layer, and obtaining a first semi-finished product; depositing a dielectric layer on the first semi-finished product; and etching the dielectric layers of the source electrode region and the drain electrode region, and stopping at the stop layer.
Step S2 further includes: and etching the stop layers of the source electrode region and the drain electrode region, and stopping at the barrier layer.
And etching the stop layer by adopting a wet etching process.
After executing step S3, a second semi-finished product is obtained, and after executing step S3 and before executing step S4, the method further includes: and depositing a dielectric layer on the second semi-finished product.
The P-type cap layer adopts low-doped P-type GaAlAs, and the N-type cap layer adopts high-doped N-type GaAs.
And each deposited dielectric layer adopts silicon nitride.
The enhanced GaAs HEMT device is manufactured based on the manufacturing method of the enhanced GaAs HEMT device.
An electronic device comprises the enhanced GaAs HEMT device.
The invention has the beneficial effects that:
According to the invention, the P-type cap layer grows on the GaAs substrate and is manufactured on the epitaxial wafer containing the P-type cap layer, so that the P-type bulge and the grid metal on the P-type bulge form a grid structure of the enhanced GaAs HEMT device together, the energy band formed by the P-type grid can deplete electrons in the barrier layer and deplete 2-dimensional electron gas of a heterojunction (between the barrier layer and the channel layer), and the thickness of the barrier layer is not consumed and threshold voltage drift cannot occur due to the influence of alloy, therefore, the threshold voltage can be obviously increased, the stability of the threshold voltage is improved, and the yield of the enhanced GaAs HEMT device is greatly improved.
Drawings
Fig. 1 is a flowchart of a method for manufacturing an enhanced GaAs HEMT device according to an embodiment of the present invention;
Fig. 2 is a schematic structural diagram of a GaAs epitaxial wafer after deposition of a dielectric layer according to an embodiment of the present invention;
FIG. 3 is a schematic view of a first semi-finished product according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure after depositing a dielectric layer on a first semi-finished product according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a structure of a dielectric layer of a source region and a drain region after etching according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the structure of a second semi-finished product according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a structure after depositing a dielectric layer on a second semi-finished product according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a structure after forming gate metal, source metal and drain metal according to an embodiment of the present invention.
Reference numerals:
The semiconductor device comprises a GaAs substrate 1, an epitaxial layer 2, a dielectric layer 3, an N-type cap layer 4, a gate metal 5, a source metal 6 and a drain metal 7;
A P-type cap layer 201, a P-type bump 201', a stop layer 202, a barrier layer 203, and a channel layer 204.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, in which like filling indicates like materials. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1 to 8, the manufacturing method of the enhanced GaAs HEMT device according to the embodiment of the present invention includes steps S1 to S4:
S1, growing an epitaxial layer 2 on a GaAs substrate 1 to form a GaAs epitaxial wafer, wherein the epitaxial layer 2 is of a multi-layer structure, four layers from top to bottom are a P-type cap layer 201, a stop layer 202, a barrier layer 203 and a channel layer 204 respectively, and the GaAs epitaxial wafer is divided into a gate region, a source region and a drain region.
In one embodiment of the invention, the epitaxial layer 2 may comprise only the four layers described above.
In one embodiment of the present invention, the P-type cap layer 201 may be a low doped P-type (P-type) GaAlAs. The stopper layer 202 may be GaInP, the barrier layer 203 may be GaInAs, and the channel layer 206 may be GaInAs.
The division of the GaAs epitaxial wafer is divided according to the positions of the electrodes of the enhanced GaAs HEMT device to be manufactured.
S2, etching the P-type cap layer 201 of the source electrode region and the drain electrode region, depositing a medium, and forming a P-type protrusion 201 'and a medium layer 3 on the gate electrode region, wherein the medium layer 3 covers the top surface and the side wall of the P-type protrusion 201'.
In one embodiment of the present invention, step S2 may specifically include S21 to S24:
and S21, depositing a dielectric layer 3 on the GaAs epitaxial wafer.
The dielectric layer 3 deposited in the embodiments of the present invention may be silicon nitride. The structure after deposition of the dielectric layer 3 on the GaAs epitaxial wafer is shown in fig. 2.
And S22, etching the dielectric layer 3 of the source electrode region and the drain electrode region and the P-type cap layer 201, and stopping at the stop layer to obtain a first semi-finished product.
That is, on the basis of the structure of fig. 2, the region except the gate region is etched, and the etching process may be a dry-process and a wet-process, so that the portion of the P-type cap layer 201 remaining in the gate region is referred to as a P-type protrusion 201'. Here, stopping at the stop layer and stopping at a layer later means that etching is stopped to the upper surface of the layer, and etching is not performed on the layer. The structure of the first semi-finished product is shown in fig. 3.
S23, depositing a dielectric layer 3 on the first semi-finished product.
Here, a second deposition of dielectric layer 3 is used to protect the sidewalls of P-type bump 201' and the upper surface of stop layer 202. The dielectric layer 3 may still be silicon nitride. The structure after deposition of the dielectric layer 3 on the first semifinished product is shown in fig. 4.
And S24, etching the dielectric layer 3 of the source electrode region and the drain electrode region, and stopping at the stop layer 202.
That is, on the basis of the structure of fig. 4, the dielectric layer 3 in the region other than the gate region may be etched. It should be appreciated that since the gate region is deposited twice with the dielectric layer 3, where the thickness of the dielectric layer 3 is larger, in another embodiment of the present invention, the dielectric layer 3 may be etched to a certain thickness at the same time except for all regions.
The structure after etching the dielectric layer 3 of the source and drain regions is shown in fig. 5, leaving the dielectric layer 3 covering the top and sidewalls of the P-type bump 201'.
In another embodiment of the present invention, step S2 may further include S25:
s25, the stopper layer 202 of the source region and the drain region is etched, and stopped at the barrier layer 203.
The stop layer 202 may be etched using a wet etch process to maintain the quality of the crystal interface of the barrier layer 203.
And S3, depositing an N-type cap layer 4 in the source electrode region and the drain electrode region.
In one embodiment of the present invention, the N-type cap layer 4 may employ highly doped N-type (n+ -type) GaAs, which may be used to form ohmic contacts for the source and drain electrodes. After depositing the N-type cap layer 4 in the source and drain regions, a second semi-finished product is obtained, the structure of which is shown in fig. 6.
And S4, forming a gate metal 5 positioned above the P-type protrusion 201' in the gate region.
In one embodiment of the invention, after step S3 is performed, before step S4, a dielectric layer 3 may also be deposited on the second semi-finished product.
Here a third deposition of a dielectric layer 3 for protecting the exposed surfaces of the second semi-finished product, including the surface of the N-type cap layer 4. The dielectric layer 3 may still be silicon nitride. The structure after deposition of the dielectric layer 3 on the second semifinished product is shown in fig. 7.
On the basis of the structure of fig. 7, the gate metal 5 may be deposited on the P-type bump 201' by etching the dielectric layer 3 to pattern the gate metal 5.
Further, the method for manufacturing the enhanced GaAs HEMT device according to the embodiment of the present invention may further include step S5:
S5, forming a source metal 6 and a drain metal 7 on the N-type cap layer 4 in the source region and the drain region respectively.
Likewise, source metal 6 and drain metal 7 may be deposited on N-cap layer 4 by patterning source metal 6 and drain metal 7.
It should be understood that S5 may be performed before or after step S4, or may be performed simultaneously with step S4.
The structure after forming the gate metal 5, the source metal 6 and the drain metal 7 is shown in fig. 8.
Thus, the manufacture of the enhanced GaAs HEMT device is completed.
According to the manufacturing method of the enhanced GaAs HEMT device, the P-type cap layer is grown on the GaAs substrate and manufactured on the epitaxial wafer containing the P-type cap layer, so that the P-type bulge and the grid metal on the P-type bulge jointly form the grid structure of the enhanced GaAs HEMT device, the energy band formed by the P-type grid can deplete electrons in the barrier layer and deplete 2-dimensional electron gas of a heterojunction (between the barrier layer and the channel layer), and the barrier layer thickness is not consumed and threshold voltage drift cannot occur due to the influence of alloy, so that the threshold voltage can be obviously increased, the stability of the threshold voltage is improved, and the yield of the enhanced GaAs HEMT device is greatly improved.
Based on the manufacturing method of the enhanced GaAs HEMT device, the invention further provides the enhanced GaAs HEMT device.
The enhanced GaAs HEMT device of the embodiment of the invention is manufactured by the manufacturing method of the enhanced GaAs HEMT device of any embodiment. The specific structure of the method can refer to the embodiment of the method for manufacturing the enhanced GaAs HEMT device and fig. 8, and will not be described herein.
According to the enhanced GaAs HEMT device provided by the embodiment of the invention, the threshold voltage is higher, the stability of the threshold voltage is better, and the performance is better.
Based on the enhanced GaAs HEMT device of the embodiment, the invention further provides electronic equipment.
The electronic equipment of the embodiment of the invention comprises the enhanced GaAs HEMT device of any embodiment of the invention. The electronic device in the embodiment of the invention can be any device including the enhanced GaAs HEMT device, for example, a radio frequency device and the like.
According to the electronic equipment provided by the embodiment of the invention, the threshold voltage of the enhanced GaAs HEMT device is higher, the stability of the threshold voltage is better, and the performance is better.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The meaning of "a plurality of" is two or more, unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (8)
1. The manufacturing method of the enhanced GaAs HEMT device is characterized by comprising the following steps of:
S1, growing an epitaxial layer on a GaAs substrate to form a GaAs epitaxial wafer, wherein the epitaxial layer is of a multi-layer structure, four layers from top to bottom are respectively a P-type cap layer, a stop layer, a barrier layer and a channel layer, the GaAs epitaxial wafer is divided into a gate region, a source region and a drain region, and the stop layer adopts GaInP;
S2, etching the P-type cap layers of the source electrode region and the drain electrode region, and depositing a medium, wherein a P-type bulge and a medium layer are formed in the gate electrode region, and the medium layer covers the top surface and the side wall of the P-type bulge;
s3, depositing an N-type cap layer on the source electrode region and the drain electrode region;
s4, forming gate metal positioned above the P-type bulge in the gate region,
The step S2 specifically comprises the following steps: depositing a dielectric layer on the GaAs epitaxial wafer; etching the dielectric layers and the P-type cap layers of the source electrode region and the drain electrode region, stopping at the stop layer, and obtaining a first semi-finished product; depositing a dielectric layer on the first semi-finished product; etching the dielectric layers of the source electrode region and the drain electrode region, stopping at the stop layer,
Step S2 further includes: and etching the stop layers of the source electrode region and the drain electrode region, and stopping at the barrier layer.
2. The method of manufacturing an enhanced GaAs HEMT device of claim 1, further comprising:
s5, forming source metal and drain metal on the N-type cap layer respectively in the source region and the drain region.
3. The method for manufacturing the enhanced GaAs HEMT device according to claim 1 or 2, wherein the stop layer is etched by a wet etching process.
4. The method for manufacturing an enhanced GaAs HEMT device according to claim 3, wherein the second semi-finished product is obtained after step S3 is performed, and further comprising, after step S3 is performed and before step S4:
and depositing a dielectric layer on the second semi-finished product.
5. The method for manufacturing the enhanced GaAs HEMT device according to claim 1 or 2, wherein the P-type cap layer is made of low-doped P-type GaAlAs and the N-type cap layer is made of high-doped N-type GaAs.
6. The method of manufacturing an enhanced GaAs HEMT device of claim 4, the method is characterized in that each deposited dielectric layer adopts silicon nitride.
7. An enhanced GaAs HEMT device manufactured based on the method of manufacturing an enhanced GaAs HEMT device of any of claims 1-6.
8. An electronic device comprising the enhanced GaAs HEMT device of claim 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410852551.4A CN118398492B (en) | 2024-06-28 | 2024-06-28 | Enhanced GaAs HEMT device, manufacturing method thereof and electronic equipment |
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| CN202410852551.4A CN118398492B (en) | 2024-06-28 | 2024-06-28 | Enhanced GaAs HEMT device, manufacturing method thereof and electronic equipment |
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| CN118398492A CN118398492A (en) | 2024-07-26 |
| CN118398492B true CN118398492B (en) | 2024-09-27 |
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| CN110112215A (en) * | 2019-04-30 | 2019-08-09 | 大连理工大学 | Have both the normally-off power device and preparation method thereof of gate-dielectric and etching barrier layer functional structure |
| CN113658856A (en) * | 2021-08-06 | 2021-11-16 | 西安电子科技大学广州研究院 | P-GaN gate enhanced HEMT device and preparation method thereof |
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| WO2000079599A1 (en) * | 1999-06-23 | 2000-12-28 | The Trustees Of Columbia University In The City Of New York | InGaAsN/GaAs QUANTUM WELL DEVICES |
| US6528405B1 (en) * | 2000-02-18 | 2003-03-04 | Motorola, Inc. | Enhancement mode RF device and fabrication method |
| TWI706566B (en) * | 2016-08-01 | 2020-10-01 | 晶元光電股份有限公司 | A high power semiconductor device |
| CN108987277A (en) * | 2018-06-04 | 2018-12-11 | 北京大学深圳研究生院 | A kind of enhancement type high electron mobility transistor and preparation method thereof |
| US20220122838A1 (en) * | 2020-10-21 | 2022-04-21 | University Of South Carolina | Approaches for Fabricating N-Polar AlxGa1-xN Templates for Electronic and Optoelectronic Devices |
| CN116741635A (en) * | 2023-06-20 | 2023-09-12 | 西安电子科技大学 | HEMT device manufacturing method based on maskless regrowth low-resistance extension layer |
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| CN110112215A (en) * | 2019-04-30 | 2019-08-09 | 大连理工大学 | Have both the normally-off power device and preparation method thereof of gate-dielectric and etching barrier layer functional structure |
| CN113658856A (en) * | 2021-08-06 | 2021-11-16 | 西安电子科技大学广州研究院 | P-GaN gate enhanced HEMT device and preparation method thereof |
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