CN118335178B - High-efficiency test method for memory chip based on time sequence analysis - Google Patents
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Abstract
The invention relates to the technical field of electronic engineering, and particularly discloses a memory chip high-efficiency test method based on time sequence analysis, which comprises the following steps: determining a plurality of loading thresholds based on design parameters of the memory chip, performing a plurality of erasure tests, and recording time sequence parameters of the memory chip in the erasure test process, wherein the time sequence parameters are combined into a time sequence parameter array; evaluating performance indexes of the memory chip based on the time sequence parameter array; establishing a quantum tunneling baseline model, observing an abnormal quantum tunneling index, taking the abnormal quantum tunneling index as an influence condition, analyzing the performance index change trend of the memory chip under the influence condition, calculating the probability of abnormal risk of the memory chip, judging whether the probability of abnormal risk of the current memory chip exceeds a tolerable abnormal state interval threshold, if not, judging to be qualified, and if so, judging to be unqualified. The invention has the advantages that: the storage chip and the stability are improved, the quality control and fault diagnosis flow are optimized, and the test cost is reduced.
Description
Technical Field
The invention relates to the technical field of electronic engineering, in particular to a high-efficiency test method for a memory chip based on time sequence analysis.
Background
The transistor memory chip is a semiconductor memory device realized by using transistor technology and is mainly divided into two types, namely Dynamic RAM (DRAM) and Static RAM (SRAM), wherein the DRAM stores data by a combination of transistors and capacitors but needs to be refreshed periodically to provide high-density low-cost storage; the SRAM uses the trigger to store data without refreshing, provides high-speed low-power consumption performance, but has higher cost, and both play a core role in data processing and storage of modern electronic equipment.
Since the testing process requires the use of complex equipment and algorithms to ensure the reliability and performance of the chip, the difficulty and cost of testing are continually increasing with the increase of storage density and the miniaturization of manufacturing processes, which not only limits the universality of testing, but also increases the manufacturing cost of manufacturers.
Disclosure of Invention
In order to solve the technical problems, the technical scheme provides a high-efficiency test method for a memory chip based on time sequence analysis, which solves the problems that the reliability and the performance of the chip are ensured by using complex equipment and algorithms in the test process, and the test difficulty and the test cost are continuously increased along with the increase of the memory density and the miniaturization of the manufacturing process, so that the test universality is limited, and the manufacturing cost of manufacturers is increased.
In order to achieve the above purpose, the invention adopts the following technical scheme:
The high-efficiency test method of the memory chip based on the time sequence analysis comprises the following steps:
acquiring design parameters of a memory chip;
Determining a plurality of loading thresholds based on design parameters of the memory chip, performing a plurality of erasure tests, and recording time sequence parameters of the memory chip in the erasure test process, wherein the time sequence parameters are combined into a time sequence parameter array;
evaluating the performance index of the memory chip based on the loading threshold value of each round in the time sequence parameter array;
According to erasure test parameters in the time sequence parameter array, a quantum tunneling baseline model is established, quantum tunneling effect deviation values under corresponding erasure test parameters are observed, and abnormal quantum tunneling indexes are obtained;
Taking the abnormal quantum tunneling index as an influence condition, analyzing the performance index change trend of the memory chip under the influence condition, and calculating the probability of abnormal risk of the memory chip;
obtaining a tolerable abnormal state interval threshold according to design parameters of the memory chip;
Judging whether the probability of the abnormal risk of the current memory chip exceeds a tolerable abnormal state interval threshold, if not, judging whether the memory chip is qualified, and if so, judging whether the memory chip is unqualified.
Preferably, the evaluating the performance index of the memory chip based on the loading threshold value of each round in the time sequence parameter array specifically includes:
determining physical characteristics and electronic characteristics of materials of the memory chip;
Obtaining current and voltage thresholds of a source electrode, a drain electrode, a control gate and an insulating layer of a minimum storage unit according to physical characteristics and electronic characteristics of materials of the storage chip;
Performing control decision according to the current and voltage threshold values to obtain time sequence parameters of the memory chip, and calculating performance indexes of the memory chip through a linear regression algorithm;
the expression of the linear regression algorithm is as follows:
；
Wherein D is the performance index of the memory chip, Is the firstN is the total number of timing parameters,、、、、All are return coefficients.
Preferably, according to the erasing test parameters in the time sequence parameter array, a quantum tunneling baseline model is established, and quantum tunneling effect deviation values under the corresponding erasing test parameters are observed, wherein the obtaining of the abnormal quantum tunneling index specifically comprises:
determining the height and width of the quantum barrier based on the physical and electronic characteristics of the memory chip;
according to the equation of Schrodinger, calculating a wave function of electrons in the potential barrier, and analyzing the wave function to obtain the product of time and space;
decomposing the equation of Schrodinger to obtain three regions 、AndThe wave function and the derivative thereof are in a continuous state by applying boundary conditions, so as to obtain a linear equation set;
Solving a linear equation set by using a Gaussian elimination method to obtain a plurality of particle coefficients, and calculating quantum tunneling probability according to the plurality of particle coefficients;
calculating a quantum tunneling current value according to the quantum tunneling probability and the electron charge;
Establishing a quantum tunneling baseline model;
According to a quantum tunneling baseline model, taking the sum of quantum tunneling probability of electrons under a given electric field as output, taking a current value of predicted quantum tunneling as output, comparing the predicted tunneling current value with an observed quantum tunneling current actual value, and calculating a deviation value of tunneling current to obtain an abnormal quantum tunneling index;
The quantum tunneling baseline model is specifically established as follows:
；
In the method, in the process of the invention, An abnormal quantum tunneling index (quantum tunneling index),For the actual value of quantum tunneling current observed,In order to predict the tunneling current,To a reduction of the planck's constant,Is the second spatial derivative, m is the mass of the particle,In the quantum state of the particles at the x-position,Is the potential energy of the particles at the x position, E is the energy of the particles,As a function of the wave of the particle wave,Is the time independent wave function of the particles, t is time, i is imaginary unit, A is the amplitude of the incident wave, F is the amplitude of the projected wave,For the amount of electron charge,The electron velocity, T, is the quantum tunneling probability.
Preferably, taking the abnormal quantum tunneling index as an influence condition, analyzing a performance index change trend of the memory chip under the influence condition, and calculating the probability of occurrence of abnormal risks of the memory chip specifically includes:
abnormal state factors which enable the memory chip to appear under the influence of abnormal quantum tunneling indexes;
According to the abnormal state factors, reversely evaluating and analyzing the excitation coefficients of the quantum tunneling effect of the memory chip under the abnormal state factors;
Performing chain relation evaluation on the performance index of the memory chip according to the abnormal quantum tunneling index and the excitation coefficient of the quantum tunneling effect to obtain updated performance of the memory chip;
Building an abnormal risk probability prediction model for identifying a storage chip by Logistic regression;
Determining the chain type influence relation of an abnormal quantum tunneling index and quantum tunneling effect on the performance index of the memory chip, taking an abnormal state factor of the memory chip under the influence of the abnormal quantum tunneling index as a basic influence condition, reversely evaluating and analyzing the excitation coefficient of the quantum tunneling effect of the memory chip under the abnormal state factor as a passive influence condition, and predicting the probability of the abnormal risk of the memory chip under the basic influence condition and the passive influence condition;
the abnormal risk probability prediction model for identifying the memory chip specifically comprises the following steps:
；
In the method, in the process of the invention, The performance of the memory chip after the update,Abnormal quantum tunneling index as jth timing parameterExcitation coefficient of quantum tunneling effect of (c)，The probability of predicting the abnormal risk of the memory chip under the condition of influence factors is shown.
Compared with the prior art, the invention has the beneficial effects that:
The invention provides a high-efficiency test scheme of a memory chip based on time sequence analysis, a quantum tunneling baseline model is established by evaluating design parameters and time sequence parameters of the memory chip, abnormal risks are predicted, and a tolerable abnormal state interval threshold value is set, so that the memory chip and stability are improved, the quality control and fault diagnosis flow is optimized, and the test cost is reduced.
Drawings
FIG. 1 is a flow chart of a method for efficiently testing a memory chip based on time sequence analysis;
FIG. 2 is a flow chart of a method for evaluating performance metrics of a memory chip;
FIG. 3 is a flow chart of a method for obtaining an abnormal quantum tunneling index;
FIG. 4 is a flow chart of a method for calculating the probability of abnormal risk of a memory chip;
FIG. 5 is a schematic diagram of an electronic device according to the present invention;
FIG. 6 is a schematic diagram of a computer readable storage medium according to the present invention.
Reference numerals: bus 501, CPU502, ROM503, RAM504, communication port 505, input/output components 506, hard disk 507, user interface 508, computer readable storage medium 600.
Detailed Description
The following description is presented to enable one of ordinary skill in the art to make and use the invention. The preferred embodiments in the following description are by way of example only and other obvious variations will occur to those skilled in the art.
Referring to fig. 1, the method for efficiently testing a memory chip based on timing analysis includes:
acquiring design parameters of a memory chip;
Determining a plurality of loading thresholds based on design parameters of the memory chip, performing a plurality of erasure tests, and recording time sequence parameters of the memory chip in the erasure test process, wherein the time sequence parameters are combined into a time sequence parameter array;
evaluating the performance index of the memory chip based on the loading threshold value of each round in the time sequence parameter array;
According to erasure test parameters in the time sequence parameter array, a quantum tunneling baseline model is established, quantum tunneling effect deviation values under corresponding erasure test parameters are observed, and abnormal quantum tunneling indexes are obtained;
Taking the abnormal quantum tunneling index as an influence condition, analyzing the performance index change trend of the memory chip under the influence condition, and calculating the probability of abnormal risk of the memory chip;
obtaining a tolerable abnormal state interval threshold according to design parameters of the memory chip;
Judging whether the probability of the abnormal risk of the current memory chip exceeds a tolerable abnormal state interval threshold, if not, judging whether the memory chip is qualified, and if so, judging whether the memory chip is unqualified.
According to the scheme, the erasing test is performed by setting different loading thresholds by utilizing quantum tunneling effect in quantum mechanics, time sequence parameters are recorded, a quantum tunneling base line model is established, and an abnormal quantum tunneling index is calculated, so that the performance change trend and the abnormal risk probability of the memory chip under the influence of the abnormal quantum tunneling index are analyzed, whether the performance of the memory chip is qualified or not is judged according to the designed tolerable abnormal state interval threshold, and the reliability and the stability of the memory chip are ensured.
Referring to fig. 2, evaluating the performance index of the memory chip based on the loading threshold of each round in the timing parameter array specifically includes:
determining physical characteristics and electronic characteristics of materials of the memory chip;
Obtaining current and voltage thresholds of a source electrode, a drain electrode, a control gate and an insulating layer of a minimum storage unit according to physical characteristics and electronic characteristics of materials of the storage chip;
Performing control decision according to the current and voltage threshold values to obtain time sequence parameters of the memory chip, and calculating performance indexes of the memory chip through a linear regression algorithm;
the expression of the linear regression algorithm is as follows:
；
Wherein D is the performance index of the memory chip, Is the firstN is the total number of timing parameters,、、、、All are return coefficients;
it should be noted that the loading threshold is based on minimum voltage and current conditions required by the source, drain and control gate of the minimum memory cell in different operation modes during the design of the memory chip, including voltage threshold for read, write, erase, tunneling, etc., and maximum safe current threshold for erase and write operations.
It should be noted that the timing parameters are key indicators describing the time characteristics of the memory chip in different operation phases, and include erase delay, erase pulse width, data retention time, access time, recovery time, cycle time, address setting time, command response time, and the like, which together determine the performance states of the memory chip.
Referring to fig. 3, according to the erasure test parameters in the time sequence parameter array, a quantum tunneling baseline model is established, and quantum tunneling effect deviation values under the corresponding erasure test parameters are observed, and the obtaining of abnormal quantum tunneling indexes specifically includes:
determining the height and width of the quantum barrier based on the physical and electronic characteristics of the memory chip;
according to the equation of Schrodinger, calculating a wave function of electrons in the potential barrier, and analyzing the wave function to obtain the product of time and space;
decomposing the equation of Schrodinger to obtain three regions 、AndThe wave function and the derivative thereof are in a continuous state by applying boundary conditions, so as to obtain a linear equation set;
Solving a linear equation set by using a Gaussian elimination method to obtain a plurality of particle coefficients, and calculating quantum tunneling probability according to the plurality of particle coefficients;
calculating a quantum tunneling current value according to the quantum tunneling probability and the electron charge;
Establishing a quantum tunneling baseline model;
According to a quantum tunneling baseline model, taking the sum of quantum tunneling probability of electrons under a given electric field as output, taking a current value of predicted quantum tunneling as output, comparing the predicted tunneling current value with an observed quantum tunneling current actual value, and calculating a deviation value of tunneling current to obtain an abnormal quantum tunneling index;
The quantum tunneling baseline model is specifically established as follows:
；
In the method, in the process of the invention, An abnormal quantum tunneling index (quantum tunneling index),For the actual value of quantum tunneling current observed,In order to predict the tunneling current,To a reduction of the planck's constant,Is the second spatial derivative, m is the mass of the particle,In the quantum state of the particles at the x-position,Is the potential energy of the particles at the x position, E is the energy of the particles,As a function of the wave of the particle wave,Is the time independent wave function of the particles, t is time, i is imaginary unit, A is the amplitude of the incident wave, F is the amplitude of the projected wave,For the amount of electron charge,The electron velocity, T, is the quantum tunneling probability.
The scheme simulates and analyzes quantum tunneling effect in the semiconductor memory chip by a quantum mechanical method. The method comprises the steps of determining quantum barrier parameters, solving a Schrodinger equation, applying boundary conditions, solving a linear equation set, calculating tunneling probability and current, and establishing a baseline model. By comparing model prediction with experimental data, an abnormal quantum tunneling index can be obtained, thereby evaluating the accuracy of the model and the characteristics of quantum tunneling effect.
It should be noted that, the physical characteristic parameters of the memory chip need to be defined according to the actual situation, and the quantum tunneling effect aggravated by the loss of the insulating layer may also be considered in the actual testing process, which is not described herein.
Referring to fig. 4, taking an abnormal quantum tunneling index as an influence condition, analyzing a performance index variation trend of a memory chip under the influence condition, and calculating a probability of occurrence of an abnormal risk of the memory chip specifically includes:
abnormal state factors which enable the memory chip to appear under the influence of abnormal quantum tunneling indexes;
According to the abnormal state factors, reversely evaluating and analyzing the excitation coefficients of the quantum tunneling effect of the memory chip under the abnormal state factors;
Performing chain relation evaluation on the performance index of the memory chip according to the abnormal quantum tunneling index and the excitation coefficient of the quantum tunneling effect to obtain updated performance of the memory chip;
Building an abnormal risk probability prediction model for identifying a storage chip by Logistic regression;
Determining the chain type influence relation of an abnormal quantum tunneling index and quantum tunneling effect on the performance index of the memory chip, taking an abnormal state factor of the memory chip under the influence of the abnormal quantum tunneling index as a basic influence condition, reversely evaluating and analyzing the excitation coefficient of the quantum tunneling effect of the memory chip under the abnormal state factor as a passive influence condition, and predicting the probability of the abnormal risk of the memory chip under the basic influence condition and the passive influence condition;
the abnormal risk probability prediction model for identifying the memory chip specifically comprises the following steps:
；
In the method, in the process of the invention, The performance of the memory chip after the update,Abnormal quantum tunneling index as jth timing parameterExcitation coefficient of quantum tunneling effect of (c)，The probability of predicting the abnormal risk of the memory chip under the condition of influence factors is shown.
It can be understood that the purpose of evaluating the performance of the updated memory chip is to evaluate the probability of the final abnormal risk of the memory chip by analyzing the chain relationship, because the performance of the memory chip causes the main body of the memory chip to generate heat or the electric field front degree to change under the influence of the quantum tunneling effect, so that the quantum tunneling effect is aggravated, the performance of the memory chip is further reduced, the data to be processed is increased due to the further reduction of the performance of the memory chip, and the chain reaction with relevance causes the quantum tunneling efficiency to be further aggravated.
In summary, the invention has the advantages that: by evaluating design parameters and time sequence parameters of the memory chip, a quantum tunneling baseline model is established, abnormal risks are predicted, a tolerable abnormal state interval threshold is set, the memory chip and stability are improved, quality control and fault diagnosis processes are optimized, and test cost stability is reduced.
Further, the method or system according to the embodiment of the present application may also be implemented by means of the architecture of the electronic device shown in fig. 5. As shown in fig. 5, the electronic device may include a bus 501, one or more CPUs 502, a Read Only Memory (ROM) 503, a Random Access Memory (RAM) 504, a communication port 505 connected to a network, an input/output component 506, a hard disk 507, and the like. A storage device in an electronic device, such as ROM503 or hard disk 507, may store the manufacturing data intelligent detection method based on time sequence analysis provided by the present application. The high-efficiency test method of the memory chip based on the time sequence analysis comprises the following steps: acquiring design parameters of a memory chip, determining a plurality of loading thresholds based on the design parameters of the memory chip, performing a plurality of erasure tests, recording time sequence parameters of the memory chip in the erasure test process, combining the time sequence parameters into a time sequence parameter array, evaluating performance indexes of the memory chip based on the loading thresholds of each round in the time sequence parameter array, establishing a quantum tunneling baseline model according to the erasure test parameters in the time sequence parameter array, observing quantum tunneling effect deviation values under the corresponding erasure test parameters to obtain abnormal quantum tunneling indexes, analyzing the performance index change trend of the memory chip under the influence condition by taking the abnormal quantum tunneling indexes as influence conditions, calculating the probability of occurrence of abnormal risk of the memory chip, obtaining a tolerable abnormal state interval threshold according to the design parameters of the memory chip, judging whether the probability of occurrence of abnormal risk of the current memory chip exceeds the tolerable abnormal state interval threshold, if not, judging to be qualified, judging to be unqualified, and the electronic equipment can further comprise a user interface 508. Of course, the architecture shown in fig. 5 is merely exemplary, and one or more components of the electronic device shown in fig. 5 may be omitted as may be practical in implementing different devices.
FIG. 6 is a schematic diagram of a computer-readable storage medium according to one embodiment of the present application. As shown in fig. 6, is a computer-readable storage medium 600 according to one embodiment of the application. Computer readable storage medium 600 has stored thereon computer readable instructions. The path planning method according to the embodiment of the present application described with reference to the above drawings may be performed when the computer readable instructions are executed by the processor. Storage medium 600 includes, but is not limited to, for example, volatile memory and/or nonvolatile memory. Volatile memory can include, for example, random Access Memory (RAM), cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like.
In addition, according to embodiments of the present application, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, the present application provides a non-transitory machine-readable storage medium storing machine-readable instructions executable by a processor to perform instructions corresponding to the method steps provided by the present application, such as: acquiring design parameters of a memory chip, determining a plurality of loading thresholds based on the design parameters of the memory chip, performing a plurality of erasure tests, recording time sequence parameters of the memory chip in the erasure test process, combining the time sequence parameters into a time sequence parameter array, evaluating performance indexes of the memory chip based on the loading thresholds of each round in the time sequence parameter array, establishing a quantum tunneling baseline model according to the erasure test parameters in the time sequence parameter array, observing quantum tunneling effect deviation values under the corresponding erasure test parameters to obtain abnormal quantum tunneling indexes, taking the abnormal quantum tunneling indexes as influence conditions, analyzing the performance index change trend of the memory chip under the influence conditions, calculating the probability of occurrence of abnormal risks of the memory chip, judging whether the probability of occurrence of abnormal risks of the current memory chip exceeds the tolerable abnormal state interval threshold according to the design parameters of the memory chip, if not, judging to be qualified, judging to be unqualified, and executing the functions defined in the method when the computer program is executed by a Central Processing Unit (CPU).
The methods and apparatus, devices of the present application may be implemented in numerous ways. For example, the methods and apparatus, devices of the present application may be implemented by software, hardware, firmware, or any combination of software, hardware, firmware. The above-described sequence of steps for the method is for illustration only, and the steps of the method of the present application are not limited to the sequence specifically described above unless specifically stated otherwise. Furthermore, in some embodiments, the present application may also be embodied as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present application. Thus, the present application also covers a recording medium storing a program for executing the method according to the present application.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made therein without departing from the spirit and scope of the invention, which is defined by the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (5)
1. The high-efficiency test method for the memory chip based on the time sequence analysis is characterized by comprising the following steps of:
acquiring design parameters of a memory chip;
Determining multiple loading thresholds based on design parameters of the memory chip, performing multiple rounds of erasing test, recording time sequence parameters of the memory chip in the erasing test process, combining into a time sequence parameter array,
Evaluating the performance index of the memory chip based on the loading threshold value of each round in the time sequence parameter array;
According to erasure test parameters in the time sequence parameter array, a quantum tunneling baseline model is established, quantum tunneling effect deviation values under corresponding erasure test parameters are observed, and abnormal quantum tunneling indexes are obtained;
Taking the abnormal quantum tunneling index as an influence condition, analyzing the performance index change trend of the memory chip under the influence condition, and calculating the probability of abnormal risk of the memory chip;
obtaining a tolerable abnormal state interval threshold according to design parameters of the memory chip;
Judging whether the probability of the abnormal risk of the current memory chip exceeds a tolerable abnormal state interval threshold, if not, judging whether the memory chip is qualified, and if so, judging whether the memory chip is unqualified;
the performance index of the memory chip is evaluated based on the loading threshold value of each round in the time sequence parameter array specifically comprises the following steps:
determining physical characteristics and electronic characteristics of materials of the memory chip;
Obtaining current and voltage thresholds of a source electrode, a drain electrode, a control gate and an insulating layer of a minimum storage unit according to physical characteristics and electronic characteristics of materials of the storage chip;
Performing control decision according to the current and voltage threshold values to obtain time sequence parameters of the memory chip, and calculating performance indexes of the memory chip through a linear regression algorithm;
The linear regression algorithm expression is:
Wherein D is the performance index of the memory chip, Is the firstN is the total number of timing parameters,、、、、All are return coefficients;
according to the erasing test parameters in the time sequence parameter array, a quantum tunneling baseline model is established, and quantum tunneling effect deviation values under the corresponding erasing test parameters are observed, wherein the obtaining of abnormal quantum tunneling indexes specifically comprises the following steps:
determining the height and width of the quantum barrier based on the physical and electronic characteristics of the memory chip;
according to the equation of Schrodinger, calculating a wave function of electrons in the potential barrier, and analyzing the wave function to obtain the product of time and space;
decomposing the equation of Schrodinger to obtain three regions 、AndThe wave function and the derivative thereof are in a continuous state by applying boundary conditions, so as to obtain a linear equation set;
Solving a linear equation set by using a Gaussian elimination method to obtain a plurality of particle coefficients, and calculating quantum tunneling probability according to the plurality of particle coefficients;
calculating a quantum tunneling current value according to the quantum tunneling probability and the electron charge;
Establishing a quantum tunneling baseline model;
According to a quantum tunneling baseline model, taking the sum of quantum tunneling probability of electrons under a given electric field as output, taking a current value of predicted quantum tunneling as output, comparing the predicted tunneling current value with an observed quantum tunneling current actual value, and calculating a deviation value of tunneling current to obtain an abnormal quantum tunneling index;
the quantum tunneling baseline model is established specifically as follows:
In the method, in the process of the invention, An abnormal quantum tunneling index (quantum tunneling index),For the actual value of quantum tunneling current observed,In order to predict the tunneling current,To a reduction of the planck's constant,Is the second spatial derivative, m is the mass of the particle,In the quantum state of the particles at the x-position,Is the potential energy of the particles at the x position, E is the energy of the particles,As a function of the wave of the particle wave,Is the time independent wave function of the particles, t is time, i is imaginary unit, A is the amplitude of the incident wave, F is the amplitude of the projected wave,For the amount of electron charge,The electron velocity, T, is the quantum tunneling probability.
2. The method for efficiently testing a memory chip based on time sequence analysis according to claim 1, wherein analyzing a trend of performance index change of the memory chip under an influence condition with an abnormal quantum tunneling index as the influence condition, and calculating a probability of occurrence of an abnormal risk of the memory chip specifically comprises:
Abnormal state factors which enable the memory chip to appear under the influence of abnormal quantum tunneling indexes; the abnormal state factors include, but are not limited to: a memory chip temperature rising factor caused by abnormal quantum tunneling and a memory chip electric field intensity changing factor caused by abnormal quantum tunneling;
According to the abnormal state factors, reversely evaluating and analyzing the excitation coefficients of the quantum tunneling effect of the memory chip under the abnormal state factors;
Performing chain relation evaluation on the performance index of the memory chip according to the abnormal quantum tunneling index and the excitation coefficient of the quantum tunneling effect to obtain updated performance of the memory chip;
Building an abnormal risk probability prediction model for identifying a storage chip by Logistic regression;
Determining a chain type influence relation of an abnormal quantum tunneling index and a quantum tunneling effect on a performance index of a memory chip, taking an abnormal state factor of the memory chip under the influence of the abnormal quantum tunneling index as a basic influence condition, reversely evaluating and analyzing the excitation coefficient of the quantum tunneling effect of the memory chip under the abnormal state factor as a passive influence condition, and predicting the probability of the abnormal risk of the memory chip under the basic influence condition and the passive influence condition.
3. The efficient test method for memory chips based on time sequence analysis according to claim 2, wherein the abnormal risk probability prediction model for identifying the memory chips is specifically:
In the method, in the process of the invention, The performance of the memory chip after the update,Abnormal quantum tunneling index as jth timing parameterExcitation coefficient of quantum tunneling effect of (c)，The probability of predicting the abnormal risk of the memory chip under the condition of influence factors is shown.
4. An electronic device, comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the time-series analysis based memory chip efficient test method of any one of claims 1-3.
5. A computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the method for efficiently testing a memory chip based on timing analysis according to any one of claims 1 to 3.
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