CN118335034B - Pixel driving circuit, display panel and driving method thereof - Google Patents

Abstract

The application discloses a pixel driving circuit, a display panel and a driving method thereof, wherein the driving method comprises the following steps: acquiring a preset number of continuous multi-frame pictures, and judging whether the data of the continuous multi-frame pictures are the same or not; the continuous multi-frame picture comprises a plurality of frame periods, and each frame period comprises a plurality of frame groups, namely a first frame group, a second frame group and a third frame group; responding to the same data of continuous multi-frame pictures, controlling the first frame group to enter a normal display mode through a time sequence controller, controlling the second frame group to enter a first power consumption display mode, and controlling the third frame group to enter a second power consumption display mode; the first power consumption display mode is different from the second power consumption display mode, and the first power consumption display mode and the second power consumption display mode both comprise a mode of alternately inputting data to odd lines and even lines of different frames of pictures. The application reduces the frequent switching between high and low levels during data input and reduces the power consumption of the display panel.

Description

Pixel driving circuit, display panel and driving method thereof

Technical Field

The application relates to the technical field of display, in particular to a pixel driving circuit, a display panel and a driving method thereof.

Background

With the development of the panel industry, the trend in the panel market is that the panel market is increasingly larger in size, and new requirements of low power consumption, high resolution, high refresh rate and the like are increasingly increased, and the new requirements provide new challenges for design, materials and processes. In the related art, the panel design is performed by adopting the GDL (GATE DRIVER LESS, fewer gate drivers) design, but there are still problems of large power consumption, easy damage to the display panel, and the like.

Disclosure of Invention

In view of the above, the present application provides a pixel driving circuit, a display panel and a driving method thereof, so as to solve the problem of large power consumption in the GDL panel design in the prior art.

In order to solve the technical problems, the first technical scheme provided by the application is as follows: the driving method of the display panel is provided, wherein the display panel comprises a normal display mode, a first power consumption display mode and a second power consumption display mode; the driving method includes: acquiring a preset number of continuous multi-frame pictures, and judging whether the data of the continuous multi-frame pictures are the same or not; the continuous multi-frame picture comprises a plurality of frame periods, wherein each frame period comprises a plurality of frame groups, namely a first frame group, a second frame group and a third frame group; responding to the fact that the data of the continuous multi-frame pictures are the same, controlling the first frame group to enter the normal display mode through a time sequence controller, controlling the second frame group to enter the first power consumption display mode, and controlling the third frame group to enter the second power consumption display mode; the first power consumption display mode is different from the second power consumption display mode, and the first power consumption display mode and the second power consumption display mode both comprise a mode of alternately inputting data to odd lines and even lines of different frames of pictures.

In an embodiment, the controlling, by the timing controller, the first frame group to enter the normal display mode includes: inputting a normal data signal including positive and negative polarities to the first frame group; the first power consumption display mode and the second power consumption display mode both comprise a mode of alternately inputting data to odd lines and even lines of different frames of pictures, and the method comprises the following steps: inputting data signals to odd lines of the second frame group, and closing data input to even lines; and closing the data signals for the odd lines of the third frame group, and inputting the data signals for the even lines.

In an embodiment, the frame period takes 6 frames as a period, the first frame group comprises 0 to 1 th frames, the second frame group comprises 2 to 3rd frames, and the third frame group comprises 4 to 5th frames; in the 0 th to 1 th frames, the grid driving units of the odd lines and the even lines are controlled to be in an open state through a control circuit, and data are input to the pixel units of the odd lines and the even lines through data lines so that the frames in the 0 th to 1 th frames display normal frames; in the 0 th to 1 th frames, the data line inputs positive polarity voltage to the pixel unit of the 0 th frame, and the data line inputs negative polarity voltage to the pixel unit of the 1st frame; in the 2nd to 3rd frames, the gate driving units of the odd lines are controlled to be in an open state by the control circuit, the gate driving units of the even lines are controlled to be in a closed state, data are input to the pixel units of the odd lines by the data lines, and data writing is closed to the pixel units of the even lines, so that normal pictures are displayed on the odd lines, and black pictures are displayed on the even lines; and in the 4th to 5th frames, controlling the gate driving units of the even lines to be in an on state and controlling the gate driving units of the odd lines to be in an off state by the control circuit, inputting data to the pixel units of the even lines by the data lines, and closing data writing to the pixel units of the odd lines so that the even lines display normal pictures and the odd lines display black pictures; or in the 2nd to 3rd frames, controlling the gate driving units of the even lines to be in an on state and controlling the gate driving units of the odd lines to be in an off state through the control circuit, inputting data to the pixel units of the even lines through the data lines, and closing data writing to the pixel units of the odd lines so that the even lines display normal pictures and the odd lines display black pictures; and in the 4th to 5th frames, controlling the gate driving units of the odd lines to be in an on state and controlling the gate driving units of the even lines to be in an off state by the control circuit, inputting data to the pixel units of the odd lines by the data lines, and closing data writing to the pixel units of the even lines so that the odd lines display normal pictures and the even lines display black pictures; in the 2nd to 3rd frames, the data line inputs positive polarity voltage to the pixel unit of the 2nd frame and inputs negative polarity voltage to the pixel unit of the 3rd frame; and in the 4th to 5th frames, the data line inputs positive polarity voltage to the pixel unit of the 4th frame and inputs negative polarity voltage to the pixel unit of the 5th frame.

In an embodiment, the frame period takes a normal display period of 6 frames and an even frame as a period, wherein in the normal display period of the even frame, voltages including positive polarity and negative polarity are input to the pixel units of the odd row and the even row by the data line.

In an embodiment, the frame period takes 3 frames as a period, the first frame group includes a 0 th frame, the second frame group includes a 1 st frame, and the third frame group includes a 2 nd frame; in the 0 th frame, the grid driving units of the odd lines and the even lines are controlled to be in an open state through a control circuit, and data are input to the pixel units of the odd lines and the even lines through data lines so that the 0 th frame displays a normal picture; in the 1 st frame, the gate driving units of the odd lines are controlled to be in an open state by the control circuit, the gate driving units of the even lines are controlled to be in a closed state, data are input to the pixel units of the odd lines by the data lines, and data writing is closed to the pixel units of the even lines, so that the odd lines display normal pictures, and the even lines display black pictures; and in the 2 nd frame, controlling the gate driving units of the even lines to be in an on state and controlling the gate driving units of the odd lines to be in an off state by the control circuit, inputting data to the pixel units of the even lines by the data lines, and closing data writing to the pixel units of the odd lines so that the even lines display normal pictures and the odd lines display black pictures; or in the 1 st frame, controlling the gate driving units of the even lines to be in an open state and controlling the gate driving units of the odd lines to be in a closed state through the control circuit, inputting data to the pixel units of the even lines through the data lines, and closing data writing to the pixel units of the odd lines so that the even lines display normal pictures and the odd lines display black pictures; and in the 2 nd frame, controlling the gate driving units of the odd lines to be in an on state and controlling the gate driving units of the even lines to be in an off state by the control circuit, inputting data to the pixel units of the odd lines by the data lines, and closing data writing to the pixel units of the even lines so that the odd lines display normal pictures and the even lines display black pictures; in the 0 th frame, the 1 st frame and the 2 nd frame, the data line inputs voltages of positive polarity and negative polarity to the pixel unit.

In an embodiment, in the second frame group and the third frame group, the gate driving unit may adjust an on time of a scan line so that a charge amount of the pixel unit corresponding to the scan line reaches a preset charge amount.

In an embodiment, the data input is performed in a cycle manner in the multiple frame periods, and the data input modes of the same frame group in the multiple frame periods may be the same or different; when the gate driving units of the odd-numbered rows are in an open state and the gate driving units of the even-numbered rows are in a closed state, the data input of the pixel units of the even-numbered rows follows the data of the odd-numbered rows and is consistent with the data of the odd-numbered rows; when the gate driving units of the even-numbered rows are in an open state and the gate driving units of the odd-numbered rows are in a closed state, the data input of the pixel units of the odd-numbered rows follows the data of the even-numbered rows and is consistent with the data of the even-numbered rows.

In order to solve the technical problems, a second technical scheme provided by the application is as follows: providing a pixel driving circuit, which comprises a plurality of scanning lines, a plurality of data lines and a plurality of pixel units driven by the scanning lines and the data lines respectively; the pixel driving circuit is driven by the driving method according to any one of the above; the pixel driving circuit further includes: the system control unit is used for acquiring data of continuous multi-frame pictures in the display pictures and carrying out similarity comparison and judgment on the data of the continuous multi-frame pictures; the plurality of cascaded grid driving units are respectively coupled with the plurality of scanning lines in a one-to-one correspondence manner; a control circuit is arranged between each gate driving unit and each scanning line and used for controlling the connection and disconnection of the gate driving units and the scanning lines of the corresponding rows; the time sequence controller is respectively and electrically connected with the system control unit and the grid driving unit; the time sequence controller is used for receiving the information of the system control unit, outputting a corresponding time sequence control signal to the control circuit based on the information, and outputting a corresponding driving signal to the grid driving unit through the control circuit so as to control the opening or closing of the scanning line of the corresponding row.

In one embodiment, the control circuit includes: a first signal control line, and first and second switching transistors electrically connected to the first signal control line, the first switching transistor being electrically connected to the scan lines of odd-numbered rows and the gate driving units corresponding to the scan lines; the second switching transistor is electrically connected with a first reference voltage; a second signal control line, and third and fourth switching transistors electrically connected to the second signal control line, the third switching transistor electrically connected to the scan lines of even numbered rows and the gate driving units corresponding to the scan lines; the fourth switching transistor is electrically connected with a second reference voltage; the first signal control line and the second signal control line are used for receiving signals of the time schedule controller and controlling the corresponding scanning lines of the odd lines or the even lines to be opened and closed; the pixel driving circuit further includes: and the level conversion unit is respectively coupled with the time schedule controller and the gate driving unit and is used for converting the data signals obtained from the time schedule controller into a signal format required by the gate driving unit and transmitting the converted data signals to the gate driving unit.

In order to solve the technical problems, a third technical scheme provided by the application is as follows: the display panel comprises an array substrate, a color film substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, wherein the array substrate comprises the pixel driving circuit as described in any one of the above

The application has the beneficial effects that: unlike the prior art, the driving method of the display panel of the present application includes: acquiring a preset number of continuous multi-frame pictures, and judging whether the data of the continuous multi-frame pictures are the same or not; the continuous multi-frame picture comprises a plurality of frame periods, and each frame period comprises a plurality of frame groups, namely a first frame group, a second frame group and a third frame group; responding to the same data of continuous multi-frame pictures, controlling the first frame group to enter a normal display mode through a time sequence controller, controlling the second frame group to enter a first power consumption display mode, and controlling the third frame group to enter a second power consumption display mode; the first power consumption display mode is different from the second power consumption display mode, and the first power consumption display mode and the second power consumption display mode both comprise a mode of alternately inputting data to odd lines and even lines of different frames of pictures. According to the application, the plurality of frame groups adopting the first power consumption display mode or the second power consumption display mode are arranged in the same frame period, so that data input is alternately carried out on odd lines and even lines of different frame pictures, thereby reducing the condition of frequent switching between high and low levels during data input, reducing the power consumption of the display panel, prolonging the service life of the display panel and reducing the cost.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a display panel according to the present application;

Fig. 2 is a schematic diagram of the structure of a pixel driving circuit provided by the present application;

FIG. 3 is a schematic diagram of a pixel driving circuit according to the present application;

fig. 4 is a schematic circuit block diagram of a pixel driving circuit according to the present application;

FIG. 5 is a schematic block diagram of a method of driving a display panel according to the present application;

FIG. 6 is a schematic block diagram of a judging flow of a static picture of a display panel provided by the application;

FIG. 7 is a schematic block diagram of a flow chart of a sub-step of step S2 provided in FIG. 5 in accordance with the present application;

FIG. 8 is a schematic view of the opening pattern of the scan line of the comparative example provided by the present application;

FIG. 9 is a schematic diagram showing the opening mode of the scan line according to the first embodiment of the present application;

FIG. 10 is a schematic diagram of a data line transmission scheme according to a comparative example provided by the present application;

FIG. 11 is a schematic diagram of a data line transmission mode according to a first embodiment of the present application;

fig. 12 is a schematic diagram of a data line transmission mode according to a second embodiment of the present application;

Fig. 13 is a schematic diagram of a data line transmission mode according to a third embodiment of the present application.

Reference numerals illustrate:

100. A pixel driving circuit; 10. a pixel unit; 11. a first subpixel; 12. a second subpixel; 13. a third sub-pixel; 20. a system control unit; 30. a gate driving unit; 40. a timing controller; 50. a level conversion unit; 60. a data driving unit; 70. a control circuit; 80. a reference line; v1, a first signal control line; v2, a second signal control line; t1, a first switching transistor; t2, a second switching transistor; t3, a third switching transistor; t4, a fourth switching transistor; VGL1, a first reference voltage; VGL2, second reference voltage; VGH, third reference voltage; data and data lines; gate, scan line; 200. a display panel; 201. an array substrate; 202. a color film substrate; 203. a liquid crystal layer; 2031. liquid crystal molecules.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. Based on the embodiments of the present application, all other embodiments that a person of ordinary skill in the art could obtain without making any inventive effort are within the scope of the present application.

The terms "first," "second," and "first," herein, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "first", "second", or "first" may include at least one such feature, either explicitly or implicitly. All directional indications (such as up, down, left, right, front, back … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

The research process of the application finds that: the Liquid Crystal Display (LCD) CRYSTAL DISPLAY has many advantages such as thin body, power saving, no radiation, etc., and has been widely used. Such as: liquid crystal televisions, mobile phones, digital cameras, computer screens, notebook computer screens, and the like are dominant in the field of flat panel displays. As the size of the panel market increases, the refresh rate increases, so too does the power consumption of the panel as a whole. A TFT (Thin Film Transistor ) type liquid crystal display is generally based on GDL technology as a drive for horizontal scan lines. That is, on the same scanning line in the horizontal direction, the gates of all TFTs are connected together, so that the applied voltages are linked, and when a sufficiently large positive voltage is applied to the scanning line, all the TFTs on the scanning line are turned on, at this time, the pixel electrodes on the scanning line are connected with the data lines in the vertical direction, and the corresponding data signals are sent by the vertical data lines to charge the pixel electrodes to an appropriate voltage; applying a sufficiently large negative voltage to the scan line, turning off the TFT until the next re-write of the signal, during which time charge is stored on the liquid crystal capacitor; at this time, the next horizontal scanning line is started again, and the corresponding data signals are sent in to complete the progressive scanning. However, when the data signal is at the high level, the n-th row pixel electrode is charged, when the n-th row is bright, and the data signal is at the low level, the n+1th row pixel electrode is not charged, the n+1th row is dark, and the n+2th row is bright, and the n+3rd row is dark … …, so that the bright-dark alternate picture, i.e. the H-LINE picture, is output through the high-low level switching of the data signal, and at the moment, high power consumption is generated due to the fact that the data signal needs to be continuously switched at the high-low level, the temperature is increased, and the display panel is easy to damage. Aiming at the problems that the data signal of an output H-LINE picture needs to be continuously switched to high and low levels, so that the power consumption is high and the display panel is easy to damage, no effective solution is proposed at present.

However, international energy standards are gradually controlling energy consumption, so that reduction of power consumption is a necessary trend. Considering the whole machine application market, the situation that the picture is maintained for a long time after being paused is truly existed, so that the power consumption of the display panel is reduced aiming at the static picture application scene.

Referring to fig. 1 to 4, fig. 1 is a schematic diagram of a display panel according to the present application; fig. 2 is a schematic diagram of the structure of a pixel driving circuit provided by the present application; FIG. 3 is a schematic diagram of a pixel driving circuit according to the present application; fig. 4 is a schematic circuit block diagram of a pixel driving circuit according to the present application.

As shown in fig. 1, the display panel 200 provided by the present application includes an array substrate 201, a color film substrate 202, and a liquid crystal layer 203 disposed between the array substrate 201 and the color film substrate 202, wherein the array substrate 201 includes a pixel driving circuit 100. Specifically, the liquid crystal layer 203 includes a plurality of liquid crystal molecules 2031, and the pixel driving circuit 100 applies an electric field to the liquid crystal molecules 2031 to change the arrangement direction of the liquid crystal molecules 2031, so as to achieve the purposes of light shielding and light transmission, thereby displaying images with different depths and different patterns.

As shown in fig. 2 to 3, the pixel driving circuit 100 according to an embodiment of the present application includes a plurality of scan lines gate and a plurality of data lines data, and a plurality of pixel units 10 driven by the plurality of scan lines gate and the plurality of data lines data, respectively. The pixel driving circuit 100 further includes a system control unit 20, a plurality of cascaded gate driving units 30, and a timing controller 40, where the system control unit 20 is configured to obtain data of consecutive multi-frame pictures in the display picture, and perform similarity comparison and judgment on the data of consecutive multi-frame pictures. For example, the system control unit 20 may determine whether the data of consecutive multi-frame pictures are the same, and thus may determine whether the display panel 200 is in a standby state, that is, whether the display picture is in a stationary state. The continuous multi-frame picture can be 10 frames, 20 frames, even 100 frames, etc., and can be specifically set according to the needs. It should be noted that, the number of consecutive multi-frame frames cannot be too small, otherwise, the problem of inaccurate judgment for the still frames is liable to occur. Therefore, when the number of consecutive multi-frame pictures is set, it is necessary to consider that the count of static pictures reaches a certain number, so as to avoid the situation that the judgment is wrong due to the fact that only one or two frames of picture data are the same (picture is stuck). In this embodiment, the system control unit 20 may be SOC (System on Chip), which is a circuit control unit of the overall system of the display panel 200, and the SOC has both a powerful memory function and a processing capability of the operating system. In other embodiments, the system control unit 20 may also employ other control chips, which are not particularly limited in the present application.

The pixel driving circuit 100 may further include a data driving unit 60, and the data driving unit 60 may be used to drive the data line data to start charging the pixel unit 10.

As shown in fig. 3 to 4, the plurality of cascaded gate driving units 30 are respectively coupled to the plurality of scan lines gate in a one-to-one correspondence manner. A control circuit 70 is disposed between each gate driving unit 30 and each scan line gate, and the control circuit 70 is used for controlling the gate driving unit 30 to be turned on or off with respect to the scan line gate of the corresponding row. For example, in a certain frame, the control circuit 70 controls the gate driving unit 30 to turn on the scan lines gate of the odd or even rows, so that the data line data can charge the pixel unit 10 corresponding to the turned-on scan line gate.

The timing controller 40 (TCON, timing Controller) is electrically connected to the system control unit 20 and the gate driving unit 30, respectively. The timing controller 40 is configured to receive information of the system control unit 20, and output a corresponding timing control signal to the control circuit 70 based on the information, and output a corresponding driving signal to the gate driving unit 30 through the control circuit 70 to control the on or off of the scanning line gate of the corresponding row. The timing controller 40 may receive information of the system control unit 20, such as control information for the gate driving unit 30, and may then convert video signals obtained from the system control unit 20 into a data signal format required by the control circuit 70, such as converting video signal LVDS into mini LVDS, through the timing controller 40. The timing control signal is transmitted to the gate driving unit 30, so that the gate driving unit 30 can turn on or off the scan line gate, thereby inputting data to the pixel unit 10. For example, the gate driving unit 30 controls the odd-numbered scanning lines gate of the 1 st frame to be turned on, so that corresponding data can be input to the pixel units 10 corresponding to the odd-numbered lines of the first frame.

In one embodiment, as shown in fig. 3, the pixel driving circuit 100 further includes a level conversion unit 50 (LEVEL SHIFT), and the level conversion unit 50 is coupled to the timing controller 40 and the gate driving unit 30, respectively, for converting the data signal obtained from the timing controller 40 into a signal format required by the gate driving unit 30, and transmitting the converted data signal to the gate driving unit 30. The gate driving unit 30 is supplied with various voltages through the level converting unit 50, for example, a Direct Current (DC) power source may be converted into a direct current power source of different voltages through a DC-DC converter.

As shown in fig. 4, in one embodiment, the control circuit 70 includes: the first signal control line V1, and the first and second switching transistors t1 and t2 electrically connected to the first signal control line V1, the first switching transistor t1 being electrically connected to the scan line gate of the odd-numbered row and the gate driving unit 30 corresponding to the scan line gate. The second switching transistor t2 is electrically connected to the first reference voltage VGL1. The first switching transistor t1 and the second switching transistor t2 may be an NMOS (Negative-Metal-Oxide-Semiconductor) and a PMOS (Positive-Metal-Oxide-Semiconductor) respectively, which form a group of inverters (not shown), and the first switching transistor t1 is turned off and the second switching transistor t2 is turned on.

The control circuit 70 further includes a second signal control line V2, and a third switching transistor t3 and a fourth switching transistor t4 electrically connected to the second signal control line V2, the third switching transistor t3 being electrically connected to the scan line gate of the even-numbered row and the gate driving unit 30 corresponding to the scan line gate. The fourth switching transistor t4 is electrically connected to the second reference voltage VGL2. The first signal control line V1 and the second signal control line V2 are used for receiving signals of the timing controller 40 and controlling the corresponding scan lines gate of the odd-numbered row or the even-numbered row to be turned on and off. The third switching transistor t3 and the fourth switching transistor t4 are arranged in the same manner and are used in the same manner as the first switching transistor t1 and the second switching transistor t2, and detailed descriptions thereof are omitted.

In this embodiment, the first switching transistor t1, the second switching transistor t2, the third switching transistor t3 and the fourth switching transistor t4 may all adopt TFTs, and the gate of the TFTs is controlled by the third reference voltage VGH, the first reference voltage VGL1 or the second reference voltage VGL2, wherein VGH is responsible for turning on the TFTs, and VGL is responsible for turning off the TFTs.

As shown in fig. 4, for example, in the odd rows of the 2 th to 3 rd frames, the first switching transistor t1 is controlled to be turned on by the first signal control line V1, at this time, the input end of the first switching transistor t1 is electrically connected to VGH, so as to realize the turning on of the first switching transistor t1, and the input end of the second switching transistor t2 is electrically connected to the first reference voltage VGL1, so as to control the second switching transistor t2 to be turned off. Therefore, at this time, the pixel cells 10 in the odd-numbered lines of the first frame are charged, and the data writing of the pixel cells 10 in the odd-numbered lines is realized, so that the odd-numbered lines normally display the screen. In contrast, since the scanning line gate of the even line of the first frame is turned off at this time, the pixel unit 10 of the even line cannot write data, and thus the even line of the first frame displays a black screen.

In order to solve the above-mentioned problems, the present application also provides a driving method of the display panel 200, and the pixel driving circuit 100 of the display panel 200 is driven by the driving method described below.

Referring to fig. 5 to 7, fig. 5 is a schematic block flow diagram of a driving method of a display panel according to the present application; FIG. 6 is a schematic block diagram of a judging flow of a static picture of a display panel provided by the application; fig. 7 is a schematic block flow diagram of a sub-step of step S2 provided in fig. 5 according to the present application.

The driving method for driving the display panel 200 according to an embodiment of the present application includes a normal display mode, a first power consumption display mode, and a second power consumption display mode; as shown in table 1 below, table 1 is a mode switching example of a plurality of display modes provided in the first embodiment of the present application.

TABLE 1

As shown in fig. 5 to 6, the driving method of the display panel 200 may include the following steps:

S1: and acquiring a preset number of continuous multi-frame pictures, and judging whether the data of the continuous multi-frame pictures are the same or not.

Specifically, the preset number of continuous multi-frame pictures can be 10 frames, 20 frames, even 100 frames, and the like, and can be specifically set according to the needs. The number of consecutive multi-frame pictures cannot be too small, otherwise, the problem of inaccurate judgment for the still picture is liable to occur. Therefore, when the number of consecutive multi-frame pictures is set, it is necessary to consider that the count of static pictures reaches a certain number, so as to avoid the situation that the judgment is wrong due to the fact that only one or two frames of picture data are the same (picture is stuck). Determining whether the data of consecutive multi-frame pictures is the same may be used to determine whether the current picture is in a still picture, and thus whether the display panel 200 is in a standby state.

In an embodiment of the present application, the continuous multi-frame picture includes a plurality of frame periods, and each frame period includes a plurality of frame groups, which are a first frame group, a second frame group, and a third frame group, respectively. The data input is performed in a plurality of frame periods in a circulating way, and the data input modes of the same frame group in the plurality of frame periods can be the same or different. For example, the data input manner in the second frame group in the first frame period and the second frame group in the second frame period may be different; the plurality of frame groups in the first frame period may perform data input in the order of the first frame group, the second frame group, and the third frame group, the plurality of frame groups in the second frame period may perform data input in the order of the first frame group, the third frame group, and the second frame group, and so on. That is, the order between each frame group is adjustable within the same frame period; the plurality of frame groups may perform data input in different orders within different frame periods.

S2: and in response to the fact that the data of the continuous multi-frame pictures are the same, the first frame group is controlled to enter a normal display mode through the time sequence controller, the second frame group is controlled to enter a first power consumption display mode, and the third frame group is controlled to enter a second power consumption display mode.

Specifically, when the data of the continuous multi-frame frames are the same, a result that the current display frame is a still frame can be obtained, and then the timing controller 40 can control the plurality of frame groups to input data according to the different display modes. The first power consumption display mode is different from the second power consumption display mode, and the first power consumption display mode and the second power consumption display mode both comprise a mode of alternately inputting data to odd lines and even lines of different frames of pictures. It will be appreciated that the first power consumption display mode and the second power consumption display mode each include a manner in which the odd lines and the even lines alternate for data input in partially different frame groups, for example, the odd lines and the even lines alternate for data input in the second frame group and the third frame group.

As shown in fig. 7, in an embodiment, controlling the first frame group to enter the normal display mode by the timing controller 40 includes:

S20: a normal data signal including positive and negative polarities is input to the first frame group.

Specifically, it can be understood that one or more frames in the first frame group are simultaneously input with positive polarity data and negative polarity data, and it is not divided into which frame positive polarity data is input and which frame negative polarity data is input, so that display pictures of odd lines and even lines in the first frame group are normal pictures.

In an embodiment, the first power consumption display mode and the second power consumption display mode each include a mode of alternately inputting data to odd lines and even lines of different frames, including:

s21: the data signal is input to the odd rows of the second frame group and the even rows close the data input.

Specifically, the odd-numbered rows of the second frame group are turned on by the gate driving unit 30 controlling the scan lines gate to be turned on, and the first switching transistors t1 are controlled to be turned on by the first signal control line V1, so that the data lines data can charge the pixel cells 10 of the odd-numbered rows in the second frame group. Meanwhile, the negative pressure of the second switching transistor t2 connected to the first reference voltage VGL1 is controlled through the first signal control line V1, so that the second switching transistor t2 is kept off, then the data line data cannot write data into the pixel units 10 of the even rows, so that the data of the even rows cannot be rewritten, a constant current signal is applied, at the moment, the odd rows display normal pictures, the even rows display black pictures, and the data signals do not need to be switched back and forth between high and low levels in a mode of alternately inputting the data of the odd rows and the even rows, so that power consumption can be saved.

S22: the data signal is turned off for the odd lines of the third frame group and the data signal is input for the even lines.

Specifically, the case of the third frame group and the case of the second frame group can be understood as the opposite case, that is, in the third frame group, data writing is not performed to the pixel cells 10 of the odd-numbered rows, but data writing is performed to the pixel cells 10 of the even-numbered rows. The scan line gate may be controlled to be turned on by the gate driving unit 30, and the third switching transistor t3 may be controlled to be turned on by the second signal control line V2, so that the data line data may charge the pixel cells 10 of the even numbered rows within the third frame group. Meanwhile, the negative pressure of the fourth switching transistor t4 connected to the second reference voltage VGL2 is controlled through the second signal control line V2, so that the fourth switching transistor t4 is kept turned off, and then the data line data cannot write data into the pixel units 10 of the odd rows, so that the data of the odd rows cannot be rewritten, but a constant current signal is applied, at this time, the even rows display normal pictures, and the odd rows display black pictures. Also, since the data signal does not need to be switched back and forth between the high and low levels by alternately performing the data input in the odd and even rows, power consumption can be saved.

The following describes in detail the display of a plurality of frame periods and frame groups of the present application in specific embodiments.

Referring to fig. 8 to 11, fig. 8 is a schematic diagram showing an opening mode of a scan line according to a comparative example provided by the present application; FIG. 9 is a schematic diagram showing the opening mode of the scan line according to the first embodiment of the present application; FIG. 10 is a schematic diagram of a data line transmission scheme according to a comparative example provided by the present application; fig. 11 is a schematic diagram of a data line transmission mode according to the first embodiment of the present application.

First embodiment:

In this embodiment, the frame period takes 6 frames as a period, the first frame group includes 0 th to 1 st frames, the second frame group includes 2 nd to 3 rd frames, and the third frame group includes 4 th to 5 th frames. In the 0 th to 1 st frame, the control circuit 70 controls the gate driving units 30 of the odd lines and the even lines to be in an on state, and data is input to the pixel units 10 of the odd lines and the even lines through the data lines data, so that the frames in the 0 th to 1 st frame display normal frames. As in fig. 11 and 12, the reference line 80 is above a positive polarity voltage and the reference line 80 is below a negative polarity voltage, as is the case in other embodiments.

As shown in fig. 10, in the comparative example provided by the present application, in the 0 th to 2 th frames, the voltage input to the pixel unit 10 by the data line data needs to be frequently switched back and forth between the positive polarity voltage and the negative polarity voltage, so that the energy consumption of the display panel 200 is high. As shown in fig. 11, in the 0 th to 1 st frames, the data line data inputs a positive polarity voltage to the pixel cell 10 of the 0 th frame, and the data line data inputs a negative polarity voltage to the pixel cell 10 of the 1 st frame. Therefore, the application alternately inputs data to the pixel units 10 of the odd lines and the even lines through the data line data, thereby reducing the voltage switching back and forth between positive polarity and negative polarity and saving the power consumption.

In the first implementation manner of the present embodiment, in the 2 nd to 3 rd frames, the control circuit 70 controls the gate driving units 30 of the odd lines to be in an on state, controls the gate driving units 30 of the even lines to be in an off state, inputs data to the pixel units 10 of the odd lines through the data lines data, and closes data writing to the pixel units 10 of the even lines, so that the odd lines display normal images and the even lines display black images. And in the 4 th to 5 th frames, the control circuit 70 controls the even-numbered gate driving units 30 to be in an on state and controls the odd-numbered gate driving units 30 to be in an off state, data is input to the even-numbered pixel units 10 through the data lines data, and data writing is closed to the odd-numbered pixel units 10, so that the even-numbered lines display normal pictures and the odd-numbered lines display black pictures. As shown in fig. 2, assuming that the scan line gate of the odd-numbered row is turned on in the 2-3 th frame, for example, the first sub-pixel 11 of the odd-numbered row is a red pixel, the second sub-pixel 12 is a green pixel, and the third sub-pixel 13 is a blue pixel when viewed from the column direction of the data line data, at this time, the data line data charges the pixel unit 10 of the odd-numbered row, all of the red, green, and blue sub-pixels are lit, and the even-numbered row is a black screen, but all of the even-numbered row is lit from the display panel 200 as a whole, and a normal screen is displayed, as shown in table 1, the odd-numbered row is 1, and the even-numbered row is 0. In the 4 th to 5 th frames, when the scan line gate of the even line is turned on, for example, the first sub-pixel 11 of the even line is a red pixel, the second sub-pixel 12 is a green pixel, and the third sub-pixel 13 is a blue pixel as viewed from the column direction of the data line data, and at this time, the data line data charges the pixel unit 10 of the even line, and all of the red, green, and blue sub-pixels are lit, and the odd line is a black screen, but is lit as viewed from the whole of the display panel 200, and a normal screen is displayed. As shown in table 1, it is indicated by the digital signal that even lines are all 1 and odd lines are all 0.

Or in the second implementation manner of this embodiment, the odd-numbered lines and the even-numbered lines of the 2 th to 3 rd frames and the 4 th to 5 th frames are switched in an open manner. The method specifically comprises the following steps: in the 2 nd to 3 rd frames, the control circuit 70 controls the gate driving units 30 of the even lines to be in an on state, controls the gate driving units 30 of the odd lines to be in an off state, inputs data to the pixel units 10 of the even lines through the data lines data, and closes data writing to the pixel units 10 of the odd lines so that the even lines display normal pictures and the odd lines display black pictures. And in the 4 th to 5 th frames, the control circuit 70 controls the gate driving units 30 of the odd lines to be in an on state, controls the gate driving units 30 of the even lines to be in an off state, inputs data to the pixel units 10 of the odd lines through the data lines data, and closes data writing to the pixel units 10 of the even lines so that the odd lines display normal pictures and the even lines display black pictures. The implementation details of this implementation are the same as those in the first implementation, and are not repeated here.

As shown in fig. 12, in the 2 nd to 3 rd frames, the data line data inputs a positive polarity voltage to the pixel cell 10 of the 2 nd frame and inputs a negative polarity voltage to the pixel cell 10 of the 3 rd frame. In the 4 th to 5 th frames, the data line data inputs a positive polarity voltage to the pixel cell 10 of the 4 th frame and inputs a negative polarity voltage to the pixel cell 10 of the 5 th frame. That is, the positive polarity voltage and the negative polarity voltage are alternately input within the consecutive frames of the same frame group, so that power consumption can be reduced.

Second embodiment:

referring to fig. 12, fig. 12 is a schematic diagram illustrating a data line transmission mode according to a second embodiment of the present application.

In this embodiment, the frame period takes the normal display period of 6 frames and even frames as a period, wherein the data input manner in the 6 frames is the same as that in the first embodiment, the 6 frames also include three frame groups, the first frame group includes 0 th to 1 st frames, the second frame group includes 2 nd to 3 rd frames, and the third frame group includes 4 th to 5 th frames. Wherein the second frame group and the third frame group comprise an alternate data input mode of odd lines and even lines. The data input manner in the three frame groups of the frame of embodiment 6 is the same as that in the first embodiment, and will not be described here again.

In the present embodiment, a normal display period of a group of even frames is set in addition to 6 frames, for example, a normal display period of an even frame such as 2, 4, 6 or 8, and 6+2, 6+4, etc. are formed as one frame period. In a normal display period of an even frame, the data line data inputs voltages including positive and negative polarities to the pixel cells 10 of both the odd and even rows. That is, in an even frame other than 6 frames, the data input is performed for both the odd and even rows in each frame. As shown in table 2, table 2 is a mode switching example of a plurality of display modes provided in the second embodiment of the present application.

TABLE 2

Even frames are exemplified by 2 frames. Since the inversion of the liquid crystal has positive and negative polarities, if the switching is performed only in the positive polarity region, the polarization of the liquid crystal is caused, and the normal display period of even frames is that the voltages are switched in both positive and negative polarities every frame. After the complete cycles of positive polarity and negative polarity are completed, the next cycle is switched, so that the problems of risk of liquid crystal polarization, difference of brightness of positive electrodes and negative electrodes, picture flickering and the like can be further avoided, and the display effect is further improved.

It can be understood that in the present embodiment, the normal display period of 6 frames and even frames is taken as a period, and the power consumption is increased compared with that in the first embodiment, but the application requirement of the market for multiple functions can be satisfied, so that the application prospect is also wider. The number of the even frames which is increased specifically on the basis of 6 frames can be flexibly set according to the needs.

Third embodiment:

referring to fig. 13, fig. 13 is a schematic diagram illustrating a data line transmission mode according to a third embodiment of the present application.

As shown in fig. 13, in this embodiment, the frame period takes 3 frames as a period, the first frame group includes the 0 th frame, the second frame group includes the 1st frame, and the third frame group includes the 2 nd frame.

Specifically, in the 0 th frame, the gate driving units 30 of the odd and even rows are controlled to be in an on state by the control circuit 70, and data is input to the pixel units 10 of the odd and even rows through the data line data, so that the 0 th frame displays a normal picture.

In the first implementation manner of the present embodiment, in the 1 st frame, the control circuit 70 controls the gate driving units 30 of the odd lines to be in an on state, and controls the gate driving units 30 of the even lines to be in an off state, data is input to the pixel units 10 of the odd lines through the data lines data, and data writing is turned off to the pixel units 10 of the even lines, so that the odd lines display a normal picture and the even lines display a black picture. And in the 2 nd frame, the gate driving unit 30 of the even line is controlled to be in an on state by the control circuit 70, and the gate driving unit 30 of the odd line is controlled to be in an off state, data is input to the pixel unit 10 of the even line through the data line data, and data writing is closed to the pixel unit 10 of the odd line, so that the even line displays a normal picture, and the odd line displays a black picture.

Or in the second implementation manner of the present embodiment, in the 1 st frame, the control circuit 70 controls the gate driving units 30 of the even rows to be in an on state, and controls the gate driving units 30 of the odd rows to be in an off state, data is input to the pixel units 10 of the even rows through the data lines data, and data writing is turned off to the pixel units 10 of the odd rows, so that the even rows display a normal picture, and the odd rows display a black picture. And in the 2 nd frame, the control circuit 70 controls the gate driving units 30 of the odd lines to be in an on state, and controls the gate driving units 30 of the even lines to be in an off state, data is input to the pixel units 10 of the odd lines through the data lines data, and data writing is closed to the pixel units 10 of the even lines, so that the odd lines display normal pictures and the even lines display black pictures.

The third embodiment is different from the first and second embodiments in that only one frame is included in each frame group of one frame period, and thus there is no switching of positive polarity and negative polarity voltages in each frame group, and the voltages need to cross positive polarity and negative polarity simultaneously in 1 frame of each frame group. That is, in the 0 th, 1 st and 2 nd frames, the data line data inputs voltages across positive and negative polarities to the pixel unit 10. For example, in a 6-frame product with a period, the voltage is 0 v-16 v, the positive polarity voltage of the normal picture is 15 v-8 v, the negative polarity voltage is 0 v-7 v, the voltage span is only 7v, but when the positive and negative polarities of the voltage are not reversed, the voltage primary span needs to reach 14-15 v, and the relative current is larger.

In any of the above embodiments, in the second frame group and the third frame group, the gate driving unit 30 may adjust the on time of the scan line gate, that is, the on width of the scan line gate may be adjusted, so that the charge amount of the pixel unit 10 corresponding to the scan line gate reaches the preset charge amount, so that the pixel unit 10 is fully charged. In the embodiment provided by the application, the scan lines gate of the odd-numbered lines and the even-numbered lines in the second frame group and the third frame group are alternately turned on, and when the pixel units 10 of the previous line are charged, the scan lines gate of the next line are in the off state, so that there is no risk of filling the wrong line.

In any of the above embodiments, as shown in table 1, fig. 9 to 12, when the gate driving units 30 of the odd-numbered rows are in the on state and the gate driving units 30 of the even-numbered rows are in the off state, the data input of the pixel units 10 of the even-numbered rows follows the data of the odd-numbered rows, and the data of the odd-numbered rows are consistent. Since the scan lines gate of the even rows are electrically connected to the second reference voltage VGL2 when the gate-driven cells of the even rows are in the off state, the pixel unit 10 cannot write data. The even-numbered data voltages directly follow the odd-numbered rows, so that the data voltages cannot be subjected to positive and negative polarity inversion in one frame group, the voltage inversion times can be reduced by half, the required current can be lower, and the power consumption is reduced.

When the gate driving units 30 of the even-numbered rows are in the on state and the gate driving units 30 of the odd-numbered rows are in the off state, the data input of the pixel units 10 of the odd-numbered rows follows the data of the even-numbered rows and is consistent with the data of the even-numbered rows. Similarly, since the scan lines gate of the odd-numbered rows are electrically connected to the second reference voltage VGL2 when the gate-driven cells of the odd-numbered rows are in the off state, the pixel unit 10 cannot write data. The liquid crystals of the odd lines are not turned over, and the data voltages of the odd lines directly follow the even lines, so that the data voltages cannot be turned over in positive and negative polarities in one frame group, the voltage turning times can be reduced by half, the required current can be lower, and the power consumption is reduced.

As shown in table 1, in the first frame group, in the normal display mode, the data voltage is switched between high and low levels, so that the gray scale of the display screen is switched between 0 and 255, and the power consumption is high. In the second frame group and the third frame group, the data input of the pixel units 10 corresponding to the turned-off line scan line directly follows the data input of the pixel units 10 of the previous line, for example, the voltage input of the second frame group is positive, the input data gray scale is 255, the voltage of the third frame group is low, and the input data gray scale is 0, so that the voltage in the frame group does not need to be turned between the positive and negative polarities, and the voltage polarity is halved, thereby reducing the overall power consumption of the display panel 200.

In the 6 frames of the first embodiment and the second embodiment, the switching times of the data signals between the high level and the low level are halved within the total time of 4 frames of the 2 th to 5 th frames, so that the power consumption of the display panel 200 is greatly reduced.

The driving method of the display panel 200 disclosed in the present application includes: acquiring a preset number of continuous multi-frame pictures, and judging whether the data of the continuous multi-frame pictures are the same or not; the continuous multi-frame picture comprises a plurality of frame periods, and each frame period comprises a plurality of frame groups, namely a first frame group, a second frame group and a third frame group; responding to the same data of continuous multi-frame pictures, controlling the first frame group to enter a normal display mode through a time sequence controller, controlling the second frame group to enter a first power consumption display mode, and controlling the third frame group to enter a second power consumption display mode; the first power consumption display mode is different from the second power consumption display mode, and the first power consumption display mode and the second power consumption display mode both comprise a mode of alternately inputting data to odd lines and even lines of different frames of pictures. According to the application, the plurality of frame groups adopting the first power consumption display mode or the second power consumption display mode are arranged in the same frame period, so that data input is alternately carried out on odd lines and even lines of different frame pictures, thereby reducing the condition of frequent switching between high and low levels during data input, reducing the power consumption of the display panel, prolonging the service life of the display panel and reducing the cost.

The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.

Claims (8)

1. A driving method of a display panel is characterized in that the display panel comprises a normal display mode, a first power consumption display mode and a second power consumption display mode; the driving method includes:

acquiring a preset number of continuous multi-frame pictures, and judging whether the data of the continuous multi-frame pictures are the same or not; the continuous multi-frame picture comprises a plurality of frame periods, wherein each frame period comprises a plurality of frame groups, namely a first frame group, a second frame group and a third frame group;

responding to the fact that the data of the continuous multi-frame pictures are the same, controlling the first frame group to enter the normal display mode through a time sequence controller, controlling the second frame group to enter the first power consumption display mode, and controlling the third frame group to enter the second power consumption display mode;

The first power consumption display mode is different from the second power consumption display mode, and the first power consumption display mode and the second power consumption display mode both comprise a mode of alternately inputting data to odd lines and even lines of different frames of pictures;

wherein said controlling, by said timing controller, said first frame group to enter said normal display mode comprises:

Inputting a normal data signal including positive and negative polarities to the first frame group;

the first power consumption display mode and the second power consumption display mode both comprise a mode of alternately inputting data to odd lines and even lines of different frames of pictures, and the method comprises the following steps:

Inputting data signals to odd lines of the second frame group, and closing data input to even lines;

closing data signals for odd lines and inputting data signals for even lines of the third frame group; or alternatively, the first and second heat exchangers may be,

Inputting data signals to even rows of the second frame group, and closing data input to odd rows;

closing data signals for even rows of the third frame group, and inputting data signals for odd rows;

the data input is circularly carried out in the plurality of frame periods, and the data input modes of the same frame group in the plurality of frame periods can be the same or different;

when the grid driving units of the odd lines are in an open state and the grid driving units of the even lines are in a closed state, the data input of the pixel units of the even lines follow the data of the odd lines and keep consistent with the data of the odd lines;

When the gate driving units of the even-numbered rows are in an open state and the gate driving units of the odd-numbered rows are in a closed state, the data input of the pixel units of the odd-numbered rows follows the data of the even-numbered rows and is consistent with the data of the even-numbered rows.

2. The method of claim 1, wherein the frame period is a period of 6 frames, the first frame group comprises frames 0-1, the second frame group comprises frames 2-3, and the third frame group comprises frames 4-5; in the 0 th to 1 th frames, the grid driving units of the odd lines and the even lines are controlled to be in an open state through a control circuit, and data are input to the pixel units of the odd lines and the even lines through data lines so that the frames in the 0 th to 1 th frames display normal frames; in the 0 th to 1 th frames, the data line inputs positive polarity voltage to the pixel unit of the 0 th frame, and the data line inputs negative polarity voltage to the pixel unit of the 1 st frame;

In the 2 nd to 3 rd frames, the gate driving units of the odd lines are controlled to be in an open state by the control circuit, the gate driving units of the even lines are controlled to be in a closed state, data are input to the pixel units of the odd lines by the data lines, and data writing is closed to the pixel units of the even lines, so that normal pictures are displayed on the odd lines, and black pictures are displayed on the even lines; and in the 4 th to 5 th frames, controlling the gate driving units of the even lines to be in an on state and controlling the gate driving units of the odd lines to be in an off state by the control circuit, inputting data to the pixel units of the even lines by the data lines, and closing data writing to the pixel units of the odd lines so that the even lines display normal pictures and the odd lines display black pictures; or alternatively, the first and second heat exchangers may be,

In the 2 nd to 3 rd frames, the gate driving units of the even lines are controlled to be in an open state by the control circuit, the gate driving units of the odd lines are controlled to be in a closed state, data are input to the pixel units of the even lines by the data lines, data writing is closed to the pixel units of the odd lines, so that normal pictures are displayed on the even lines, and black pictures are displayed on the odd lines; and in the 4 th to 5 th frames, controlling the gate driving units of the odd lines to be in an on state and controlling the gate driving units of the even lines to be in an off state by the control circuit, inputting data to the pixel units of the odd lines by the data lines, and closing data writing to the pixel units of the even lines so that the odd lines display normal pictures and the even lines display black pictures;

in the 2 nd to 3 rd frames, the data line inputs positive polarity voltage to the pixel unit of the 2 nd frame and inputs negative polarity voltage to the pixel unit of the 3 rd frame; and in the 4 th to 5 th frames, the data line inputs positive polarity voltage to the pixel unit of the 4 th frame and inputs negative polarity voltage to the pixel unit of the 5 th frame.

3. The method according to claim 2, wherein the frame period is one period of a normal display period of 6 frames and an even frame, wherein the data line inputs voltages including positive and negative polarities to the pixel cells of both the odd and even rows during the normal display period of the even frame.

4. The method of claim 1, wherein the frame period is one period of 3 frames, the first frame group includes frame 0, the second frame group includes frame 1, and the third frame group includes frame 2;

in the 0 th frame, the grid driving units of the odd lines and the even lines are controlled to be in an open state through a control circuit, and data are input to the pixel units of the odd lines and the even lines through data lines so that the 0 th frame displays a normal picture;

In the 1 st frame, the gate driving units of the odd lines are controlled to be in an open state by the control circuit, the gate driving units of the even lines are controlled to be in a closed state, data are input to the pixel units of the odd lines by the data lines, and data writing is closed to the pixel units of the even lines, so that the odd lines display normal pictures, and the even lines display black pictures; and in the 2 nd frame, controlling the gate driving units of the even lines to be in an on state and controlling the gate driving units of the odd lines to be in an off state by the control circuit, inputting data to the pixel units of the even lines by the data lines, and closing data writing to the pixel units of the odd lines so that the even lines display normal pictures and the odd lines display black pictures; or alternatively, the first and second heat exchangers may be,

In the 1 st frame, the gate driving units of the even lines are controlled to be in an open state by the control circuit, the gate driving units of the odd lines are controlled to be in a closed state, data are input to the pixel units of the even lines by the data lines, and data writing is closed to the pixel units of the odd lines, so that the even lines display normal pictures, and the odd lines display black pictures; and in the 2 nd frame, controlling the gate driving units of the odd lines to be in an on state and controlling the gate driving units of the even lines to be in an off state by the control circuit, inputting data to the pixel units of the odd lines by the data lines, and closing data writing to the pixel units of the even lines so that the odd lines display normal pictures and the even lines display black pictures;

In the 0 th frame, the 1 st frame and the 2 nd frame, the data line inputs voltages of positive polarity and negative polarity to the pixel unit.

5. The method according to any one of claims 1 to 4, wherein in the second frame group and the third frame group, the gate driving unit adjusts an on time of a scanning line so that a charge amount of the pixel unit corresponding to the scanning line reaches a preset charge amount.

6. A pixel driving circuit includes a plurality of scanning lines and a plurality of data lines, and a plurality of pixel units driven by the plurality of scanning lines and the plurality of data lines, respectively; the pixel driving circuit is driven by the driving method according to any one of claims 1 to 5;

Wherein the pixel driving circuit further comprises:

The system control unit is used for acquiring data of continuous multi-frame pictures in the display pictures and carrying out similarity comparison and judgment on the data of the continuous multi-frame pictures;

The plurality of cascaded grid driving units are respectively coupled with the plurality of scanning lines in a one-to-one correspondence manner; a control circuit is arranged between each gate driving unit and each scanning line and used for controlling the connection and disconnection of the gate driving units and the scanning lines of the corresponding rows;

the time sequence controller is respectively and electrically connected with the system control unit and the grid driving unit; the time sequence controller is used for receiving the information of the system control unit, outputting a corresponding time sequence control signal to the control circuit based on the information, and outputting a corresponding driving signal to the grid driving unit through the control circuit so as to control the opening or closing of the scanning line of the corresponding row.

7. The pixel driving circuit according to claim 6, wherein the control circuit comprises:

A first signal control line, and first and second switching transistors electrically connected to the first signal control line, the first switching transistor being electrically connected to the scan lines of odd-numbered rows and the gate driving units corresponding to the scan lines; the second switching transistor is electrically connected with a first reference voltage;

A second signal control line, and third and fourth switching transistors electrically connected to the second signal control line, the third switching transistor electrically connected to the scan lines of even numbered rows and the gate driving units corresponding to the scan lines; the fourth switching transistor is electrically connected with a second reference voltage;

The first signal control line and the second signal control line are used for receiving signals of the time schedule controller and controlling the corresponding scanning lines of the odd lines or the even lines to be opened and closed;

The pixel driving circuit further includes:

And the level conversion unit is respectively coupled with the time schedule controller and the gate driving unit and is used for converting the data signals obtained from the time schedule controller into the signal format required by the gate driving unit and transmitting the converted data signals to the gate driving unit.

8. A display panel comprising an array substrate, a color film substrate and a liquid crystal layer disposed between the array substrate and the color film substrate, wherein the array substrate comprises the pixel driving circuit as claimed in claim 6 or 7.