Nothing Special   »   [go: up one dir, main page]

CN118263230A - Three-dimensional integrated structure - Google Patents

Three-dimensional integrated structure Download PDF

Info

Publication number
CN118263230A
CN118263230A CN202211642640.3A CN202211642640A CN118263230A CN 118263230 A CN118263230 A CN 118263230A CN 202211642640 A CN202211642640 A CN 202211642640A CN 118263230 A CN118263230 A CN 118263230A
Authority
CN
China
Prior art keywords
dummy
bonding
dielectric layer
semiconductor device
dimensional integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211642640.3A
Other languages
Chinese (zh)
Inventor
胡胜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan Xinxin Integrated Circuit Co ltd
Original Assignee
Wuhan Xinxin Integrated Circuit Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan Xinxin Integrated Circuit Co ltd filed Critical Wuhan Xinxin Integrated Circuit Co ltd
Priority to CN202211642640.3A priority Critical patent/CN118263230A/en
Publication of CN118263230A publication Critical patent/CN118263230A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a three-dimensional integrated structure. In the three-dimensional integrated structure, a first semiconductor device is bonded with a second semiconductor device so that a first dummy bonding pad is bonded with an opposite second dummy bonding pad, and a heat radiation shielding layer is provided in at least a partial region of a bonding interface formed by bonding the first semiconductor device and the second semiconductor device, wherein the heat radiation shielding layer comprises at least two first dummy bonding pads electrically connected with each other. The heat radiation shielding layer can improve the heat radiation capability of the three-dimensional integrated structure, reduce electromagnetic interference between different metal layers in the three-dimensional integrated structure, and utilize the first virtual bonding pad to construct the heat radiation shielding layer, so that the performance of the three-dimensional integrated structure is improved under the condition of not increasing cost and process complexity.

Description

Three-dimensional integrated structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional integrated structure.
Background
With the speed of moore's law slowed, integrated circuit fabrication has evolved to three-dimensional (3D) integration technologies in order to continue to improve the performance of Integrated Circuits (ICs). The three-dimensional integration technology can increase the integration level of the chip, improve the storage density and realize complex system functions.
At least two chip circuits are stacked and interconnected in the thickness direction by a three-dimensional integration technique to form a three-dimensional integrated structure. However, for three-dimensional integrated structures, one problem to be solved is how to eliminate the heat generated inside the structure, and the excessive heat can adversely affect the overall performance of the chip, and another problem to be solved is how to solve the electromagnetic interference between metal layers so as to reduce or avoid the coupling effect between different chip circuits.
Disclosure of Invention
In order to improve the heat dissipation capability of the three-dimensional integrated structure and reduce electromagnetic interference between metal layers, the invention provides the three-dimensional integrated structure.
The three-dimensional integrated structure provided by the invention comprises:
The first semiconductor device comprises a first substrate, a first dielectric layer formed on the first substrate and a plurality of first dummy bonding pads embedded in the first dielectric layer;
The second semiconductor device comprises a second substrate, a second dielectric layer formed on the second substrate and a plurality of second virtual bonding pads embedded in the second dielectric layer, wherein the first semiconductor device is bonded with the second semiconductor device so that the first virtual bonding pads are bonded and connected with the second opposite virtual bonding pads; and
And the heat dissipation shielding layer is positioned in at least part of the area of a bonding interface formed by bonding the first semiconductor device and the second semiconductor device, and comprises at least two first virtual bonding pads which are electrically connected with each other.
Optionally, in the heat dissipation shielding layer, at least two first dummy bonding pads are electrically connected through wires formed in the first dielectric layer and connected to the first dummy bonding pads.
Optionally, in the heat dissipation shielding layer, at least two first dummy bonding pads are electrically connected by bonding the second dummy bonding pads and using the second dummy bonding pads as wires.
Optionally, at least two first dummy bonding pads are connected to the second dummy bonding pad through bonding, and the second dummy bonding pad is used as a wire to realize electrical connection.
Optionally, in the heat dissipation shielding layer, each of the second dummy bonding pads is bonded with at least two of the first dummy bonding pads.
Optionally, the heat dissipation shielding layer further includes at least two second dummy bond pads electrically connected to each other.
Optionally, the first semiconductor device further includes a first interconnection structure, the first interconnection structure is formed on one side of the first substrate, and the first dielectric layer covers the first interconnection structure.
Optionally, at least one of the first dummy bond pads in the heat dissipation shielding layer is electrically connected to the first interconnect structure, so that the heat dissipation shielding layer is grounded through the first interconnect structure.
Optionally, the first semiconductor device further includes a first interconnection metal pad embedded in the first dielectric layer, and the first interconnection metal pad is electrically connected to the first interconnection structure through a first via hole formed in the first dielectric layer.
Optionally, the second semiconductor device further includes a second interconnect structure and a second interconnect metal pad, the second interconnect structure is formed on one side of the second substrate, the second dielectric layer covers the second interconnect structure, the second interconnect metal pad is embedded in the second dielectric layer and is electrically connected with the second interconnect structure through a second via hole formed in the second dielectric layer, and the first interconnect metal pad and the opposite second interconnect metal pad are bonded and connected.
Optionally, the heat dissipation shielding layer is a mesh structure, and at least half area of the heat dissipation shielding layer is covered by the first dummy bonding pad and the second dummy bonding pad.
In the three-dimensional integrated structure provided by the invention, the first semiconductor device is bonded with the second semiconductor device so that the first virtual bonding pad is bonded with the second opposite virtual bonding pad, and a heat dissipation shielding layer is arranged in at least part of a bonding interface formed by bonding the first semiconductor device and the second semiconductor device, and comprises at least two first virtual bonding pads electrically connected with each other. The heat radiation shielding layer can improve the heat radiation capability of the three-dimensional integrated structure, reduce electromagnetic interference between different metal layers in the three-dimensional integrated structure, and utilize the first virtual bonding pad to construct the heat radiation shielding layer, so that the performance of the three-dimensional integrated structure is improved under the condition of not increasing cost and process complexity.
Drawings
FIG. 1 is a schematic cross-sectional view of a three-dimensional integrated structure in accordance with one embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a three-dimensional integrated structure in accordance with another embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a three-dimensional integrated structure in accordance with yet another embodiment of the present invention.
Fig. 4 is a top view of a heat dissipation shield according to an embodiment of the invention.
Fig. 5 is a top view of a heat dissipation shield according to another embodiment of the present invention.
Fig. 6 is a top view of a heat dissipation shield in accordance with yet another embodiment of the present invention.
Detailed Description
The three-dimensional integrated structure of the present invention is described in further detail below with reference to the drawings and examples. The advantages and features of the present invention will become more apparent from the following description. It should be understood that the drawings in a very simplified form and to a non-precise scale are merely provided to facilitate a convenient and clear illustration of embodiments of the invention. The terms "first" and "second" and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances.
Embodiments of the present invention relate to a three-dimensional integrated structure including at least two wafers stacked in a thickness direction, or including at least two chips stacked in a thickness direction, or including at least one package substrate and at least one chip stacked in a thickness direction. The three-dimensional integrated structure may be a stacked wafer or a stacked chip. In the three-dimensional integrated structure, each wafer, package substrate or chip is used for forming a semiconductor device, and the semiconductor device can comprise at least one of an active device (such as a MOS device, a sensing device or a memory device, etc.) and a passive device (such as a resistor or a capacitor, etc.). For convenience of description, hereinafter, wafers, package substrates, or chips stacked in a three-dimensional integrated structure are referred to as semiconductor devices.
In the three-dimensional integrated structure of the embodiment of the present invention, at least one interface among the interfaces among the stacked wafers, package substrates, or chips is, for example, a hybrid bonding interface, that is, semiconductor devices located on both sides of the hybrid bonding interface are bonded by hybrid bonding (hybridbonding, or referred to as metal/dielectric layer hybrid bonding), which is a technique of forming direct bonding without using an intermediate layer such as solder or adhesive, and by hybrid bonding, metal-metal bonding, dielectric layer-dielectric layer bonding, and metal-dielectric layer bonding can be simultaneously obtained. In the three-dimensional integrated structure, the virtual bonding pad positioned at the hybrid bonding interface is used for heat dissipation and signal shielding, and the performance of the three-dimensional integrated structure can be improved under the condition that the cost and the process complexity are not required to be increased.
FIG. 1 is a schematic cross-sectional view of a three-dimensional integrated structure according to one embodiment of the present invention. Referring to fig. 1, in an embodiment of the present invention, a three-dimensional integrated structure includes a first semiconductor device 100 and a second semiconductor device 200.
Specifically, the first semiconductor device 100 may include a first substrate 110, a first interconnect structure 120 formed on the first substrate 110, and a first dielectric layer 130, where the first dielectric layer 130 covers the first interconnect structure 120. The second semiconductor device 200 may include a second substrate 210, a second interconnect structure 220 formed on the second substrate 210, and a second dielectric layer 230, the second dielectric layer 230 covering the second interconnect structure 220.
Illustratively, the first substrate 110 includes a front surface and a back surface opposite to each other, wherein the front surface is a main surface of the first substrate 110, and electronic components may be formed near the front surface of the first substrate 110, and the first interconnect structure 120 is formed on, for example, a front side of the first substrate 110, and the first interconnect structure 120 may be connected to contact terminals of the electronic components formed near the front surface of the first substrate 110; however, the first interconnection structure 120 is not limited thereto, and the first interconnection structure 120 may be formed on the rear surface side of the first substrate 110, and the first interconnection structure 120 may be electrically connected to a metal layer formed on the front surface side of the first substrate 110 through a TSV penetrating the first substrate 110.
Illustratively, the second substrate 210 includes a front surface and a back surface opposite to each other, wherein the front surface is a main surface of the second substrate 210, and an electronic component may be formed near the front surface of the second substrate 210. The second substrate 210 may be subjected to a thinning process, the second interconnection structure 220 is formed, for example, on a rear side of the second substrate 210, and the second interconnection structure 220 may be electrically connected to a metal layer formed on a front side of the second substrate 210 through a TSV (not shown) penetrating the second substrate 210; however, the second interconnection structure 220 is not limited thereto, and the second interconnection structure 220 may be formed on the front side of the second substrate 210, and the second interconnection structure 220 may be connected to a contact terminal of an electronic component formed near the front side of the second substrate 210.
The first interconnect structure 120 and the second interconnect structure 220 may include one or more metal layers (e.g., re-wiring layers, RDLs) separated from each other by a dielectric material, and the first interconnect structure 120 and the second interconnect structure 220 may further include a via hole penetrating the dielectric material to connect adjacent metal layers. For clarity, only one metal layer in the first interconnect structure 120 and one metal layer in the second interconnect structure 220 are shown in fig. 1.
In the first semiconductor device 100, a surface of the first dielectric layer 130 on a side away from the first substrate 110 is used for bonding with the second semiconductor device 200, and in the second semiconductor device 200, a surface of the second dielectric layer 230 on a side away from the second substrate 210 is used for bonding with the first semiconductor device 100. The first dielectric layer 130 and the second dielectric layer 230 may comprise one or a combination of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and nitrogen doped silicon carbide (NDC). Illustratively, the first dielectric layer 130 includes a first silicon nitride film 131 covering the first interconnect structure 120, a first silicon oxide film 132 stacked on the surface of the first silicon nitride film 131, and a first nitrogen-doped silicon carbide film 133 stacked on the surface of the first silicon oxide film 132, and the second dielectric layer 230 includes a second silicon nitride film 231 covering the second interconnect structure 220, a second silicon oxide film 232 stacked on the surface of the second silicon nitride film 231, and a second nitrogen-doped silicon carbide film 233 stacked on the surface of the second silicon oxide film 232.
The first semiconductor device 100 further includes a metal bonding pad formed on the surface of the first dielectric layer 130, and the second semiconductor device 200 further includes a metal bonding pad formed on the surface of the second dielectric layer 230. The metal bond pad may include at least one of elemental metal (e.g., copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, cobalt, molybdenum, platinum, aluminum, hafnium, ruthenium, etc.) and an alloy (e.g., copper alloy or aluminum alloy, etc.), for example, copper is used in this embodiment. As an example, when forming the corresponding metal bonding pad on the surface of the first dielectric layer 130, an opening may be formed on the surface of the first dielectric layer 130, then the opening is filled with a metal material, and then the top surface of the metal material is subjected to CMP processing, so as to remove the metal material covered on the first dielectric layer 130, and the metal material remaining in the opening forms the metal bonding pad. When bonding, the first dielectric layer 130 and the metal bonding pad embedded in the first dielectric layer 130 are opposite to and bonded with the second dielectric layer 230 and the metal bonding pad embedded in the second dielectric layer 230, and in particular, a homogeneous bonding (such as metal-metal bonding and dielectric layer-dielectric layer bonding) interface and a heterogeneous bonding (such as metal-dielectric layer bonding) interface can be formed.
Specifically, as shown in fig. 1, the first semiconductor device 100 includes, for example, a first interconnection metal pad 140 embedded in the first dielectric layer 130, where the first interconnection metal pad 140 may be electrically connected to the first interconnection structure 120 through a first via 130a formed in the first dielectric layer 130. The second semiconductor device 200, for example, includes a second interconnect metal pad 240 embedded in the second dielectric layer 230, where the second interconnect metal pad 240 may be electrically connected to the second interconnect structure 220 through a second via 230a formed in the second dielectric layer 230. The first dielectric layer 130 may have a surface formed with a plurality of first interconnect metal pads 140 and the second dielectric layer 230 may have a surface formed with a plurality of second interconnect metal pads 240, depending on the particular interconnect arrangement of the first semiconductor device 100 and the second semiconductor device 200. The first and second interconnection metal pads 140 and 240 are, for example, configured in a one-to-one correspondence, and each pair of mutually corresponding first and second interconnection metal pads 140 and 240 are electrically contacted by bonding such that the first and second interconnection structures 120 and 220 form an electrical connection.
As shown in fig. 1, the first semiconductor device 100 further includes a first dummy bond pad 150 embedded in the first dielectric layer 130, and the second semiconductor device 200 further includes a second dummy bond pad 250 embedded in the second dielectric layer 230. The "dummy" herein refers to that the first dummy bond pad 150 and the second dummy bond pad 250 are not used to electrically connect the first interconnect structure 120 and the second interconnect structure 220. In this embodiment, the first dummy bond pad 150 and the first interconnect metal pad 140 formed on the surface of the first dielectric layer 130 are electrically isolated, and the second dummy bond pad 250 and the second interconnect metal pad 240 formed on the surface of the second dielectric layer 230 are electrically isolated. By providing the first dummy bond pad 150 and the second dummy bond pad 250, in the process of manufacturing the metal bond pad, the surface flatness of the first dielectric layer 130 and the second dielectric layer 230 after a Chemical Mechanical Polishing (CMP) process can be improved, the density of the metal bond pad in the bonding interface can be adjusted, the bonding strength can be improved, and the reliability of the bonding process can be ensured.
In the embodiment of the present invention, the first dummy bond pad 150 and the second dummy bond pad 250 are further used for dissipating heat and shielding electromagnetic interference between metal layers in the first semiconductor device 100 and the second semiconductor device 200, so as to reduce or avoid coupling effects between circuits of the first semiconductor device 100 and the second semiconductor device 200. Specifically, the three-dimensional integrated structure further includes a heat dissipation shielding layer 10, where the heat dissipation shielding layer 10 is located in at least a partial area of a bonding interface formed by bonding the first semiconductor device 100 and the second semiconductor device 200, and includes at least two first dummy bonding pads 150 electrically connected to each other. In the embodiment of the present invention, the first dummy bond pad 150 is multiplexed, and is used as both a bonding element of the first semiconductor device 100 and a heat dissipation shielding element of the three-dimensional integrated structure.
Alternatively, all of the first dummy bond pads 150 at the bond interface may be electrically connected to each other to form a heat spreader shield 10. However, in one embodiment, in a portion of the bonding interface, the first dummy bonding pads 150 are electrically connected to each other to form a heat dissipation shielding layer 10. In another embodiment, the bonding interface includes a plurality of regions formed with the first dummy bonding pads 150, and at least two first dummy bonding pads 150 in each region are electrically connected to each other to form a heat dissipation shielding layer 10, and each heat dissipation shielding layer 10 is located in a different region of the bonding interface.
Since the first dummy bond pad 150 is bonded to the second dummy bond pad 250 at the bonding interface, the heat spreader 10 may further include the second dummy bond pad 250 bonded to the first dummy bond pad 150. In one embodiment, the heat dissipation shielding layer 10 further includes at least two second dummy bonding pads 250, and the at least two second dummy bonding pads 250 are electrically connected to each other.
Referring to fig. 1, in an embodiment of the heat dissipation shielding layer 10, at least two first dummy bonding pads 150 are electrically connected by bonding a second dummy bonding pad 250 and using the second dummy bonding pad 250 as a wire. In this embodiment, at least a portion of the first dummy bond pads 150 are bonded with the second dummy bond pads 250 in an offset manner. Specifically, among the at least two first dummy bond pads 150 included in the heat dissipation shielding layer 10, two adjacent first dummy bond pads 150 can be bonded to the same second dummy bond pad 250, and the second dummy bond pad 250 is used as a wire (or an electrical connector), so that the two adjacent first dummy bond pads 150 are electrically connected. When the heat dissipation shielding layer 10 further includes at least two second dummy bonding pads 250, the second dummy bonding pads 250 may be electrically connected by bonding with the first dummy bonding pads 150 and using the first dummy bonding pads 150 as wires.
Referring to fig. 2, in another embodiment, at least two first dummy bond pads 150 in the heat dissipation shielding layer 10 are electrically connected through wires 151 formed in the first dielectric layer 130 and connected to the first dummy bond pads 150. That is, the first dummy bond pads 150 may not be electrically connected through the second dummy bond pads 250, but rather form an electrical connection within the first semiconductor device 100. In this embodiment, for the first dummy bond pads 150 electrically connected by wires formed in the first dielectric layer 130, the second dummy bond pads 250 may be aligned with or offset from bonding. In one embodiment, the width of the conductive line formed in the first dielectric layer 130 is smaller than the width of the first dummy bond pad 150, for example. In one embodiment, the thickness of the conductive line formed in the first dielectric layer 130 is smaller than that of the first dummy bond pad 150, for example.
Referring to fig. 3, in still another embodiment, in the heat dissipation shielding layer 10, for two adjacent first dummy bonding pads 150, the number of the first dummy bonding pads 150 in at least one portion of the first dummy bonding pads 150 is greater than or equal to 2, and each first dummy bonding pad 150 is electrically connected through a wire formed in the first dielectric layer 130 and connected to the first dummy bonding pad 150, and the two adjacent portions of the first dummy bonding pads 150 are electrically connected through a wire bonded to the second dummy bonding pad 250 and using the second dummy bonding pad 250 as a wire.
Similarly to the manner in which the first dummy bonding pad 150 is electrically connected, when the heat dissipation shielding layer 10 further includes at least two second dummy bonding pads 250 electrically connected to each other, the second dummy bonding pads 250 may be electrically connected to the first dummy bonding pad 150 by bonding and using the first dummy bonding pad 150 as a wire, or the second dummy bonding pads 250 may be electrically connected to each other by bonding wires formed in the second dielectric layer 230 and connected to the second dummy bonding pads 250, or for two adjacent portions of the second dummy bonding pads 250, the number of the second dummy bonding pads 250 in at least a portion of the second dummy bonding pads 250 is greater than or equal to 2, and each of the second dummy bonding pads 250 is electrically connected to each other by bonding wires formed in the second dielectric layer 230 and connected to the second dummy bonding pad 250, and the two adjacent portions of the second dummy bonding pads 250 are electrically connected to each other by bonding the first dummy bonding pad 150 and using the first dummy bonding pad 150 as a wire.
It should be noted that, the electrical connection manner of the first dummy bond pad 150 and/or the second dummy bond pad 250 in the heat dissipation shielding layer 10 is merely an example, and other electrical connection manners of the first dummy bond pad and/or the second dummy bond pad may be adopted in the three-dimensional integrated structure of the present invention.
Fig. 4 to 6 are top views of a heat dissipation shielding layer according to an embodiment of the present invention. Referring to fig. 4 to 6, in the heat dissipation shielding layer 10, a plurality of first dummy bonding pads 150 are disposed, for example, at intervals, on the surface of the first dielectric layer 130, and a plurality of second dummy bonding pads 250 are disposed, for example, at intervals, on the surface of the second dielectric layer 230. A portion of the orthographic projection of each second dummy bond pad 250 on the surface of the first dielectric layer 130 may coincide with at least two first dummy bond pads 150, and another portion of the orthographic projection of each second dummy bond pad 250 coincides with the first dielectric layer 130, so that each second dummy bond pad 250 is bonded to at least two first dummy bond pads 150 in the heat dissipation shield layer 10. In addition, a portion of the orthographic projection of each first dummy bond pad 150 on the surface of the second dielectric layer 230 may overlap with at least one second dummy bond pad 250, and another portion of the orthographic projection of the first dummy bond pad 150 overlaps with the second dielectric layer 230, so that each first dummy bond pad 150 is bonded to at least one second dummy bond pad 250 in the heat dissipation shield layer 10.
As shown in fig. 4, in one embodiment, each second dummy bond pad 250 is bonded to four first dummy bond pads 150, and each first dummy bond pad 150 is bonded to one, two or four second dummy bond pads 250 to form a mesh-shaped metal layer as the heat dissipation shielding layer 10. In another embodiment, as shown in fig. 5, each second dummy bonding pad 250 is bonded to two first dummy bonding pads 150, and each first dummy bonding pad 150 is bonded to two or three second dummy bonding pads 250 to form a mesh-shaped metal layer as the heat dissipation shielding layer 10. In yet another embodiment, as shown in fig. 6, a portion of each of the second dummy bond pads 250 is bonded to six first dummy bond pads 150, and a portion of each of the second dummy bond pads 250 is bonded to four first dummy bond pads 150, and each of the first dummy bond pads 150 is bonded to at least one second dummy bond pad 250 to form a mesh-shaped metal layer as the heat dissipation shielding layer 10. It should be noted that the arrangement and connection of the first dummy bond pad 150 and the second dummy bond pad 250 shown in fig. 4 to 6 are merely examples, and in other embodiments, other arrangements and connection of the first dummy bond pad 150 and the second dummy bond pad 250 may be used.
As shown in fig. 4 to 6, the heat dissipation shielding layer 10 is, for example, a mesh structure, and the area of the mesh structure is the sum of the area of the metal region formed by bonding the first dummy bonding pad 150 and the second dummy bonding pad 250 and the area of the mesh hole located between the metal regions. In order to enhance the heat dissipation effect and shielding effect of the heat dissipation shielding layer 10, the area ratio of the mesh holes in the heat dissipation shielding layer 10 may be reduced and the area ratio of the metal region may be increased, where appropriate, for example, in an embodiment, at least half of the area of the heat dissipation shielding layer 10 is covered by the first dummy bond pads 150 and the second dummy bond pads 250.
The heat sink shield 10 may be electrically connected to a ground element and thus to ground. The ground element may be formed in the first semiconductor device 100 or within the second semiconductor device 200. Referring to fig. 1 to 3, in the heat dissipation shielding layer 10, at least one of the first dummy bond pads 150 is electrically connected to the first interconnect structure 120 through a third via 130b formed in the first dielectric layer 130, so that the heat dissipation shielding layer 10 is grounded through the first interconnect structure 120. In the first interconnect structure 120, the metal layer portion connecting the heat dissipation shield layer 10 is isolated, e.g., insulated, from the metal layer portion connecting the first interconnect metal pad 140.
In the three-dimensional integrated structure of the embodiment of the present invention, the first semiconductor device 100 and the second semiconductor device 200 are bonded such that the first dummy bond pad 150 is bonded to the second opposing dummy bond pad 250, and the heat dissipation shielding layer 10 is provided in at least a partial region of a bonding interface formed by bonding the first semiconductor device 100 and the second semiconductor device 200, and the heat dissipation shielding layer 10 includes at least two first dummy bond pads 150 electrically connected to each other. The heat dissipation shielding layer 10 can improve the heat dissipation capability of the three-dimensional integrated structure, reduce the electromagnetic interference between different metal layers inside the three-dimensional integrated structure, and utilize the first dummy bonding pad 150 to construct the heat dissipation shielding layer 10, so that the heat dissipation shielding layer has the heat dissipation function and the electromagnetic shielding function in addition to the bonding function, and the performance of the three-dimensional integrated structure is improved without increasing the cost and the process complexity.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims (10)

1. A three-dimensional integrated structure, comprising:
The first semiconductor device comprises a first substrate, a first dielectric layer formed on the first substrate and a plurality of first dummy bonding pads embedded in the first dielectric layer;
The second semiconductor device comprises a second substrate, a second dielectric layer formed on the second substrate and a plurality of second virtual bonding pads embedded in the second dielectric layer, wherein the first semiconductor device is bonded with the second semiconductor device so that the first virtual bonding pads are bonded and connected with the second opposite virtual bonding pads; and
And the heat dissipation shielding layer is positioned in at least part of the area of a bonding interface formed by bonding the first semiconductor device and the second semiconductor device, and comprises at least two first virtual bonding pads which are electrically connected with each other.
2. The three-dimensional integrated structure of claim 1, wherein at least two of said first dummy bond pads in said thermal shield are electrically connected by wires formed in said first dielectric layer and connecting said first dummy bond pads.
3. The three-dimensional integrated structure of claim 1, wherein at least two of said first dummy bond pads in said thermal shield are electrically connected by bonding said second dummy bond pads and using said second dummy bond pads as wires.
4. The three-dimensional integrated structure of claim 1, wherein each of the second dummy bond pads is bonded to at least two of the first dummy bond pads in the thermal shield layer.
5. The three-dimensional integrated structure of claim 1, wherein the heat spreader shield further comprises at least two of the second dummy bond pads electrically connected to each other.
6. The three-dimensional integrated structure of claim 1, wherein the first semiconductor device further comprises:
and the first interconnection structure is formed on one side of the first substrate, and the first dielectric layer covers the first interconnection structure.
7. The three-dimensional integrated structure of claim 6, wherein at least one of the first dummy bond pads in the thermal shield is electrically connected to the first interconnect structure such that the thermal shield is grounded through the first interconnect structure.
8. The three-dimensional integrated structure of claim 6, wherein the first semiconductor device further comprises:
And the first interconnection metal pad is embedded in the first dielectric layer and is electrically connected with the first interconnection structure through a first via hole formed in the first dielectric layer.
9. The three-dimensional integrated structure of claim 8, wherein the second semiconductor device further comprises:
the second interconnection structure is formed on one side of the second substrate, and the second dielectric layer covers the second interconnection structure; and
And the second interconnection metal pad is embedded in the second dielectric layer and is electrically connected with the second interconnection structure through a second via hole formed in the second dielectric layer, and the first interconnection metal pad and the second interconnection metal pad which are opposite are in bonding connection.
10. The three-dimensional integrated structure of any one of claims 1-9, wherein the heat-dissipating shielding layer is a mesh structure and at least half of an area of the heat-dissipating shielding layer is covered by the first dummy bond pad and the second dummy bond pad.
CN202211642640.3A 2022-12-20 2022-12-20 Three-dimensional integrated structure Pending CN118263230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211642640.3A CN118263230A (en) 2022-12-20 2022-12-20 Three-dimensional integrated structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211642640.3A CN118263230A (en) 2022-12-20 2022-12-20 Three-dimensional integrated structure

Publications (1)

Publication Number Publication Date
CN118263230A true CN118263230A (en) 2024-06-28

Family

ID=91601064

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211642640.3A Pending CN118263230A (en) 2022-12-20 2022-12-20 Three-dimensional integrated structure

Country Status (1)

Country Link
CN (1) CN118263230A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118588657A (en) * 2024-08-07 2024-09-03 武汉新芯集成电路股份有限公司 Semiconductor device and layout design method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118588657A (en) * 2024-08-07 2024-09-03 武汉新芯集成电路股份有限公司 Semiconductor device and layout design method thereof

Similar Documents

Publication Publication Date Title
CN110060992B (en) Semiconductor package
CN110071070B (en) Semiconductor device and method for manufacturing the same
US10867897B2 (en) PoP device
KR101107806B1 (en) Bond pad design with reduced dishing effect
US20050101116A1 (en) Integrated circuit device and the manufacturing method thereof
CN112490235A (en) Integrated circuit, stack thereof and method for manufacturing the same
US20220310577A1 (en) Semiconductor package
CN103187396A (en) Semiconductor package with ultra-thin interposer without through-semiconductor vias
US11296037B2 (en) Semiconductor package
US9548283B2 (en) Package redistribution layer structure and method of forming same
CN106449579A (en) Semiconductor device and method of manufacturing the same
US9059067B2 (en) Semiconductor device with interposer and method manufacturing same
CN115831885A (en) Semiconductor package
US20240170440A1 (en) Semiconductor package
US20240055411A1 (en) Semiconductor devices with redistribution structures configured for switchable routing
KR20220077762A (en) Semiconductor packages including heat dissipation layer
CN116798993A (en) Package structure and method for forming the same
CN118263230A (en) Three-dimensional integrated structure
US20230033087A1 (en) Semiconductor package
TW202410373A (en) Semiconductor package and manufacturing method thereof
US9721928B1 (en) Integrated circuit package having two substrates
CN116114396A (en) Previous process interconnect structures and associated systems and methods
KR20230054192A (en) Semiconductor devices including substrates bonded each other and method for fabricating the same
KR20210145568A (en) Semiconductor devices including stacked substrates and method for fabricating the same
KR102628146B1 (en) Semiconductor packages and methods of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination