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CN118248746B - Low-leakage GaN Schottky diode and preparation method thereof - Google Patents

Low-leakage GaN Schottky diode and preparation method thereof Download PDF

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CN118248746B
CN118248746B CN202410674491.1A CN202410674491A CN118248746B CN 118248746 B CN118248746 B CN 118248746B CN 202410674491 A CN202410674491 A CN 202410674491A CN 118248746 B CN118248746 B CN 118248746B
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gan
gan layer
leakage
schottky diode
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CN118248746A (en
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武乐可
李亦衡
朱廷刚
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Jiangsu Corenergy Semiconductor Co ltd
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Jiangsu Corenergy Semiconductor Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204Diodes
    • H01L29/66212Schottky diodes

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention belongs to the technical field of Schottky diodes, and particularly relates to a low-leakage GaN Schottky diode and a preparation method thereof. The low leakage GaN Schottky diode provided by the invention comprises the following components: a substrate; the N+ GaN layer is arranged on the upper surface of the substrate and consists of a plane layer and a boss integrally arranged on the plane layer; the N-GaN layer is covered on the upper surface of the boss; the P-type GaN layer is arranged on the upper surface of the N-GaN layer part, the side wall of the N-GaN layer, the side wall of the boss and the upper surface of the plane layer part; the Schottky electrode is arranged on the residual upper surface of the N-GaN layer; an ohmic electrode disposed on the remaining upper surface of the planar layer; and the P-type GaN layer is not contacted with the Schottky electrode and the ohmic electrode. The low-leakage GaN Schottky diode provided by the invention can effectively prevent the leakage channel of the side wall, thereby effectively reducing the reverse leakage current.

Description

Low-leakage GaN Schottky diode and preparation method thereof
Technical Field
The invention belongs to the technical field of Schottky diodes, and particularly relates to a low-leakage GaN Schottky diode and a preparation method thereof.
Background
The characteristics of Si-based power electronics have approached the theoretical limit that Si materials can reach, and third generation semiconductors, typified by GaN, are preferred as next generation semiconductor power device materials. GaN has large forbidden bandwidth, high electron mobility and low dielectric constant, so that the GaN power device can be used in high-frequency and high-withstand voltage application scenes. Meanwhile, the GaN material has the advantages of very stable chemical property, radiation resistance and the like, and can stably work in a more severe environment.
The Schottky diode (SBD) manufactured by the GaN material has the characteristics of high current, high reverse withstand voltage, low recovery time and the like, and becomes a hot spot for power device research. The GaN SBD has a lateral structure, a quasi-vertical structure, and a vertical structure. The transverse structure has the characteristics of large current and high withstand voltage, but the device has the problem of current collapse due to the existence of surface states. The vertical structure has no current collapse, high withstand voltage, very high cost and difficult industrialization of the process technology. The GaN SBD with the quasi-vertical structure has the advantages of low cost, small on-resistance, no current collapse and easy industrialization, but the reverse electric leakage of the device is larger. Reverse leakage of the quasi-vertical structure GaN SBD occurs, with one portion flowing from the cathode to the anode through the bulk of the heavily doped N-type GaN layer (n+ GaN layer) and the lightly doped N-type GaN layer (N-GaN layer), and another portion flowing from the cathode to the anode through the surfaces of the n+ GaN and N-GaN.
Disclosure of Invention
The invention aims to provide a GaN Schottky diode with low electric leakage and a preparation method thereof, the low-leakage GaN Schottky diode provided by the invention can effectively prevent the leakage channel of the side wall, thereby effectively reducing the reverse leakage current.
In order to achieve the above object, the present invention provides the following technical solutions:
The invention provides a low-leakage GaN Schottky diode, which comprises the following components: a substrate; the N+ GaN layer is arranged on the upper surface of the substrate and consists of a plane layer and a boss integrally arranged on the plane layer; the N-GaN layer is covered on the upper surface of the boss; the P-type GaN layer is arranged on the upper surface of the N-GaN layer part, the side wall of the N-GaN layer, the side wall of the boss and the upper surface of the plane layer part; the Schottky electrode is arranged on the residual upper surface of the N-GaN layer; an ohmic electrode disposed on the remaining upper surface of the planar layer; and the P-type GaN layer is not contacted with the Schottky electrode and the ohmic electrode.
Preferably, the gap between the P-type GaN layer and the Schottky electrode is more than or equal to 5 mu m;
The gap between the P-type GaN layer and the ohmic electrode is more than or equal to 5 mu m.
Preferably, the material of the P-type GaN layer is Mg-doped GaN, and the doping concentration of Mg element in the Mg-doped GaN is more than 1 multiplied by 10 18cm-3.
Preferably, the doping concentration of the N+ GaN layer is more than 1 multiplied by 10 19cm-3; the thickness of the plane layer is 2-3 mu m and is not equal to 3 mu m; the thickness of the boss is less than or equal to 1 mu m.
Preferably, the doping concentration of the N-GaN layer is less than 1 multiplied by 10 19cm-3; the thickness of the N-GaN layer was 5. Mu.m.
Preferably, the schottky electrode comprises a contact layer and a metal layer arranged on the upper surface of the contact layer; the contact layer of the Schottky electrode is made of Ni, and the thickness of the contact layer is 100nm; the metal layer of the Schottky electrode is made of Au, and the thickness of the metal layer is 1000nm.
Preferably, the ohmic electrode comprises a contact layer and a metal layer arranged on the upper surface of the contact layer; the contact layer of the ohmic electrode is made of Ni, and the thickness of the contact layer is 20nm; the metal layer of the ohmic electrode is made of Al, and the thickness of the metal layer is 1000nm.
Preferably, the substrate is a sapphire substrate.
The invention provides a preparation method of the low-leakage GaN Schottky diode, which comprises the following steps:
Sequentially epitaxially growing an initial N+ GaN layer and an initial N-GaN layer on the upper surface of the substrate; etching the initial N+ GaN layer and the initial N-GaN layer according to the shapes and structures of the N+ GaN layer and the N-GaN layer to obtain the N+ GaN layer and the N-GaN layer; preparing a hard mask plate on the upper surface of the N-GaN layer part and the upper surface of the plane layer part, and then carrying out ion implantation on the remaining upper surface of the N-GaN layer, the side wall of the boss and the remaining upper surface of the plane layer to obtain a first semi-finished product;
Annealing the first semi-finished product in a protective gas atmosphere to obtain a P-type GaN layer, and obtaining a second semi-finished product;
And removing the hard mask plate from the second semi-finished product, and then preparing a Schottky electrode and an ohmic electrode to obtain the low-leakage GaN Schottky diode.
Preferably, the annealing treatment is carried out at 1250 ℃ for 30min and at normal pressure; the shielding gas is nitrogen.
The invention provides a low-leakage GaN Schottky diode (GaN SBD), comprising: a substrate; the N+ GaN layer is arranged on the upper surface of the substrate and consists of a plane layer and a boss integrally arranged on the plane layer; the N-GaN layer is covered on the upper surface of the boss; the P-type GaN layer is arranged on the upper surface of the N-GaN layer part, the side wall of the N-GaN layer, the side wall of the boss and the upper surface of the plane layer part; the Schottky electrode is arranged on the residual upper surface of the N-GaN layer; an ohmic electrode disposed on the remaining upper surface of the planar layer; and the P-type GaN layer is not contacted with the Schottky electrode and the ohmic electrode. The invention discovers that the side wall of the N-GaN layer and the side wall of the boss can generate conductive ions on the side wall area due to etching damage, and simultaneously some exogenous conductive ions can be attached to the side wall. Due to the presence of the conductive ions on the sidewall, a reverse leakage current is formed when a reverse voltage is applied to the device (high voltage is applied to the ohmic electrode). In the invention, the P-type GaN layer is arranged on the side wall of the N-GaN layer and the side wall of the boss, and as the P-type GaN is contacted with the N-type GaN (the N+ GaN layer and the N-GaN layer), a depletion region is formed, as shown in figure 7. In the depletion region, the charge is in an equilibrium state, so that a leakage channel is not formed in the side wall region of the GaN Schottky diode provided by the invention. Meanwhile, the P-type GaN layer is arranged on the upper surface of the N-GaN layer part and the upper surface of the plane layer part, and meanwhile, the P-type GaN layer is not contacted with the Schottky electrode and the ohmic electrode, so that the potential of the P-GaN layer can be well maintained (namely, the potential of the P-GaN layer is not changed when the GaN SBD is positively biased or negatively biased), and the width of a depletion region is kept not reduced. In summary, through structural improvement, the low-leakage GaN Schottky diode provided by the invention has the advantages that the depletion effect of the P-type GaN layer on the N-type GaN is realized, a depletion region is formed in the side wall region, and no electrons flow in the depletion region, so that the leakage channel of the side wall of the device is prevented, and the reverse leakage current of the device is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a low leakage GaN schottky diode provided by the present invention;
FIG. 2 is a schematic diagram showing the structure of an initial N+ GaN layer and an initial N-GaN layer prepared on the surface of a substrate according to example 1 of the present invention;
FIG. 3 is a schematic diagram of the structure of an N+ GaN layer and an N-GaN layer etched according to the embodiment of the invention;
FIG. 4 is a schematic diagram of a structure of a hard mask plate according to embodiment 1 of the present invention;
Fig. 5 is a schematic structural diagram of ion implantation according to embodiment 1 of the present invention;
FIG. 6 is a schematic diagram of the structure of a P-type GaN layer obtained after annealing treatment in embodiment 1 of the invention;
FIG. 7 is a schematic diagram showing the structure of a depletion region formed by contacting a P-type GaN layer with N-type GaN (N+ GaN layer and N-GaN layer) after annealing treatment in example 1 of the present invention;
in the figure: 1 is a substrate, 2 is an N+ GaN layer, 3 is an N-GaN layer, 4 is an ohmic electrode, 5 is a Schottky electrode, 6 is a P-type GaN layer, 7 is an initial N+ GaN layer, 8 is an initial N-GaN layer, 9 is a hard mask plate, and 10 is a depletion region.
Detailed Description
The invention provides a low-leakage GaN Schottky diode, which comprises the following components: a substrate; the N+ GaN layer is arranged on the upper surface of the substrate and consists of a plane layer and a boss integrally arranged on the plane layer; the N-GaN layer is covered on the upper surface of the boss; the P-type GaN layer is arranged on the upper surface of the N-GaN layer part, the side wall of the N-GaN layer, the side wall of the boss and the upper surface of the plane layer part; the Schottky electrode is arranged on the residual upper surface of the N-GaN layer; an ohmic electrode disposed on the remaining upper surface of the planar layer; and the P-type GaN layer is not contacted with the Schottky electrode and the ohmic electrode.
In the present invention, all preparation materials/components are commercially available products well known to those skilled in the art unless specified otherwise.
The low-leakage GaN Schottky diode provided by the invention comprises a substrate. In the present invention, the substrate is preferably a sapphire substrate.
The low-leakage GaN Schottky diode comprises an N+ GaN layer arranged on the upper surface of a substrate, wherein the N+ GaN layer is composed of a plane layer and a boss integrally arranged on the plane layer. In the present invention, the doping concentration of the n+ GaN layer is preferably > 1×10 19cm-3. The boss is preferably located near the center of the n+ GaN layer. The thickness of the boss is preferably less than or equal to the thickness of the planar layer. The thickness of the planar layer is preferably 2 to 3 μm and is not equal to 3 μm, more preferably 2 to 2.8 μm. The thickness of the boss is preferably less than or equal to 1 mu m, and more preferably 200 nm-1 mu m. The total thickness of the planar layer and the lands is preferably 3 μm.
The low-leakage GaN Schottky diode provided by the invention comprises an N-GaN layer covered on the upper surface of the boss. In the present invention, the doping concentration of the N-GaN layer is preferably < 1×10 19cm-3; the thickness of the N-GaN layer is preferably 5 μm.
The low-leakage GaN Schottky diode provided by the invention comprises a P-type GaN layer arranged on the upper surface of the N-GaN layer part, the side wall of the N-GaN layer, the side wall of the boss and the upper surface of the plane layer part. In the present invention, the P-type GaN layer is continuous. The material of the P-type GaN layer is preferably Mg-doped GaN, and the doping concentration of Mg element in the Mg-doped GaN is preferably more than 1 multiplied by 10 18cm-3.
The low-leakage GaN Schottky diode provided by the invention comprises a Schottky electrode arranged on the residual upper surface of the N-GaN layer. In the present invention, the schottky electrode preferably includes a contact layer and a metal layer disposed on an upper surface of the contact layer; the contact layer of the Schottky electrode is preferably made of Ni, and the thickness is preferably 100nm; the material of the metal layer of the schottky electrode is preferably Au, and the thickness is preferably 1000nm.
The low-leakage GaN Schottky diode provided by the invention comprises an ohmic electrode arranged on the residual upper surface of the planar layer. In the present invention, the ohmic electrode preferably includes a contact layer and a metal layer disposed on an upper surface of the contact layer; the contact layer of the ohmic electrode is preferably made of Ni, and the thickness is preferably 20nm; the material of the metal layer of the ohmic electrode is preferably Al, and the thickness is preferably 1000nm.
In the low-leakage GaN Schottky diode provided by the invention, the P-type GaN layer is not contacted with the Schottky electrode and the ohmic electrode. In the present invention, the gap between the P-type GaN layer and the Schottky electrode is preferably not less than 5. Mu.m. The gap between the P-type GaN layer and the ohmic electrode is preferably more than or equal to 5 mu m.
The invention provides a preparation method of the low-leakage GaN Schottky diode, which comprises the following steps:
Sequentially epitaxially growing an initial N+ GaN layer and an initial N-GaN layer on the upper surface of the substrate; etching the initial N+ GaN layer and the initial N-GaN layer according to the shapes and structures of the N+ GaN layer and the N-GaN layer to obtain the N+ GaN layer and the N-GaN layer; preparing a hard mask plate on the upper surface of the N-GaN layer part and the upper surface of the plane layer part, and then carrying out ion implantation on the remaining upper surface of the N-GaN layer, the side wall of the boss and the remaining upper surface of the plane layer to obtain a first semi-finished product;
Annealing the first semi-finished product in a protective gas atmosphere to obtain a P-type GaN layer, and obtaining a second semi-finished product;
And removing the hard mask plate from the second semi-finished product, and then preparing a Schottky electrode and an ohmic electrode to obtain the low-leakage GaN Schottky diode.
The invention sequentially epitaxially grows an initial N+ GaN layer and an initial N-GaN layer on the upper surface of the substrate; etching the initial N+ GaN layer and the initial N-GaN layer according to the shapes and structures of the N+ GaN layer and the N-GaN layer to obtain the N+ GaN layer and the N-GaN layer; preparing a hard mask plate on the upper surface of the N-GaN layer part and the upper surface of the plane layer part, and then carrying out ion implantation on the remaining upper surface of the N-GaN layer, the side wall of the boss and the remaining upper surface of the plane layer to obtain a first semi-finished product. In the present invention, the epitaxial growth is preferably performed in an MOCVD apparatus, and the present invention is not particularly limited to the specific embodiment of the epitaxial growth. In the present invention, the thickness of the initial n+ GaN layer is preferably 3 μm. The thickness of the initial N-GaN layer is preferably 5 μm. The initial N-GaN layer and the initial N+ GaN layer are etched in sequence, and when the initial N-GaN layer is etched, the initial N+ GaN layer below is exposed; and then continuing to etch the initial N+ GaN. The method has no special requirements on the initial N+ GaN layer and the etching method of the initial N-GaN layer. The hard mask plate is preferably SiO 2. The ion implantation is preferably Mg ion implantation. The energy of the Mg ion implantation is preferably 360Kev. The present invention is not particularly limited to the specific embodiment of the ion implantation.
After the first semi-finished product is obtained, the first semi-finished product is annealed in a protective gas atmosphere to obtain a P-type GaN layer, and a second semi-finished product is obtained. In the invention, the temperature of the annealing treatment is preferably 1250 ℃, the time is preferably 30min, and the pressure is preferably normal pressure; the shielding gas is preferably nitrogen. In the invention, the annealing effect of the annealing treatment is as follows: one is to repair the material damage caused during the implantation process, and the other is because Mg activation energy in GaN is large, and high temperature annealing is required to activate Mg to form P-type GaN.
After a second semi-finished product is obtained, the second semi-finished product is removed from the hard mask plate, and then a Schottky electrode and an ohmic electrode are prepared, so that the low-leakage GaN Schottky diode is obtained. The invention has no special requirements on the preparation methods of the Schottky electrode and the ohmic electrode.
The technical solutions provided by the present invention are described in detail below in conjunction with examples for further illustrating the present invention, but they should not be construed as limiting the scope of the present invention.
Example 1
Step 1: the substrate 1 is placed in an MOCVD apparatus in which the substrate 1 is sapphire, and an initial n+ GaN layer 7 and an initial N-GaN layer 8 are epitaxially grown in sequence (as shown in fig. 2). Wherein the initial N-GaN layer 8 is a lightly doped N-type GaN layer with a thickness of 5 μm and a doping concentration of less than 1×10 18/cm3, and the initial N+ GaN layer 7 is a heavily doped N-type GaN layer with a thickness of 3 μm and a doping concentration of more than 1×10 19/ cm3.
Step 2: etching the initial N-GaN layer 8 until the lower initial N+ GaN layer 7 is exposed, so as to obtain an N-GaN layer 3; and continuing to etch the initial N+ GaN layer 7, and etching the initial N+ GaN layer 7 downwards by 1 mu m with the N-GaN layer 3 as a template to obtain a boss structure with the thickness of 1 mu m, thereby obtaining the N+ GaN layer 2 (shown in figure 3). In the etching process, the obtained N-GaN layer 3 and the sidewall of the boss structure having a thickness of 1 μm may be damaged by etching, thereby generating conductive ions on the sidewall, and some contaminants or conductive ions may be attached to the sidewall in the wafer process. Due to the presence of these conductive ions, a reverse leakage current is formed when a reverse voltage of the device (high voltage is applied to the ohmic electrode) is applied.
Step 3: siO 2 is prepared on the upper surface of the N-GaN layer 3 and the upper surface of the plane layer part to be used as a hard mask plate 9, and then ion implantation is performed on the remaining upper surface of the N-GaN layer 3, the side wall of the boss and the remaining upper surface of the plane layer (the ion implantation energy is 360Kev, and the total concentration of Mg ions is more than 1 multiplied by 10 18/cm3), as shown in FIG. 5. Then annealing for 30min under the normal pressure and 1250 ℃ and nitrogen atmosphere. The annealing purposes are two, one is to repair the material damage caused during the implantation process, and the other is because the activation energy of Mg in GaN is large, and high-temperature annealing is required to activate Mg to form P-type GaN.
Step 4: after the annealing is completed, the SiO 2 hard mask 9 is removed to form the structure shown in FIG. 6. In fig. 6, the implanted region forms P-type GaN. Since P-type GaN contacts N-type GaN, a depletion region is formed as shown in fig. 7. In the depletion region, the charge is in an equilibrium state, and therefore, the sidewall region does not form a leakage channel.
Step 5: finally, the schottky electrode (Ni/Au 100nm/1000 nm) and the ohmic electrode (Ti/Al 20nm/1000 nm) are respectively fabricated, and during the fabrication process, the schottky electrode and the ohmic electrode are not connected to the injection region, and a certain distance (> 5 μm) is maintained, so that the purpose of this is to maintain the potential of the P-GaN layer (i.e., the potential of the P-GaN layer does not change when the GaN SBD is biased positively or negatively), and keep the width of the depletion region from shrinking.
From the above examples, it can be seen that: the invention provides a preparation method of a low-leakage GaN Schottky diode, which comprises the following steps: first, an initial n+ GaN layer and an initial N-GaN layer are sequentially grown on a sapphire substrate. The initial n+ GaN layer and the initial N-GaN layer are then etched. And then carrying out Mg ion implantation on the side wall and part of the surface of the N-GaN, the side wall of the boss of the N+ GaN and part of the surface of the planar layer, and carrying out high-temperature annealing after the implantation is finished to form a depletion region. Finally, the schottky electrode and the ohmic electrode are manufactured, and are not connected with the injection region and keep a certain distance. According to the low-leakage GaN Schottky diode provided by the invention, mg ion implantation is performed on the upper surface of the N-GaN layer part, the side wall of the N-GaN layer, the side wall of the boss and the upper surface area of the plane layer part, then the implanted layer is changed into P-GaN through high-temperature annealing, the depletion region is formed in the side wall area by utilizing the depletion effect of P-type GaN on N-type GaN, and no electrons flow in the depletion region, so that a leakage channel of the side wall is prevented, and the reverse leakage current is reduced.
Although the foregoing embodiments have been described in some, but not all embodiments of the invention, other embodiments may be obtained according to the present embodiments without departing from the scope of the invention.

Claims (8)

1. A low leakage GaN schottky diode comprising: a substrate; the N+ GaN layer is arranged on the upper surface of the substrate and consists of a plane layer and a boss integrally arranged on the plane layer; the N-GaN layer is covered on the upper surface of the boss; the P-type GaN layer is arranged on the upper surface of the N-GaN layer part, the side wall of the N-GaN layer, the side wall of the boss and the upper surface of the plane layer part; the Schottky electrode is arranged on the residual upper surface of the N-GaN layer; an ohmic electrode disposed on the remaining upper surface of the planar layer; the P-type GaN layer is not contacted with the Schottky electrode and the ohmic electrode; the gap between the P-type GaN layer and the Schottky electrode is more than or equal to 5 mu m; the gap between the P-type GaN layer and the ohmic electrode is more than or equal to 5 mu m; the material of the P-type GaN layer is Mg-doped GaN, and the doping concentration of Mg element in the Mg-doped GaN is more than 1 multiplied by 10 18cm-3;
The preparation method of the low-leakage GaN Schottky diode comprises the following steps:
Sequentially epitaxially growing an initial N+ GaN layer and an initial N-GaN layer on the upper surface of the substrate; etching the initial N+ GaN layer and the initial N-GaN layer according to the shapes and structures of the N+ GaN layer and the N-GaN layer to obtain the N+ GaN layer and the N-GaN layer; preparing a hard mask plate on the upper surface of the N-GaN layer part and the upper surface of the plane layer part, and then carrying out ion implantation on the remaining upper surface of the N-GaN layer, the side wall of the boss and the remaining upper surface of the plane layer to obtain a first semi-finished product;
Annealing the first semi-finished product in a protective gas atmosphere to obtain a P-type GaN layer, and obtaining a second semi-finished product;
And removing the hard mask plate from the second semi-finished product, and then preparing a Schottky electrode and an ohmic electrode to obtain the low-leakage GaN Schottky diode.
2. The low leakage GaN schottky diode of claim 1 wherein the n+ GaN layer has a doping concentration > 1 x 10 19cm-3; the thickness of the plane layer is 2-3 mu m and is not equal to 3 mu m; the thickness of the boss is less than or equal to 1 mu m.
3. The low leakage GaN schottky diode of claim 1 wherein the N-GaN layer has a doping concentration < 1 x 10 19cm-3; the thickness of the N-GaN layer was 5. Mu.m.
4. The low leakage GaN schottky diode of claim 1 wherein the schottky electrode comprises a contact layer and a metal layer disposed on an upper surface of the contact layer; the contact layer of the Schottky electrode is made of Ni, and the thickness of the contact layer is 100nm; the metal layer of the Schottky electrode is made of Au, and the thickness of the metal layer is 1000nm.
5. The low leakage GaN schottky diode of claim 1 wherein the ohmic electrode comprises a contact layer and a metal layer disposed on an upper surface of the contact layer; the contact layer of the ohmic electrode is made of Ni, and the thickness of the contact layer is 20nm; the metal layer of the ohmic electrode is made of Al, and the thickness of the metal layer is 1000nm.
6. The low leakage GaN schottky diode of claim 1 wherein the substrate is a sapphire substrate.
7. The method for manufacturing the low-leakage GaN schottky diode according to any one of claims 1 to 6, comprising the steps of:
Sequentially epitaxially growing an initial N+ GaN layer and an initial N-GaN layer on the upper surface of the substrate; etching the initial N+ GaN layer and the initial N-GaN layer according to the shapes and structures of the N+ GaN layer and the N-GaN layer to obtain the N+ GaN layer and the N-GaN layer; preparing a hard mask plate on the upper surface of the N-GaN layer part and the upper surface of the plane layer part, and then carrying out ion implantation on the remaining upper surface of the N-GaN layer, the side wall of the boss and the remaining upper surface of the plane layer to obtain a first semi-finished product;
Annealing the first semi-finished product in a protective gas atmosphere to obtain a P-type GaN layer, and obtaining a second semi-finished product;
And removing the hard mask plate from the second semi-finished product, and then preparing a Schottky electrode and an ohmic electrode to obtain the low-leakage GaN Schottky diode.
8. The method according to claim 7, wherein the annealing treatment is performed at 1250 ℃ for 30min under normal pressure; the shielding gas is nitrogen.
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* Cited by examiner, † Cited by third party
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CN110190115A (en) * 2019-06-10 2019-08-30 广东省半导体产业技术研究院 A kind of SBD structure and preparation method thereof

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