CN118248640A

CN118248640A - Semiconductor package

Info

Publication number: CN118248640A
Application number: CN202311682035.3A
Authority: CN
Inventors: 姜政勋; 姜芸炳; 金镇洙; 申承完; 张炳旭
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-12-22
Filing date: 2023-12-08
Publication date: 2024-06-25

Abstract

A semiconductor package includes: a lower redistribution layer having a first region and a second region adjacent to the first region and including a first redistribution wire; a semiconductor chip on the first region of the lower redistribution layer and electrically connected to the first redistribution wire; a sealing member located on the lower redistribution wiring layer on a side surface of the semiconductor chip; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wiring; a mark pattern on the semiconductor chip; seed layer pads on respective ends of the vertical conductive structures, the ends being exposed by the sealing member at an upper surface of the sealing member; and an upper redistribution layer on the sealing member and the marking pattern and including a second redistribution layer.

Description

Semiconductor package

Technical Field

Example embodiments relate to a semiconductor package. More particularly, example embodiments relate to a fan-out package.

Background

In manufacturing the fan-out package, a sealing member may be formed on the lower redistribution wiring layer to cover the semiconductor chip, copper pillars may be formed to penetrate the sealing member, and a back redistribution wiring layer may be formed on the sealing member. Then, a marking pattern may be formed by performing a laser marking process on the outermost insulating layer of the backside redistribution routing layer. However, since the laser marking process may use laser light having a wavelength in a green wavelength range (for example, 532 nm), and since the reflectivity of the insulating layer material in the green laser wavelength range may be high, laser ablation may be difficult, thereby making it difficult to ensure marking visibility.

Disclosure of Invention

Example embodiments provide a semiconductor package that improves the visibility of a marking pattern and may improve the efficiency of a manufacturing process.

Example embodiments provide a method of manufacturing a semiconductor package.

According to an example embodiment, a semiconductor package includes: a lower redistribution routing layer having a first region and a second region adjacent to the first region, the lower redistribution routing layer including a first redistribution routing; a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wiring; a sealing member on a side surface of the semiconductor chip on the lower redistribution wiring layer; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution routing layer and electrically connected to the first redistribution routing; a mark pattern on the semiconductor chip; a seed layer pad on respective ends of the vertical conductive structure, the ends being exposed by the sealing member at an upper surface of the sealing member; and an upper redistribution routing layer on the sealing member and the marking pattern, the upper redistribution routing layer including a second redistribution routing electrically connected to the plurality of vertical conductive structures.

According to an example embodiment, a semiconductor package includes: a lower redistribution routing layer including a first redistribution routing; a semiconductor chip on the lower redistribution routing layer, wherein a first surface of the semiconductor chip including a chip pad faces the lower redistribution routing layer; a sealing member on the semiconductor chip and on the lower redistribution wiring layer, wherein the sealing member exposes a second surface of the semiconductor chip opposite the first surface; a plurality of vertical conductive structures penetrating the sealing member and electrically connected to the first redistribution routing; a marking pattern on the second surface of the semiconductor chip; and an upper redistribution routing layer on the sealing member and the marking pattern, the upper redistribution routing layer including a second redistribution routing electrically connected to the plurality of vertical conductive structures. An upper surface of the marking pattern is coplanar with an upper surface of the sealing member.

According to an example embodiment, a semiconductor package includes: a lower redistribution routing layer having a first region and a second region adjacent to the first region, the lower redistribution routing layer including a first redistribution routing; a semiconductor chip on the first region of the lower redistribution routing layer, wherein a first surface of the semiconductor chip including a chip pad faces the lower redistribution routing layer; a sealing member on the semiconductor chip and on the lower redistribution wiring layer, wherein the sealing member exposes a second surface of the semiconductor chip opposite the first surface; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution routing layer and electrically connected to the first redistribution routing; a marking pattern on the second surface of the semiconductor chip; seed layer pads at respective ends of the vertical conductive structures, the ends being exposed by the sealing member at an upper surface of the sealing member; and an upper redistribution routing layer on the sealing member and the marking pattern, the upper redistribution routing layer including a second redistribution routing on the seed layer pad. The sealing member is on a side surface of the marking pattern and on a side surface of the seed layer pad.

According to an example embodiment, in a method of manufacturing a semiconductor package, an insulating layer and a seed layer are sequentially formed on a carrier substrate having a first region and a second region adjacent to the first region. A plurality of vertical conductive structures are formed on the seed layer in the second region. A first laser is irradiated onto the seed layer over the second region to remove portions of the seed layer between the vertical conductive structures to form seed layer pads under the vertical conductive structures. A second laser is irradiated onto the seed layer on the first region to form a marking pattern. A semiconductor chip is disposed on the marking pattern of the first region such that a second surface of the semiconductor chip opposite to a first surface thereof including a chip pad faces the insulating layer. A sealing member is formed on the insulating layer, on the semiconductor chip, and on the vertical conductive structure. A lower redistribution layer is formed on the first surface of the sealing member, the lower redistribution layer having a first redistribution wire electrically connected to the die pad and the vertical conductive structure. An upper redistribution wiring layer having a second redistribution wiring electrically connected to the vertical conductive structure is formed on the second surface of the sealing member and on the marker pattern.

According to example embodiments, a semiconductor package as a fan-out type wafer level package may include a lower redistribution routing layer, a semiconductor chip on the lower redistribution routing layer, a sealing member on at least a portion of the semiconductor chip and an upper surface of the lower redistribution layer, a plurality of vertical conductive structures penetrating the sealing member, a marking pattern on the semiconductor chip, and an upper redistribution routing layer on an upper surface of the sealing member.

The marking pattern may be on a back surface of the semiconductor chip in the first region of the lower redistribution routing layer. The marking pattern may include a seed layer dummy pattern and a intaglio pattern defined by a via hole formed by irradiating laser on the seed layer dummy pad. Even though the upper redistribution routing layer may completely cover the marking pattern, the marking pattern may be identified by the upper redistribution routing layer.

Instead of the existing marking process of engraving the upper insulating layer of PID material, the marking pattern may be formed by laser machining a portion of the seed layer used to form the vertical conductive structure. Accordingly, the visibility of the marking pattern may be improved, and the efficiency of the marking process may be improved.

Drawings

Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Fig. 1-26 illustrate a non-limiting example embodiment as described herein.

Fig. 1 is a cross-sectional view illustrating a semiconductor package according to an example embodiment.

Fig. 2 is a plan view illustrating a vertical conductive structure and a marking pattern in the sealing member of fig. 1.

Fig. 3 is an enlarged sectional view showing a portion "a" in fig. 1.

Fig. 4, 5,6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, and 19 are diagrams illustrating a method of manufacturing a semiconductor package according to example embodiments.

Fig. 20 is a cross-sectional view illustrating a semiconductor package according to an example embodiment.

Fig. 21 is a cross-sectional view illustrating a semiconductor package according to an example embodiment.

Fig. 22, 23, 24, 25, and 26 are sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.

Detailed Description

Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings. The terms "first," "second," and the like are used herein to distinguish one element, layer, direction, etc., from another element, layer, direction, etc.

Fig. 1 is a cross-sectional view illustrating a semiconductor package according to an example embodiment. Fig. 2 is a plan view illustrating a vertical conductive structure and a marking pattern in the sealing member of fig. 1. Fig. 3 is an enlarged sectional view showing a portion "a" in fig. 1. Fig. 1 is a sectional view taken along line I-I' in fig. 2.

Referring to fig. 1 to 3, the semiconductor package 10 may include a lower redistribution routing layer 100, a semiconductor chip 200 disposed on the lower redistribution routing layer 100, a sealing member 300 covering at least a portion of the semiconductor chip 200 on an upper surface of the lower redistribution routing layer 100, a plurality of vertical conductive structures 400 penetrating the sealing member 300, a marking pattern 420 disposed on the semiconductor chip 200, and an upper redistribution routing layer 510 disposed on an upper surface 302 of the sealing member 300. In addition, the semiconductor package 10 may further include an external connection member 550 disposed on an outer surface of the lower redistribution layer 100.

In an example embodiment, the semiconductor package 10 may be a fan-out type package in which the lower redistribution routing layer 100 extends to the sealing member 300 covering the side surface of the semiconductor chip 200. The lower redistribution layer 100 may be formed by a wafer level redistribution routing process. Further, the semiconductor package 10 may be provided as a unit package on which the second package is stacked.

Further, the semiconductor package 10 may be provided as a System In Package (SIP). For example, one or more semiconductor chips may be disposed on the lower redistribution routing layer 100. The semiconductor chip may include a logic chip including a logic circuit and/or a memory chip. The logic chip may be a controller that controls the memory chip. The memory chip may include various types of memory circuits such as DRAM, SRAM, flash, PRAM, reRAM, feRAM, or MRAM.

In an example embodiment, the lower redistribution layer 100 may have a first redistribution wire 102. The semiconductor chip 200 may be disposed on the lower redistribution layer 100 to be electrically connected to the first redistribution wire 102. The lower redistribution layer 100 may be disposed on the front side 202 of the semiconductor chip 200 as a front side redistribution layer. Accordingly, the lower redistribution routing layer 100 may be a front redistribution routing layer (FRDL) of the fan-out package.

Specifically, the lower redistribution layer 100 may include a plurality of first, second, third, and fourth lower insulating layers 110, 120, 130, and 140, and first redistribution wirings 102 disposed in the first, second, third, and fourth lower insulating layers. The first redistribution line 102 may include a first lower redistribution line 112, a second lower redistribution line 122, and a third lower redistribution line 132.

The first, second, third and fourth lower insulating layers may comprise a polymer or dielectric layer. For example, the first, second, third, and fourth lower insulating layers may include a photosensitive insulating layer, such as a photoimageable dielectric (PID). The first lower insulating layer, the second lower insulating layer, the third lower insulating layer, and the fourth lower insulating layer may be formed by a vapor deposition process, a spin coating process, or the like. The first redistribution wire may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof. The first redistribution may be formed by an electroplating process, an electroless plating process, a vapor deposition process, or the like.

Specifically, the first lower insulating layer 110 may be formed on the lower surface 304 of the sealing member 300, and the first lower redistribution wire 112 may be formed on the first lower insulating layer 110. The first lower redistribution line 112 may be electrically connected to the conductive bump 220 and the vertical conductive structure 400 through a first opening formed in the first lower insulating layer 110.

The second lower insulating layer 120 may be formed on the first lower insulating layer 110, and the second lower redistribution wire 122 may be formed on the second lower insulating layer 120. The second lower redistribution wire 122 may be electrically connected to the first lower redistribution wire 112 through a second opening formed in the second lower insulating layer 120.

A third lower insulating layer 130 may be formed on the second lower insulating layer 120, and a third lower redistribution wire 132 may be formed on the third lower insulating layer 130. The third lower redistribution wire 132 may be electrically connected to the second lower redistribution wire 122 through a third opening formed in the third lower insulating layer 130.

Package pads (not shown) may be formed on the third lower redistribution lines 132. A fourth lower insulating layer 140 may be formed on the third lower insulating layer 130 to expose at least a portion of the package pad on the third lower redistribution line 132. The fourth lower insulating layer 140 may serve as a passivation layer.

The number and arrangement of the lower insulation layer and the lower redistribution wirings of the lower redistribution wiring layer are provided as examples, and it will be appreciated that the inventive concept is not limited thereto.

In an example embodiment, the lower redistribution wiring layer 100 may include a first region R1 overlapping the semiconductor chip 200 mounted on the upper surface of the lower redistribution wiring layer 100 and a second region R2 adjacent to the first region R1 or surrounding the first region R1 when viewed from a plan view. Components or layers described as "overlapping" may be at least partially hindered from one another when viewed along a straight line extending in a particular direction or in a plane perpendicular to the particular direction. The second region R2 may be a fan-out region outside (e.g., extending around the periphery of) a region where the semiconductor chip 200 is disposed.

In an example embodiment, the semiconductor chip 200 may have a plurality of chip pads 210 on the first surface 202 (i.e., active surface). The semiconductor chip 200 may be mounted on the lower redistribution layer 100 such that the first surface forming the chip pad 210 faces down the redistribution layer 100.

The semiconductor chip 200 may be mounted on the lower redistribution layer 100 via conductive bumps 220. The conductive bump 220 may be disposed between the first lower redistribution wire 112 of the lower redistribution wire layer 100 and the chip pad 210 of the semiconductor chip 200 to electrically connect them.

For example, each of the conductive bumps 220 may include a pillar bump formed on the chip pad 210 of the semiconductor chip 200 and a solder bump formed on the pillar bump. Alternatively, each of the conductive bumps 220 may include a solder bump formed on the chip pad 210 of the semiconductor chip 200.

Although only a few chip pads are shown in the drawings, the structure and arrangement of the chip pads are provided as examples, and it will be understood that the inventive concept is not limited thereto. Further, although only one semiconductor chip is shown, it is not limited thereto, and a plurality of semiconductor chips may be stacked on the lower redistribution wiring layer.

In an example embodiment, the sealing member 300 may be disposed on the upper surface of the lower redistribution layer 100 to extend over at least a portion of the semiconductor chip 200 or cover at least a portion of the semiconductor chip 200. The sealing member 300 may include a first molding portion extending over the first surface 202 of the semiconductor chip 200 or covering the first surface 202 of the semiconductor chip 200, and a second sealing portion extending over the upper surface of the lower redistribution wiring layer 100 around the semiconductor chip 200 or covering the upper surface of the lower redistribution wiring layer 100. The sealing member 300 may expose the second surface 204 opposite to the first surface 202 of the semiconductor chip 200. The term "exposing" is used in this specification to describe an intermediate process of fabricating a completed semiconductor device and is not intended to necessarily require exposing specific areas, layers, structures or other elements in the actual completed device. The second surface 204, i.e., the back surface, of the semiconductor chip 200 may be exposed by the upper surface 302 of the sealing member 300.

For example, the sealing member 300 may include an Epoxy Molding Compound (EMC). The sealing member 300 may be formed through a molding process, a screen printing process, a lamination process, or the like.

In an example embodiment, the plurality of vertical conductive structures 400 may extend in a vertical direction (with reference to a cross-sectional view) to penetrate the sealing member 300. The vertical conductive structure 400 may extend in a vertical direction from the first surface 302 to the second surface 304 of the sealing member 300. One end of the vertical conductive structure 400 may be exposed by the sealing member 300 at the second surface 304 of the sealing member 300. The vertical conductive structure 400 may be electrically connected to the first redistribution line 122 located in the second region R2. For example, the vertical conductive structure 400 may include a metal material such as copper (Cu).

The vertical conductive structure 400 may penetrate the sealing member 300 and serve as an electrical connection path. The vertical conductive structure 400 may be used as a Through Mold Via (TMV) formed through the second sealing portion of the sealing member 300. That is, the vertical conductive structure 400 may be disposed in the fan-out region R2 outside the region in which the semiconductor chip 200 is disposed to electrically connect the lower and upper redistribution wiring layers 100 and 510.

In an example embodiment, the marking pattern 420 may be disposed on the back surface 204 of the semiconductor chip 200 in the first region R1. The marking pattern 420 may be exposed by the sealing member 300 at the upper surface 302 of the sealing member 300. The upper surface of the marking pattern 420 may be located on the same plane (i.e., coplanar) with the first surface 302 of the sealing member 300. The sealing member 300 may extend on or cover a side surface of the marking pattern 420.

Further, the seed layer pad 410 may be bonded to an end of the vertical conductive structure 400 exposed from the first surface 302 of the sealing member 300 in the second region R2. The upper surface of the seed layer pad 410 may be on the same plane as the first surface 302 of the sealing member 300 or below (e.g., recessed relative to) the first surface 302 of the sealing member 300. Seed layer pads 410 may be disposed on the ends of the vertical conductive structures 400, respectively. The seed layer pad 410 may have a diameter that is the same as the diameter of the vertical conductive structure 400 or smaller than the diameter of the vertical conductive structure 400 (e.g., when viewed in plan view). The sealing member 300 may extend on or cover a side surface of the seed layer pad 410.

The seed layer pad 410 and the marking pattern 420 may have the same or different metal layer structures. For example, the seed layer pad 410 and the marking pattern 420 may include a first seed layer and a second seed layer stacked on the first seed layer. Alternatively, the seed layer pad 410 may include a first seed layer, and the marking pattern 420 may include a first seed layer and a second seed layer stacked on the first seed layer. The first seed layer may include copper (Cu), and the second seed layer may include titanium (Ti). The seed layer pad 410 and the marking pattern 420 may have a thickness in a range of about 0.1 μm to about 0.5 μm. The first seed layer may have a thickness of 200nm and the second seed layer may have a thickness of 80 nm.

As shown in fig. 2, the marking pattern 420 may be disposed on the back surface 204 of the semiconductor chip 200 in the first region R1, and the vertical conductive structure 400 may be disposed in the sealing member 300 in the second region R2.

The marking pattern 420 may include a seed layer "dummy" (or nonfunctional) pattern 423 disposed in the first region R1 and a intaglio pattern 422 defined by a plurality of openings formed in the seed layer dummy pattern 423, for example, by irradiating laser light or irradiating laser light on the seed layer dummy pattern 423. Intaglio patterns 422 may represent information about the manufacturer, date of manufacture, serial number, etc.

The marking pattern 420 may be attached to the back surface 204 of the semiconductor chip 200 through the adhesive film 230. For example, the adhesive film 230 may include a wafer adhesive film (DAF). The thickness of the adhesive film 230 may be in the range of about 30 μm to about 120 μm. The semiconductor chip 200 attached with the adhesive film 230 may be attached on the marking pattern 420 through a hot pressing process. A portion of the DAF having fluidity due to the pressure and temperature of the hot pressing process may at least partially fill the intaglio pattern 422 of the mark pattern 420, i.e., the opening of the seed layer dummy pattern 423.

In an example embodiment, the upper redistribution layer 510 may be disposed on the first surface 302 of the sealing member 300, and may include second redistribution wirings 502 electrically connected to the vertical conductive structures 400, respectively. The upper redistribution layer 510 may entirely cover the mark pattern 420. The second redistribution wirings 502 may be disposed on the seed layer pads 410 bonded to the ends of the vertical conductive structures 400, respectively. The second redistribution wiring 502 may be provided on the sealing member 300 to serve as a back-side redistribution wiring. Accordingly, the upper redistribution routing layer 510 may be a backside redistribution routing layer (BRDL) of the fan-out package.

For example, the second redistribution wire 502 may include a first plating pattern 504 and a second plating pattern 506 sequentially formed on the seed layer pad 410. In this case, the first plating pattern 504 may include nickel (Ni), and the second plating pattern 506 may include gold (Au). Here, the seed layer pad 410 may include a copper (Cu) seed layer, and the first plating pattern 504 may be formed on the copper (Cu) seed layer.

Alternatively, the second redistribution line 502 may include a single plating pattern on the seed layer pad 410. In this case, the plating pattern may include gold (Au). Here, the seed layer pad 410 may include a titanium (Ti) seed layer and a copper (Cu) seed layer, and a gold (Au) plating pattern may be formed on the copper (Cu) seed layer.

The upper redistribution layer 510 may be disposed on the upper surface 302 of the sealing member 300 and may have an opening exposing the seed layer pad 410 on the vertical conductive structure 400. The second redistribution wirings 502 may be formed on the seed layer pads 410, respectively.

For example, the upper redistribution routing layer may include a polymer or dielectric layer. The upper redistribution routing layer may include a photosensitive insulating material (PID) or an insulating layer such as ABF. The upper redistribution layer may have a thickness of about 20 μm or less. The second redistribution wire may include copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

The upper redistribution layer 510 may have the second redistribution wirings 502 stacked in one layer on the first surface 302 of the sealing member 300. The second redistribution wiring 502 may correspond to an uppermost redistribution wiring, and may function as a bonding pad on which a solder bump for electrical connection with the second package is provided.

Alternatively, the upper redistribution layer may include a first upper redistribution wire and a second upper redistribution wire stacked in at least two layers. In this case, the upper redistribution wiring layer may include a plurality of stacked upper insulating layers, the first upper redistribution wiring may correspond to the second redistribution wiring 502, and the second upper redistribution wiring may serve as a bonding pad on which a solder bump for electrical connection with the second package is disposed.

The number and arrangement of the upper redistribution wiring layer and the second redistribution wiring are provided as examples, and it will be appreciated that the inventive concept is not limited thereto.

In an example embodiment, the external connection member 550 may be disposed on the outer surface of the lower redistribution routing layer 100 or on a package pad on the outer surface. For example, the external connection member 550 may include a solder ball. The solder balls may have a diameter of about 300 μm to about 500 μm. The semiconductor package 10 may be mounted on a module substrate (not shown) via solder balls to form a memory module.

As described above, the semiconductor package 10, which is a fan-out type wafer level package, may include the lower redistribution routing layer 100, the semiconductor chip 200 disposed on the lower redistribution routing layer 100, the sealing member 300 on the upper surface of the lower redistribution routing layer 100 and covering at least a portion of the semiconductor chip 200, the plurality of vertical conductive structures 400 penetrating the sealing member 300, the marking pattern 420 disposed on the semiconductor chip 200, and the upper redistribution routing layer 510 disposed on the upper surface 302 of the sealing member 300.

The marking pattern 420 may be disposed on the back surface 204 of the semiconductor chip 200 in the first region R1 of the lower redistribution layer 100. The marking pattern 420 may include, for example, a gravure pattern 422 formed by irradiating laser light onto or onto a portion of the seed layer pad disposed in the first region R1. The laser may form an opening penetrating the seed layer dummy pattern 423, and the intaglio pattern 422 may be defined by the opening. Even though the upper redistribution layer 510 may completely cover the marker pattern 420, the marker pattern 420 may still be identified by the upper redistribution layer 510. For example, the upper redistribution routing layer 510 may include at least partially transparent portions such that the marker pattern 420 may be visible through portions of the upper redistribution routing layer 510 thereon.

The marking pattern 420 is formed by laser-applying a portion of the seed layer for forming the vertical conductive structure 400, an existing marking process of forming the upper insulating layer of the PID material may be omitted, and the visibility of the marking pattern may be improved.

Hereinafter, a method of manufacturing the semiconductor package of fig. 1 will be described.

Fig. 4 to 19 are diagrams illustrating a method of manufacturing a semiconductor package according to an example embodiment. Fig. 4 to 10, 12 to 16, 18 and 19 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an example embodiment. Fig. 11 is a plan view of fig. 10. Fig. 17 is an enlarged sectional view showing a portion "B" in fig. 16. Fig. 10 is a sectional view taken along line II-II' in fig. 11.

Referring to fig. 4 to 11, a vertical conductive structure 400 and a mark pattern 420 may be formed on the first carrier substrate C1.

First, as shown in fig. 4, the insulating layer 20 and the seed layer 30 may be sequentially formed on the first carrier substrate C1, and the photoresist layer 40 may be formed on the seed layer 30.

In an example embodiment, the first carrier substrate C1 may include a wafer substrate as a base for disposing a plurality of semiconductor chips and forming a sealing member on or over the semiconductor chips. The first carrier substrate C1 may have a shape corresponding to a wafer on which a semiconductor process is performed. For example, the first carrier substrate C1 may include a silicon substrate, a glass substrate, a nonmetallic or metallic plate, or the like.

The first carrier substrate C1 may include a package region PR on which the semiconductor chip is mounted and a dicing region CR adjacent to or surrounding the package region PR. As described below, the lower redistribution layer 100 and the sealing member formed on the first carrier substrate C1 may be cut along a cutting region CR dividing a plurality of encapsulation regions PR so as to be individualized or singulated.

Further, the first carrier substrate C1 may include a first region R1 overlapping the semiconductor chip and a second region R2 adjacent to the first region R1 or surrounding the first region R1. The second region R2 may be a fan-out region outside a region where the semiconductor chip is disposed.

The insulating layer 20 may be formed on the first carrier substrate C1 by a spin coating process, a vapor deposition process, or the like. For example, the insulating layer 20 may include a dielectric material such as oxide, nitride, carbide, carbonitride, polyimide derivatives, polybenzoxazole (PBO), and the like. The insulating layer 20 may be formed to have a thickness in the range of about 0.1 μm to about 10 μm.

The insulating layer 20 may include a polymer tape used as a temporary adhesive. The insulating layer 20 may include a material that may lose adhesive strength when irradiated with light or heated. For example, the insulating layer 20 may be peeled off from the first carrier substrate C1 such as a glass substrate by irradiation of ultraviolet rays or visible light.

The seed layer 30 may be formed on the insulating layer 20 through a sputtering process. The seed layer 30 may have a multi-layered structure in which different metal layers are stacked. The seed layer 30 may be formed to have a thickness in a range of about 0.1 μm to about 0.5 μm. For example, the seed layer 30 may include a first seed layer and a second seed layer stacked on the first seed layer. The first seed layer may include titanium (Ti), and the second seed layer may include copper (Cu). The first seed layer may have a thickness of about 80nm and the second seed layer may have a thickness of about 200 nm.

As shown in fig. 5 and 6, the photoresist layer 40 may be patterned to form a photoresist pattern having openings 41, the openings 41 exposing vertical conductive structure regions on the seed layer 30, and an electroplating process may be performed on the exposed regions of the seed layer 30 to fill the openings 41 with a conductive material to form the vertical conductive structures 400, respectively. For example, the vertical conductive structure 400 may include a metal material such as copper (Cu).

As shown in fig. 7, the photoresist pattern may be removed from the first carrier substrate C1 to form a vertical conductive structure 400 in the second region R2 of the first carrier substrate C1. The vertical conductive structures 400 may be spaced apart from each other on the seed layer 30 in the second region R2.

As shown in fig. 8 and 9, a first laser may be irradiated on the seed layer 30 in the second region R2 to remove a portion of the seed layer between the vertical conductive structures 400 and exposed by the vertical conductive structures 400, thereby forming a seed layer pad 410. Meanwhile, as a portion of the seed layer in the second region R2 is removed, the seed layer pad 412 for the marking pattern may remain in the first region R1.

Portions of the seed layer 30 in the second region R2 may be partially removed by a laser lift-off device. The laser lift-off apparatus may irradiate the first laser onto the seed layer 30 in the second region R2. The laser lift-off device may include an excimer laser device, a diode pumped solid state laser device, or the like. The first laser may include a laser having a wavelength of about 308nm or about 343 nm. The first laser may have a laser sectional shape such as a gaussian beam or a flat-top beam.

When the first laser is irradiated onto the seed layer 30, only a thin seed layer portion on the polyimide insulating layer 20 exposed by the vertical conductive structure 400 may absorb photon energy by a shock wave effect, and may then be peeled off from the insulating layer 20. At this time, the vertical conductive structure 400 including copper may not react with the first laser and may maintain an original shape.

Accordingly, seed layer pad 410 left by or remaining after laser lift-off may be located under vertical conductive structure 400. The diameter of the seed layer pad 410 may be the same as the diameter of the vertical conductive structure 400 or smaller than the diameter of the vertical conductive structure 400.

Then, as shown in fig. 9 to 11, a second laser may be irradiated onto the seed layer pad 412 for the marking pattern in the first region R1 to form a marking pattern 420.

The marking pattern 420 may be formed by a laser processing apparatus. The laser processing device may include an excimer laser device, a diode pumped solid state laser device, or the like. The second laser may include a laser having a wavelength of about 355nm or about 532 nm.

The laser processing apparatus may include a scanner optical system to form intaglio patterns 422 for marking patterns in the seed layer pads 412. Intaglio patterns 422 may represent information about the manufacturer, date of manufacture, serial number, etc. The second laser may form an opening penetrating the seed layer pad 412 to define a seed layer dummy pattern 423, and the intaglio pattern 422 may be defined by the opening.

Referring to fig. 12, at least one semiconductor chip 200 may be disposed on the first carrier substrate C1.

In an example embodiment, the conductive bump 220 may be formed on the chip pad 210 of the semiconductor chip 200, and the semiconductor chip 200 may be disposed such that the back surface 204 opposite to the front surface 202 (i.e., active surface) on which the chip pad 210 is formed faces the first carrier substrate C1. The semiconductor chip 200 may be disposed in the first region R1, i.e., the fan-in region of the first carrier substrate C1. A plurality of vertical conductive structures 400 may be disposed around the second region R2 of the semiconductor chip 200.

Each of the conductive bumps 220 may include a pillar bump formed on the chip pad 210 of the semiconductor chip 200 and a solder bump formed on the pillar bump. Alternatively, each of the conductive bumps 220 may include a solder bump formed on the chip pad 210 of the semiconductor chip 200.

In an example embodiment, the semiconductor chip 200 may be attached to the marking pattern 420 on the insulating layer 20 through the adhesive film 230. For example, the adhesive film 230 may include a wafer adhesive film (DAF). The thickness of the adhesive film 230 may be in the range of about 30 μm to about 120 μm.

For example, the adhesive film 230 may be attached to the back surface 204 of the semiconductor chip 200, and the semiconductor chip 200 attached with the adhesive film 230 may be attached to the marking pattern 420 on the insulating layer 20 by a thermal pressing process. The semiconductor chip 200 may be pressed onto the marking pattern 420 by a wafer bonding tool and heated to a high temperature by a heater block in a support system supporting the first carrier substrate C1. A portion of the DAF having fluidity due to the pressure and temperature of the hot pressing process may at least partially fill the intaglio pattern 422 of the marking pattern 420, i.e., the opening of the marking pattern 420.

As shown in fig. 13 and 14, a sealing material 50 may be formed on the first carrier substrate C1 to cover the semiconductor chip 200 and the plurality of vertical conductive structures 400, and an upper portion of the sealing material 50 may be partially removed to form a sealing member 300, the sealing member 300 exposing the conductive bumps 220 on the front surface 202 of the semiconductor chip 200 and the upper surfaces of the plurality of vertical conductive structures 400.

The sealing material 50 may be formed to cover the front surface 202 of the semiconductor chip 200 and the upper surfaces of the plurality of vertical conductive structures 400. For example, the sealing material 50 may include an Epoxy Molding Compound (EMC).

The upper portion of the sealing material 50 may be partially removed by a grinding process. With the upper portion of the sealing material 50 removed, the conductive bumps 220 and the plurality of vertical conductive structures 400 on the front surface 202 of the semiconductor chip 200 may be exposed from the second surface 304 of the sealing member 300. The sealing member 300 may include a first sealing portion on the front surface 202 of the semiconductor chip 200 or covering the front surface 202 of the semiconductor chip 200, and a second sealing portion on the side surface of the semiconductor chip 200 or covering the side surface of the semiconductor chip 200. The upper surface of the conductive bump 220 on the front surface 202 of the semiconductor chip 200 may be exposed through the first sealing portion of the sealing member 300.

The sealing member 300 may cover an outer surface of the vertical conductive structure 400. The sealing member 300 may cover an outer surface of the seed layer pad 410 under the vertical conductive structure 400. The sealing member 300 may cover the outer surface of the marking pattern 420.

Referring to fig. 15, a lower redistribution layer 100 having first redistribution wirings 102 may be formed on the second surface 304 of the sealing member 300 and the front surface 202 of the semiconductor chip 200.

In an example embodiment, after the first lower insulating layer 110 is formed on the second surface 304 of the sealing member 300 and the front surface of the semiconductor chip 200, the first lower insulating layer 110 may be patterned to form an opening exposing the vertical conductive structure 400 and the conductive bump 220. Some of the openings of the patterned first lower insulating layer 110 may expose the vertical conductive structure 400, while other of the openings may expose the conductive bump 220.

After forming the seed layer on the vertical conductive structure 400 and the conductive bump 220 and in the opening, the seed layer may be patterned, and an electroplating process may be performed to form the first lower redistribution line 112. Accordingly, at least a portion of the first lower redistribution line 112 may directly contact the end of the vertical conductive structure 410 and the conductive bump 220 through the opening of the first lower insulating layer 110. As used herein, when components or layers are referred to as being "directly connected" or "directly connected" to each other, there are no intervening components or layers present.

The first lower insulating layer may be formed by a vapor deposition process, a spin coating process, or the like. The first lower redistribution wire may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof. The first lower redistribution line may be formed by an electroplating process, an electroless plating process, a vapor deposition process, or the like.

Similarly, after forming the second lower insulating layer 120 on the first lower insulating layer 110, the second lower insulating layer 120 may be patterned to form an opening exposing the first lower redistribution line 112. Then, the second lower redistribution wire 122 may be formed on the second lower insulating layer 120 to directly contact the first lower redistribution wire 112 through an opening of the second lower insulating layer.

Then, after forming the third lower insulating layer 130 on the second lower insulating layer 120, the third lower insulating layer 130 may be patterned to form an opening exposing the second lower redistribution line 122. Then, the third lower redistribution wire 132 may be formed on the third lower insulating layer 130 to directly contact the second lower redistribution wire 122 through an opening of the third lower insulating layer 130.

Then, a package pad (not shown) may be formed on the third lower redistribution wire 132, and a fourth lower insulating layer 140 may be formed on the third lower insulating layer 130 to expose at least a portion of the package pad on the third lower redistribution wire 132. The fourth lower insulating layer 140 may serve as a passivation layer.

Referring to fig. 16 to 19, an upper redistribution wiring layer 510 having a second redistribution wiring 502 electrically connected to the vertical conductive structure 400 may be formed on the first surface 302 of the sealing member 300.

As shown in fig. 16 and 17, after the first carrier substrate C1 is removed, the structure of fig. 15 may be flipped, and a second redistribution wire 502 may be formed on the first surface 302 of the sealing member 300 so as to be electrically connected to the vertical conductive structure 400.

For example, the insulating layer 20 may be irradiated with UV light through the first carrier substrate C1 to remove the first carrier substrate C1, and the lower redistribution layer 100 may be disposed on the second carrier substrate C2. In this case, the marking pattern 420 in the first region R1 may be exposed from the first surface 302 of the sealing member 300 or at the first surface 302 of the sealing member 300. The upper surface of the marking pattern 420 may be coplanar with the first surface 302 of the sealing member 300. Further, the seed layer pads 410 bonded to the respective ends of the vertical conductive structure 400 in the second region R2 may be exposed from the first surface 302 of the sealing member 300 or at the first surface 302 of the sealing member 300.

Then, a photoresist pattern 60 having an opening 61 may be formed on the first surface 302 of the sealing member 300, the opening 61 exposing the seed layer pad 410 bonded to one end of the vertical conductive structure 400, and an electrolytic plating process may be performed to fill the opening 61 of the photoresist pattern 60 with a conductive material to form the second redistribution wire 502.

For example, the second redistribution wire 502 may include a first plating pattern 504 and a second plating pattern 506 sequentially formed on the seed layer pad 410. In this case, the first plating pattern 504 may include nickel (Ni), and the second plating pattern 506 may include gold (Au). When the seed layer pad 410 includes a titanium (Ti) seed layer and a copper (Cu) seed layer, the titanium (Ti) seed layer exposed from the first surface 302 of the sealing member 300 or at the first surface 302 of the sealing member 300 may be removed, and then the first and second plating patterns 504 and 506 may be sequentially formed on the copper (Cu) seed layer.

Alternatively, the second redistribution line 502 may include a single plating pattern on the seed layer pad 410. In this case, the plating pattern may include gold (Au). When the seed layer pad 410 includes a titanium (Ti) seed layer and a copper (Cu) seed layer, the titanium (Ti) seed layer exposed from the first surface 302 of the sealing member 300 or at the first surface 302 of the sealing member 300 may not be removed, and a gold (Au) plating pattern may be formed on the titanium (Ti) seed layer.

As shown in fig. 18, the photoresist pattern 60 may be removed to form a second redistribution wire 502 on the first surface 302 of the sealing member 300. The second redistribution wirings 502 may be electrically connected to seed layer pads 410 bonded to respective ends of the vertical conductive structures 400.

As shown in fig. 19, after forming the upper redistribution layer 510 as an upper insulating layer on the first surface 302 of the sealing member 300, the upper redistribution layer 510 may be patterned to form openings 511 exposing the second redistribution wirings 502, respectively. Accordingly, the upper redistribution wire 510 having the second redistribution wire 502 stacked in one layer may be formed on the first surface 302 of the sealing member 300. The second redistribution wiring 502 may correspond to an uppermost redistribution wiring, and may function as a bonding pad on which a solder bump for electrical connection with the second package is provided.

Then, the second carrier substrate C2 may be removed, and external connection members 550 (see fig. 1) may be formed on the lower surface, i.e., the package pad on the outer surface of the lower redistribution layer 100.

The lower redistribution routing layer 100 may then be singulated or singulated by a sawing process to complete the fanout wafer level package 10 of fig. 1, including the sealing member 300, the lower redistribution routing layer 100 formed on the lower surface 304 of the sealing member 300, and the upper redistribution routing layer 510 formed on the upper surface 302 of the sealing member 300.

Fig. 20 is a cross-sectional view illustrating a semiconductor package according to an example embodiment. The semiconductor package may be substantially the same as the semiconductor package described with reference to fig. 1, except for an additional second package. Accordingly, the same reference numerals may be used to refer to the same or similar elements, and any further repetitive explanation concerning the above elements will be omitted.

Referring to fig. 20, the semiconductor package 11 may include a first package and a second package 600 stacked on the first package. The first package may include a lower redistribution layer 100, a semiconductor chip 200, a sealing member 300, and an upper redistribution layer 510. The first enclosure may be substantially the same or similar to the unit package 10 described with reference to fig. 1.

In an example embodiment, the second package 600 may include a second package substrate 610, a plurality of second semiconductor chips 620 mounted on the second package substrate 610, and a sealing member 640 covering the second semiconductor chips 620 on the second package substrate 610.

The second package 600 may be stacked on the first package via the conductive connection member 650. For example, the conductive connection member 650 may include solder balls, conductive bumps, and the like. The conductive connection member 650 may be disposed between the second redistribution wire 502 of the upper redistribution wire layer 510 and the second connection pad 614 of the second package substrate 610. Accordingly, the first and second packages 600 may be electrically connected to each other through the conductive connection member 650.

The plurality of second semiconductor chips 620a, 620b, 620c, and 620d may be sequentially stacked on the second package substrate 610 by an adhesive member. The bonding wires 630 may connect the second chip pads 622 of the second semiconductor chip 620 to the first connection pads 612 of the second package substrate 610. The second semiconductor chip 620 may be electrically connected to the second package substrate 610 by bonding wires 630.

Although the second package 600 including four semiconductor chips mounted by the wire bonding method is illustrated, it should be understood that the number of semiconductor chips in the second package and/or the mounting method or the bonding method is not limited thereto.

In an example embodiment, the semiconductor package 11 may further include a heat sink (not shown) stacked on the second package 600. A heat sink may be provided on the second package 600 to dissipate heat from the first and second packages to the outside. The heat spreader may be attached to the second package 600 through the use of a Thermal Interface Material (TIM).

Fig. 21 is a cross-sectional view illustrating a semiconductor package according to an example embodiment. The semiconductor package may be substantially the same as the semiconductor package 10 described with reference to fig. 1, except for the connection relationship between the semiconductor chip and the lower redistribution wiring layer. Accordingly, the same reference numerals may be used to refer to the same or similar elements, and any further repetitive explanation concerning the above elements will be omitted.

Referring to fig. 21, the semiconductor package 12 may include a lower redistribution routing layer 100, a semiconductor chip 200 disposed on the lower redistribution routing layer 100, a sealing member 300 covering at least a side surface of the semiconductor chip 200 on the lower redistribution routing layer 100, a plurality of vertical conductive structures 400 penetrating the sealing member 300, a marking pattern 420 on the semiconductor chip 200, and an upper redistribution routing layer 510 disposed on the sealing member 300. In addition, the semiconductor package 12 may further include an external connection member 550 disposed on an outer surface of the lower redistribution layer 300.

In an example embodiment, the semiconductor chip 200 may have a plurality of chip pads 210 on the first surface 202 (i.e., active surface). The semiconductor chip 200 may be accommodated in the sealing member 300 such that the first surface 202 on which the chip pad 210 is formed faces down the redistribution layer 100. The sealing member 300 may extend on or cover a side surface of the semiconductor chip 200. The first surface 202 of the semiconductor chip 200 may be exposed by the sealing member 300 from the second surface 304 of the sealing member 300 or at the second surface 304 of the sealing member 300, and the second surface 204 opposite to the first surface 202 of the semiconductor chip 200 may be exposed by the sealing member 300 from the first surface 302 of the sealing member 300 or at the first surface 302 of the sealing member 300.

In an example embodiment, the lower redistribution layer 100 may be disposed on the second surface 304 of the encapsulation member 300 and the first surface 202 of the semiconductor chip 200. The lower redistribution layer 100 may include a plurality of first redistribution wirings 102. The first redistribution line 102 may be electrically connected to the chip pad 210 and the vertical conductive structure 400 of the semiconductor chip 200, respectively. The first redistribution trace 102 may be disposed on the front surface 202 of the semiconductor chip 200 and the second surface 304 of the sealing member 300 to serve as a front-surface redistribution trace. Accordingly, the lower redistribution routing layer 100 may be a front side redistribution routing layer of a fan-out package.

Hereinafter, a method of manufacturing the semiconductor package of fig. 21 will be described.

Fig. 22 to 26 are sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.

Referring to fig. 22, first, the same or similar process as that described with reference to fig. 4 to 12 may be performed to form the vertical conductive structure 400 and the marking pattern 420 on the first carrier substrate C1, and to dispose at least one semiconductor chip 200 on the first carrier substrate C1.

In an example embodiment, the semiconductor chip 200 may be disposed in the fan-in region R1 of the first carrier substrate C1. The vertical conductive structure 400 may be disposed in the second region R2 surrounding the semiconductor chip 200. The semiconductor chip 200 may be disposed such that the back surface 204 opposite the front surface 202 (i.e., active surface) on which the chip pads 210 are formed faces the first carrier substrate C1.

Referring to fig. 23 and 24, a sealing material 50 may be formed on the first carrier substrate C1 to cover the semiconductor chip 200 and the plurality of vertical conductive structures 400, and an upper portion of the sealing material 50 may be partially removed to form a sealing member 300 exposing the front surface 202 of the semiconductor chip 200 and upper surfaces of the plurality of vertical conductive structures 400.

The upper portion of the sealing material 50 may be partially removed by a grinding process. With the upper portion of the sealing material 50 removed, the chip pads 210 and the ends of the plurality of vertical conductive structures 410 on the front surface 202 of the semiconductor chip 200 may be exposed from the second surface 304 of the sealing member 300. The sealing member 300 may cover a side surface of the semiconductor chip 200.

Referring to fig. 25, the same or similar process as described with reference to fig. 15 may be performed to form the lower redistribution layer 100 having the first redistribution wire 102 on the second surface 304 of the sealing member 300 and the front surface 202 of the semiconductor chip 200.

In an example embodiment, after forming the first lower insulating layer 110 on the second surface 304 of the sealing member 300, the first lower insulating layer 110 may be patterned to form openings exposing the chip pads 210 and the vertical conductive structures 400 of the semiconductor chip 200, respectively. Some of the openings of the patterned first lower insulating layer 110 may expose the vertical conductive structure 400, while others of the openings may expose the chip pad 210.

After forming the seed layer on the vertical conductive structure 400 and the chip pad 210 and in the opening, the seed layer may be patterned, and an electroplating process may be performed to form the first lower redistribution line 112. Accordingly, at least a portion of the first lower redistribution line 112 may directly contact the vertical conductive structure 400 and the chip pad 210 through the opening of the first lower insulating layer 110.

Then, a package pad (not shown) may be formed on the third lower redistribution line 132, and a fourth lower insulating layer 140 may be formed on the third lower redistribution line layer 132 to expose at least a portion of the package pad. The fourth lower insulating layer 140 may serve as a passivation layer.

Referring to fig. 26, the same or similar process as that described with reference to fig. 16 to 19 may be performed to form an upper redistribution layer 510 having second redistribution wirings 502 electrically connected to the vertical conductive structures 400 on the upper surface 302 of the sealing member 300, and external connection members 550 respectively electrically connected to the first redistribution wirings 102 are formed on the outer surface of the lower redistribution layer 100, completing the fan-out-type wafer level package 12 of fig. 21.

The semiconductor packages described herein may include semiconductor devices such as logic devices or memory devices. The semiconductor package may include a logic device such as a Central Processing Unit (CPU), a Main Processing Unit (MPU), or an Application Processor (AP), and a volatile memory device such as a DRAM device, an HBM device, or a nonvolatile memory device such as a flash memory device, a PRAM device, an MRAM device, a ReRAM device, or the like.

Spatially relative terms, such as "below," "lower," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The foregoing is illustrative of example embodiments and is not to be construed as limiting the example embodiments. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims.

Claims

1. A semiconductor package, the semiconductor package comprising:

A lower redistribution routing layer having a first region and a second region adjacent to the first region, the lower redistribution routing layer including a first redistribution routing;

A semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wiring;

a sealing member on a side surface of the semiconductor chip on the lower redistribution wiring layer;

A plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution routing layer and electrically connected to the first redistribution routing;

a mark pattern on the semiconductor chip;

a seed layer pad on respective ends of the vertical conductive structure, the ends being exposed by the sealing member at an upper surface of the sealing member; and

And an upper redistribution routing layer on the sealing member and the marking pattern, the upper redistribution routing layer including a second redistribution routing electrically connected to the plurality of vertical conductive structures.

2. The semiconductor package of claim 1, wherein an upper surface of the marking pattern is coplanar with an upper surface of the sealing member.

3. The semiconductor package of claim 1, wherein an upper surface of the seed layer pad is coplanar with or lower than an upper surface of the sealing member.

4. The semiconductor package of claim 1, wherein the sealing member is on a side surface of the marking pattern.

5. The semiconductor package of claim 1, wherein the marking pattern comprises a first seed layer and a second seed layer stacked on the first seed layer.

6. The semiconductor package of claim 5, wherein the first seed layer comprises copper and the second seed layer comprises titanium.

7. The semiconductor package of claim 5, wherein the seed layer pads comprise the first seed layer and the second seed layer stacked on the first seed layer, respectively, or wherein the seed layer pads comprise the first seed layer, respectively.

8. The semiconductor package of claim 1, wherein the thickness of the marking pattern is 0.1 to 0.5 microns.

9. The semiconductor package according to claim 1, wherein the marking pattern is attached to a back surface of the semiconductor chip via an adhesive film, wherein the back surface of the semiconductor chip is opposite to the lower redistribution wiring layer.

10. The semiconductor package of claim 1, wherein the semiconductor chip is a first semiconductor chip of a first package, and the semiconductor package further comprises:

A second package on the upper redistribution layer,

Wherein the second package includes a package substrate and at least one second semiconductor chip stacked on the package substrate.

11. A semiconductor package, the semiconductor package comprising:

A lower redistribution routing layer including a first redistribution routing;

a semiconductor chip on the lower redistribution routing layer, wherein a first surface of the semiconductor chip including a chip pad faces the lower redistribution routing layer;

a sealing member on the semiconductor chip and on the lower redistribution wiring layer, wherein the sealing member exposes a second surface of the semiconductor chip opposite the first surface;

A plurality of vertical conductive structures penetrating the sealing member and electrically connected to the first redistribution routing;

a marking pattern on the second surface of the semiconductor chip; and

An upper redistribution routing layer on the sealing member and the marking pattern, the upper redistribution routing layer including a second redistribution routing electrically connected to the plurality of vertical conductive structures,

Wherein an upper surface of the marking pattern is coplanar with an upper surface of the sealing member.

12. The semiconductor package of claim 11, wherein the sealing member is on a side surface of the marking pattern.

13. The semiconductor package of claim 11, wherein the marking pattern comprises a first seed layer and a second seed layer stacked on the first seed layer.

14. The semiconductor package of claim 13, wherein the first seed layer comprises copper and the second seed layer comprises titanium.

15. The semiconductor package of claim 11, wherein the thickness of the marking pattern is 0.1 to 0.5 microns.

16. The semiconductor package of claim 11, further comprising:

A seed layer pad on respective ends of the vertical conductive structure, the ends being exposed by the sealing member at an upper surface of the sealing member.

17. The semiconductor package of claim 16, wherein an upper surface of the seed layer pad is coplanar with or lower than an upper surface of the sealing member.

18. The semiconductor package of claim 16, wherein the sealing member is on a side surface of the seed layer pad.

19. The semiconductor package of claim 16, wherein:

the seed layer pads respectively comprise a first seed layer and a second seed layer stacked on the first seed layer, or the seed layer pads respectively comprise the first seed layer; and

Wherein the marking pattern includes the first seed layer and the second seed layer.

20. The semiconductor package of claim 11, wherein the marking pattern is attached to the second surface of the semiconductor chip by an adhesive film.